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APU, SCU, Global Timer, GIC, WDT Cortex-A9 MPCore, Part DDI 0407F (ID043010) Copyright 2008-2010 ARM. L2 Cache DMAC SDT TTC USB ARM AMBA Level 2 Cache Controller (L2C-310) Copyright 2007-2010 ARM. ARM AMBA DMA Controller DMA-330, ARM part DDI 0424C (ID080710) Copyright 2007, 2009-2010 ARM Limited, All rights reserved. Part Number: T-CS-PE-0004-100 2008 Cadence Design Systems, Inc. All rights reserved Triple Timer Counter (TTC) 2000 Cadence Design Systems, Inc. All rights reserved. Chipidea/Synopsys CI13612a (CI133210A) HighSpeed USB OnTheGo Controller Core, Copyright 2009 Synopsys, Inc. Synopsys proprietary, used with permission. Gigabit Ethernet MAC (GEM), Part Number: T-CS-ET-0005-100 2000 Cadence Design Systems, Inc. All rights reserved Arasan SD2.0/ SDIO2.0/ MMC3.31 AHB Host Controller Copyright 2009 Arasan Systems, Inc. Part Number: T-CS-PE-0007-100 2000 Cadence Design Systems, Inc. All rights reserved. Part Number: T-CS-PE-0009-100 2000 Cadence Design Systems, Inc. All rights reserved. Part Number: T-CS-PE-0001-100 2003 Cadence Design Systems, Inc. All rights reserved. IntelliTM DDR Arbiter Interface, Part Number: DS-114-pkg16 2010 Virage Logic Corporation. All rights reserved. ARM Part number PL353 - DDI 0380G, Copyright 2005-2007 ARM Limited. All rights reserved.
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Chapter 5
Interconnect
5
5.1.1
Interconnect
Introduction
The Interconnect comprises multiple switches to connect system resources using AXI point-to-point channels for communicating addresses, data and response transactions between master and slave clients. This ARM AMBA 3.0 interconnect implements a full array of the interconnect communications capabilities and overlays for QoS, debug and test monitoring. The Interconnect manages multiple outstanding transactions and is architected for low-latency paths for the ARM CPUs and a high-throughput path for the PL Fabric master controllers.
5.1.2
Features
The PS Interconnect is the primary mechanism for data communications. PS Interconnect is based on AXI high performance datapath switches o o o o Snoop Control Unit that encompasses the CPU, ACP and HP interfaces OCM Interconnect Central and Slave/Master Interconnect Bridges/Switches AHB and APB Interconnect Bridges/Switches
PS-PL Interfaces o o o AXI_ACP, one cache coherent master port for PL Fabric AXI_HP, four high performance/bandwidth master ports for PL Fabric AXI_GP, four general purpose ports (two master ports and two slave ports)
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Chapter 5: Interconnect
5.1.3
PL Fabric
ASYNC
PL Fabric
PL Fabric
Cortex A9
NEON/FPU Jazelle, Thumb-2, MMUs, L1 i/dCaches
PL Fabric
Masters
Data
32-bit
DMA Controller
64-bit CPU_2x M
M1
ASYNC
CPU_1x DevC M
4 8 8
M3
DAP M
1
FIFO
FIFO
FIFO
FIFO
S0
S1
S2
S3 32-bit
RAM
Slave Interconnect
CPU_2x M
16
M0 S0 S1 S2 S3
4
M1
PL to Memory Interconnect
DDR_2x M0 M1
64-bit
64-bit
S
64-bit
S1 S0 S2
M2
L2 Cache
8 8
512 kB
CPU_6x4x M1
8
Central Interconnect
M0
64-bit M1
CPU_2x M2
M0
ASYNC ASYNC ASYNC
16
64-bit
S0 S0 S1
OCM Interconnect
64-bit M
S1
ASYNC
32-bit M0
8
Master Interconnect
M1
8
CPU_2x
ASYNC
CPU_2x
M2
4
M3
1
32-bit
ASYNC ASYNC
32-bit
S1
S0 S0 S1 S S
256 kB
128-bit CPU_2x
PL Fabric
On-chip RAM
Slaves
Reg & Data CPU_1x
APB Slaves
Registers CPU_1x
64-bit
S3 S2 S0
64-bit
S1 DDR_3x
64-bit
DDR DRAM
Interconnect Masters
The interconnect masters are shown at the top of the figure, Interconnect Block Diagram. The address map for each of these masters are defined in Chapter 4, System Addresses.
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Chapter 5: Interconnect
Central Interconnect
The Interconnect comprises multiple switches to connect system resources using AXI point-to-point channels for communicating addresses, data and response transactions between master and slave clients. This ARM AMBA 3.0 interconnect implements a full array of the interconnect communications capabilities and overlays for QoS, debug and test monitoring. The Interconnect manages multiple outstanding transactions and is architected for low-latency paths for the ARM CPUs and a high-throughput path for the PL Fabric master controllers.
5.1.5
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Chapter 5: Interconnect
PS APU
PS and PL IO Peripherals
CPUs
CPU_6x4x
Async
Interconnect Switch
Masters
CPU_1x
DMA Controller
CPU_2x
CPU_2x
CPU_3x2x
On-chip RAM
L2 Cache
Central Interconnect
CPU_2x
Interconnect Switch
CPU_2x
Async
Async
M_AXI_GP
Slaves
CPU_1x
APB Slaves
CPU_1x
Async
DDR DRAM
DDR_3x
5.2
Arbitration
T he A XI interconnect uses a two-level arbitration scheme to resolve contention. T he first-level arbitration is based on the priority indicated by the QoS signals from the master. T he highest QoS value has the highest priority. T he second-level arbitration is based on a least recently granted (L R G ) scheme and is used when multiple requests are pending with the same QoS signal value. The AXI_HP interfaces can generate the QoS signals dynamically; that is, the QoS value can be changed between one transaction and the next. The QoS values for all the other AXI masters are statically controlled by a register setting. In each case, there are separate controls for read and write transactions. T he interconnect uses all four QoS signals except where the interconnect attaches to the D D R memory controller, w hich takes only the most significant Q oS signal to determine if a request is urgent. T he other QoS signals are not used. R efer to the D D R memory controller chapter for more details. The QoS mechanism is based on ARMs QoS-301 which is an extension to the NIC-301 network interconnect. For more information, refer to CoreLink QoS-301 Network Interconnect Advanced Quality of Service technical reference manual.
5.3
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Chapter 5: Interconnect
5.3.1
Interface Name M_AXI_GP0
Table 1: PS-PL AXI Interfaces Data Width Interface Description PS 32-bit M_AXI_GP1 S_AXI_GP0 S_AXI_GP1 S_AXI_ACP0 S_AXI_HP0 S_AXI_HP1 S_AXI_HP2 S_AXI_HP3 32- or 64-bit 32-bit 32- or 64-bit General Purpose (AXI_GP) Accelerator Coherent Port, cache-coherent transaction (ACP) High Performance ports (AXI_HP) with read/write FIFOs and two dedicated memory ports on DDR controller and a path to the OCM. General Purpose (AXI_GP) PS PL Fabric PL Fabric PL Fabric PL Fabric PL Fabric PL Fabric PL Fabric Master Slave PL Fabric PL Fabric PS PS PS PS PS PS PS Well over a thousand signals are used to implement these nine interfaces. Signals
5.3.2
Block Diagram
PS AXI Interconnect
M_AXI_GP{0, 1}
Slave Controller
Slave Controller
S_AXI_HP{0, 1, 2, 3}
S_AXI_ACP
S_AXI_GP{0, 1}
SCU
PS AXI Interconnect
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Master Controller
Chapter 5: Interconnect
5.3.3
XILINX CONFIDENTIAL DISCLOSED UNDER NDA PS-PL AXI Channel and Signals
General Purpose Interface High Performance Interface, Advanced Coherent Port x2, S_AXI_GP{0,1} x4, S_AXI_HP{0:3} with FIFOs x1, S_AXI_ACP
PL Fabric
Slaves
Processing System
Masters M_AXI_GP{0,1}
_ACLK _ARESETN
Interface clk rst
PL Fabric
Masters
_ACLK _ARESETN
Processing System
Slaves
Interface clk rst
Receive
Initiate
Master Controller Controllers Controller Master Controller Master Master Controller Master Controller
Initiate
Receive
Receive
Receive
Receive
Initiate
8 3 8 8
HP_WR_ISSUECAP1_EN HP_RD_ISSUECAP1_EN HP_RCOUNT [7:0] ACP_RACOUNT [2:0] HP_WCOUNT [7:0] HP_WACOUNT [5:0]
Clock/ Reset
I O
{GP,HP,ACP}_ACLK {GP,HP,ACP}_ARESETN
I O
{GP,HP,ACP}_ARADDR [31:0]
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Chapter 5: Interconnect
Zynq-7000 EPP Technical Reference Manual www.xilinx.com UG585 (DRAFT) February 15, 2012
Chapter 5: Interconnect
5.3.4
Table 2: AXI Channel Signal Types Signal VALID READY Channel Type all channels all channels AR AW AR AW AW AR AW AR AW AR AW AR AW AR R, W Name Channel clock enable Slave accepts transfer Byte Address Direction IR IR IR IR IR IR IR IR IR IR Description The valid signal is a clock enable. It is asserted when valid signals are being driven by the channel transmitter. The receiver asserts the ready signal when it has latched the signals from the transmitter. Address of the first transfer in a burst transaction. The associated control signals are used to determine the addresses of the remaining data transfers in the burst. 32-bit byte address. Exact number of data transfer cycles in a burst transfer. Byte lane strobes indicate which byte lanes to update. Burst Length of transactions. The burst type, coupled with the size information, details how the address for each transfer within the burst is calculated. Defines the atomic characteristics of the transfer. This signal indicates the bufferable, cacheable write-through, write-back and allocate attributes of the transaction. Indicates that the transaction is occurring with the interconnect operating in a secure mode. Final transfer in a burst.
ADDR
Data Beats Burst Size, words Burst Type Lock Type Caching Indicators TrustZone Security Last data cycle
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Chapter 5: Interconnect
5.3.5
5.4
AXI_HP Interfaces
The four AXI_HP interfaces provides PL bus masters with high bandwidth datapaths to the DDR and OCM memories. Each interface includes two FIFO buffers for read and write traffic. The PL to Memory Interconnect routes the high-speed AXI_HP ports to two DDR memory ports or the OCM. The AXI_HP interfaces are also referenced as AFI (AXI FIFO Interface), to emphasize their buffering capabilities.
5.4.1
Features
The interfaces are designed to provide a high throughput data path between PL masters and PS memories including the DDR and on-chip RAM. Main features: 32- or 64-bit data wide master interfaces (independently programmed per port) Efficient resizing in 32-bit widths Efficient upsizing to 64-bits for aligned 32-bit transfers in 32-bit slave interface configuration mode. Automatic Expansion to 64-bits for unaligned 32-bit transfers in 32-bit slave interface configuration mode Dynamic command upsizing translation between 32-bit and 64-bit interfaces, controllable via AxCACHE[1] Programmable acceptance by Interconnect capability, separately for read and write commands Programmable release threshold of write commands Asynchronous clock frequency domain crossing for all AXI interfaces between PL Fabric and PS Smoothing out of long-latency transfers using 1 kB (128 by 64 bit) data FIFOs for both reads and writes QoS signaling available from PL Fabric ports Command and Data FIFO fill-level counts available to PL Fabric Standard AXI 3.0 interfaces supported Large slave interface read acceptance capability in the range of 14 to 70 commands (burst length dependent) Large slave interface write acceptance capability in the range of 8 to 32 commands (burst length dependent)
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Chapter 5: Interconnect
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