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XILINX CONFIDENTIAL DISCLOSED UNDER NDA

Zynq-7000 EPP TRM


Chapter 5: Interconnect

XTP159 (Draft) February 15, 2012

NOTICE: This pre-release document contains confidential and proprietary information of Xilinx, Inc. and is being disclosed to you as a participant in an early access program, under obligation of confidentiality. You may print one (1) copy of this document for evaluation purposes. You may not modify, distribute, or disclose this material to anyone, including your employees, coworkers, or contractors (these individuals must apply for separate access to the program). This document contains preliminary information and is subject to change without notice. Information provided herein relates to products and/or services not yet available for sale, and provided solely for information purposes and are not intended, or to be construed, as an offer for sale or an attempted commercialization of the products and/or services referred to herein.

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APU, SCU, Global Timer, GIC, WDT Cortex-A9 MPCore, Part DDI 0407F (ID043010) Copyright 2008-2010 ARM. L2 Cache DMAC SDT TTC USB ARM AMBA Level 2 Cache Controller (L2C-310) Copyright 2007-2010 ARM. ARM AMBA DMA Controller DMA-330, ARM part DDI 0424C (ID080710) Copyright 2007, 2009-2010 ARM Limited, All rights reserved. Part Number: T-CS-PE-0004-100 2008 Cadence Design Systems, Inc. All rights reserved Triple Timer Counter (TTC) 2000 Cadence Design Systems, Inc. All rights reserved. Chipidea/Synopsys CI13612a (CI133210A) HighSpeed USB OnTheGo Controller Core, Copyright 2009 Synopsys, Inc. Synopsys proprietary, used with permission. Gigabit Ethernet MAC (GEM), Part Number: T-CS-ET-0005-100 2000 Cadence Design Systems, Inc. All rights reserved Arasan SD2.0/ SDIO2.0/ MMC3.31 AHB Host Controller Copyright 2009 Arasan Systems, Inc. Part Number: T-CS-PE-0007-100 2000 Cadence Design Systems, Inc. All rights reserved. Part Number: T-CS-PE-0009-100 2000 Cadence Design Systems, Inc. All rights reserved. Part Number: T-CS-PE-0001-100 2003 Cadence Design Systems, Inc. All rights reserved. IntelliTM DDR Arbiter Interface, Part Number: DS-114-pkg16 2010 Virage Logic Corporation. All rights reserved. ARM Part number PL353 - DDI 0380G, Copyright 2005-2007 ARM Limited. All rights reserved.

GEM SDIO I2C SPI UART DMC SMC

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Chapter 5

Interconnect
5
5.1.1

Interconnect
Introduction
The Interconnect comprises multiple switches to connect system resources using AXI point-to-point channels for communicating addresses, data and response transactions between master and slave clients. This ARM AMBA 3.0 interconnect implements a full array of the interconnect communications capabilities and overlays for QoS, debug and test monitoring. The Interconnect manages multiple outstanding transactions and is architected for low-latency paths for the ARM CPUs and a high-throughput path for the PL Fabric master controllers.

5.1.2

Features
The PS Interconnect is the primary mechanism for data communications. PS Interconnect is based on AXI high performance datapath switches o o o o Snoop Control Unit that encompasses the CPU, ACP and HP interfaces OCM Interconnect Central and Slave/Master Interconnect Bridges/Switches AHB and APB Interconnect Bridges/Switches

PS-PL Interfaces o o o AXI_ACP, one cache coherent master port for PL Fabric AXI_HP, four high performance/bandwidth master ports for PL Fabric AXI_GP, four general purpose ports (two master ports and two slave ports)

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Chapter 5: Interconnect

5.1.3

XILINX CONFIDENTIAL DISCLOSED UNDER NDA Block Diagram


Figure 1 shows the block diagram for Interconnect.
CPU, L1 Clock cpu_6x4x SCU, L2, OCM Clock cpu_3x2x DDR Clock ddr_3x Each of the eight AXI interfaces are asynchronous to all else. 8

PL Fabric

Read/Write Requests (e.g., 8 reads, 8 writes) Clock Synchronizer

AHB/APB Clock cpu_1x

Interconnect, AXI_PS cpu_2x

ASYNC

DDR Clock ddr_2x

PL Fabric

High Performance AXI Controllers


(AXI_HP[3:0])
PL clocks M0 M1 M2

PL Fabric

Cortex A9
NEON/FPU Jazelle, Thumb-2, MMUs, L1 i/dCaches

PL Fabric

Cache Coherent ACP port


(S_AXI_ACP)
M
ASYNC

General Purpose AXI Controllers


(S_AXI_GP[1:0])
M0
ASYNC

Masters
Data
32-bit

DMA Controller
64-bit CPU_2x M

M1
ASYNC

CPU_1x DevC M
4 8 8

M3

CPU_6x4x 32- / 64-bit


ASYNC ASYNC ASYNC ASYNC

DAP M
1

FIFO

FIFO

FIFO

FIFO

Snoop Control Unit Cache Tag (SCU) CPU_6x4x


8 8 8 8

S0

S1

S2

S3 32-bit

RAM

Slave Interconnect
CPU_2x M
16

M0 S0 S1 S2 S3
4

M1

PL to Memory Interconnect
DDR_2x M0 M1

64-bit

64-bit
S

64-bit
S1 S0 S2

M2

L2 Cache
8 8

512 kB
CPU_6x4x M1
8

Central Interconnect
M0

64-bit M1

CPU_2x M2

M0
ASYNC ASYNC ASYNC

16

64-bit
S0 S0 S1

OCM Interconnect
64-bit M

S1
ASYNC

32-bit M0
8

Master Interconnect
M1
8

CPU_2x
ASYNC

CPU_2x

M2
4

M3
1

32-bit
ASYNC ASYNC

32-bit

S1

S0 S0 S1 S S

256 kB
128-bit CPU_2x

PL Fabric

On-chip RAM

General Purpose AXI Controllers


(M_AXI_GP[1:0])

Slaves
Reg & Data CPU_1x

APB Slaves
Registers CPU_1x

64-bit
S3 S2 S0

64-bit
S1 DDR_3x

64-bit

DDR DRAM

Figure 1 Interconnect Block Diagram

Interconnect Masters
The interconnect masters are shown at the top of the figure, Interconnect Block Diagram. The address map for each of these masters are defined in Chapter 4, System Addresses.

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Chapter 5: Interconnect

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The Interconnect masters include: CPUs and ACP High Performance PL Interfaces, AXI_HP{3:0} General Purpose PL Interfaces, AXI_GP{1:0} DMA Controller AHB bus masters (IO peripherals with local DMA units)

Snoop Control Unit (SCU)


The functionality of the snoop control unit is described in Chapter 3, Application Processing Unit.

Central Interconnect
The Interconnect comprises multiple switches to connect system resources using AXI point-to-point channels for communicating addresses, data and response transactions between master and slave clients. This ARM AMBA 3.0 interconnect implements a full array of the interconnect communications capabilities and overlays for QoS, debug and test monitoring. The Interconnect manages multiple outstanding transactions and is architected for low-latency paths for the ARM CPUs and a high-throughput path for the PL Fabric master controllers.

5.1.5

Clock Domains Block Diagram


The DDR clock domain includes two independent, asynchronous clocks: DDR_3x and DDR_2x as shown in Figure 2. The peripheral IO clocks run asynchronous to both the CPU and DDR clock domains and to each other. The frequency ratios for these clocks are software programmable as described in the Clocks chapter. All the clocks between the PS and the PL are asynchronous.

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Chapter 5: Interconnect

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Programmable Logic
Async

PS APU

3:1 or 2:1 Ratio

PS and PL IO Peripherals

High Performance AXI Controllers (AXI_HP)

CPUs
CPU_6x4x

Cache Coherent ACP port

DevC AXI_GP DAP

Async

Interconnect Switch

Masters
CPU_1x

DMA Controller
CPU_2x

Snoop Control Unit (SCU)


AXI_HP to DDR Interconnect DDR_2x CPU_6x4x CPU_3x2x CPU_2x

CPU_2x

CPU_3x2x

On-chip RAM

L2 Cache

Central Interconnect

CPU_2x

Interconnect Switch

CPU_2x

Async

Async

M_AXI_GP

Slaves
CPU_1x

APB Slaves
CPU_1x

Async

DDR DRAM

DDR_3x

Figure 2 Clock Domain Block Diagram

5.2

Arbitration
T he A XI interconnect uses a two-level arbitration scheme to resolve contention. T he first-level arbitration is based on the priority indicated by the QoS signals from the master. T he highest QoS value has the highest priority. T he second-level arbitration is based on a least recently granted (L R G ) scheme and is used when multiple requests are pending with the same QoS signal value. The AXI_HP interfaces can generate the QoS signals dynamically; that is, the QoS value can be changed between one transaction and the next. The QoS values for all the other AXI masters are statically controlled by a register setting. In each case, there are separate controls for read and write transactions. T he interconnect uses all four QoS signals except where the interconnect attaches to the D D R memory controller, w hich takes only the most significant Q oS signal to determine if a request is urgent. T he other QoS signals are not used. R efer to the D D R memory controller chapter for more details. The QoS mechanism is based on ARMs QoS-301 which is an extension to the NIC-301 network interconnect. For more information, refer to CoreLink QoS-301 Network Interconnect Advanced Quality of Service technical reference manual.

5.3

PS-PL AXI Interfaces

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5.3.1
Interface Name M_AXI_GP0

XILINX CONFIDENTIAL DISCLOSED UNDER NDA Features

Table 1: PS-PL AXI Interfaces Data Width Interface Description PS 32-bit M_AXI_GP1 S_AXI_GP0 S_AXI_GP1 S_AXI_ACP0 S_AXI_HP0 S_AXI_HP1 S_AXI_HP2 S_AXI_HP3 32- or 64-bit 32-bit 32- or 64-bit General Purpose (AXI_GP) Accelerator Coherent Port, cache-coherent transaction (ACP) High Performance ports (AXI_HP) with read/write FIFOs and two dedicated memory ports on DDR controller and a path to the OCM. General Purpose (AXI_GP) PS PL Fabric PL Fabric PL Fabric PL Fabric PL Fabric PL Fabric PL Fabric Master Slave PL Fabric PL Fabric PS PS PS PS PS PS PS Well over a thousand signals are used to implement these nine interfaces. Signals

5.3.2

Block Diagram
PS AXI Interconnect

M_AXI_GP{0, 1}

Programmable Logic (PL)


High Performance, AXI_HP AXI FIFO Interface, AFI
Master Controller Master Controller Master Controller Master Controller

Slave Controller

Slave Controller

Cache Coherent AXI_ACP port


Master Controller

General Purpose AXI_GP


Master Controller

S_AXI_HP{0, 1, 2, 3}

S_AXI_ACP

S_AXI_GP{0, 1}

DDR DRAM Memory Ports

SCU

PS AXI Interconnect

Figure 4 PL AXI Interfaces Block Diagram

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Master Controller

Chapter 5: Interconnect

5.3.3

XILINX CONFIDENTIAL DISCLOSED UNDER NDA PS-PL AXI Channel and Signals
General Purpose Interface High Performance Interface, Advanced Coherent Port x2, S_AXI_GP{0,1} x4, S_AXI_HP{0:3} with FIFOs x1, S_AXI_ACP

General Purpose Interface x2, M_AXI_GP{0,1}

PL Fabric
Slaves

Processing System
Masters M_AXI_GP{0,1}
_ACLK _ARESETN
Interface clk rst

PL Fabric
Masters
_ACLK _ARESETN

Processing System
Slaves
Interface clk rst

Read Address Ready Read Address Ready


Address Read Channel
Receive

Address Read Channel

Receive

Read Data Ready

Data Read Channel

Initiate

Slave Controllers Master Controller

Read Data Ready

Master Controller Controllers Controller Master Controller Master Master Controller Master Controller

Data Read Channel

Initiate

Write Address Ready

Address Write Channel

Receive

Write Address Ready

Address Write Channel

Receive

Write Data Ready

Write Data Ready


Data Write Channel

Data Write Channel

Receive

Receive

Write Response Ready


Initiate

Write Response Channel

Initiate

Write Response Ready

Write Response Channel

8 3 8 8

HP_WR_ISSUECAP1_EN HP_RD_ISSUECAP1_EN HP_RCOUNT [7:0] ACP_RACOUNT [2:0] HP_WCOUNT [7:0] HP_WACOUNT [5:0]

Figure 5 PL AXI Interface Channels

General Purpose AXI PS Masters AXI Channel M_AXI_GP{0,1} I/O

AXI PS Slaves S_AXI_GP{0,1} S_AXI_HP{0:3} S_AXI_ACP I/O

Clock/ Reset

GP_ACLK GP_ARESETN Read Address GP_ARADDR [31:0]

I O

{GP,HP,ACP}_ACLK {GP,HP,ACP}_ARESETN

I O

{GP,HP,ACP}_ARADDR [31:0]

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General Purpose AXI PS Masters AXI Channel M_AXI_GP{0,1} GP_ARVALID GP_ARREADY ~ GP_ARID [11:0] ~ GP_ARSIZE[2:0] GP_ARQOS [3:0] GP_ARLOCK [1:0] GP_ARCACHE [3:0] GP_ARPROT [2:0] GP_ARLEN [3:0] GP_ARBURST [1:0] Read Data GP_RDATA [31:0] ~ GP_RVALID GP_RREADY GP_RID [11:0] ~ GP_RLAST GP_RRESP [1:0] Write Address GP_AWADDR [31:0] GP_AWVALID GP_AWREADY ~ GP_AWID [11:0] ~ GP_AWQOS [3:0] GP_AWLOCK [1:0] GP_AWCACHE [3:0] GP_AWPROT [2:0] GP_AWLEN [3:0] GP_AWSIZE [1:0] GP_AWBURST [1:0] Write Data GP_WDATA [31:0] ~ O GP_WDATA [31:0] {HP,ACP}_WDATA [63:0] I I O O O O O O O O O O I {GP,HP,ACP}_AWADDR [31:0] {GP,HP,ACP}_AWVALID {GP,HP,ACP}_AWREADY ACP_AWUSER [4:0] {GP,HP}_AWID [11:0] ACP_AWID [2:0] {GP,HP,ACP}_AWQOS [3:0] {GP,HP,ACP}_AWLOCK [1:0] {GP,HP,ACP}_AWCACHE [3:0] {GP,HP,ACP}_AWPROT [2:0] {GP,HP,ACP}_AWLEN [3:0] {GP,HP,ACP}_AWSIZE [1:0] {GP,HP,ACP}_AWBURST [1:0] I I O I I I I I I I I I I I O I I I I I GP_RDATA [31:0] {HP,ACP}_RDATA [63:0] {GP,HP,ACP}_RVALID {GP,HP,ACP}_RREADY {GP,HP}_RID [11:0] ACP_RID [2:0] {GP,HP,ACP}_RLAST {GP,HP,ACP}_RRESP [2:0] O O O I O O O O O O O O O O O O I/O O I AXI PS Slaves S_AXI_GP{0,1} S_AXI_HP{0:3} S_AXI_ACP {GP,HP,ACP}_ARVALID {GP,HP,ACP}_ARREADY ACP_ARUSER [4:0] {GP,HP}_ARID [11:0] ACP_ARID [2:0] {GP,HP,ACP}_ARSIZE[2:0] {GP,HP,ACP}_ARQOS [3:0] {GP,HP,ACP}_ARLOCK [1:0] {GP,HP,ACP}_ARCACHE [3:0] {GP,HP,ACP}_ARPROT [2:0] {GP,HP,ACP}_ARLEN [3:0] {GP,HP,ACP}_ARBURST [1:0] I/O I O I I I I I I I I I I

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General Purpose AXI PS Masters AXI Channel M_AXI_GP{0,1} GP_WVALID GP_WREADY GP_WID [11:0] GP_WLAST GP_WSTRB [3:0] Write Response GP_BVALID GP_BREADY GP_BID [11:0] ~ GP_BRESP [1:0] I I O I {GP,HP,ACP}_BVALID {GP,HP,ACP}_BREADY {GP,HP}_BID [11:0] ACP_BID [2:0] {GP,HP,ACP}_BRESP [1:0] O I O O O I/O O I O O O AXI PS Slaves S_AXI_GP{0,1} S_AXI_HP{0:3} S_AXI_ACP {GP,HP,ACP}_WVALID {GP,HP,ACP}_WREADY {GP,HP,ACP}_WID [11:0] {GP,HP,ACP}_WLAST {GP,HP,ACP}_WSTRB [3:0] I/O I O I I I

5.3.4

PS-PL AXI Channel Signal Descriptions


The AXI Channel signal types are listed in Table 2. Channel signals flow from the Initiator (I) to Receptor (R). Address and data write channels are always initiated by the master. The slave imitates the data read and write response channel activity.

Table 2: AXI Channel Signal Types Signal VALID READY Channel Type all channels all channels AR AW AR AW AW AR AW AR AW AR AW AR AW AR R, W Name Channel clock enable Slave accepts transfer Byte Address Direction IR IR IR IR IR IR IR IR IR IR Description The valid signal is a clock enable. It is asserted when valid signals are being driven by the channel transmitter. The receiver asserts the ready signal when it has latched the signals from the transmitter. Address of the first transfer in a burst transaction. The associated control signals are used to determine the addresses of the remaining data transfers in the burst. 32-bit byte address. Exact number of data transfer cycles in a burst transfer. Byte lane strobes indicate which byte lanes to update. Burst Length of transactions. The burst type, coupled with the size information, details how the address for each transfer within the burst is calculated. Defines the atomic characteristics of the transfer. This signal indicates the bufferable, cacheable write-through, write-back and allocate attributes of the transaction. Indicates that the transaction is occurring with the interconnect operating in a secure mode. Final transfer in a burst.

ADDR

LEN SIZE BURST LOCK CACHE PROT LAST

Data Beats Burst Size, words Burst Type Lock Type Caching Indicators TrustZone Security Last data cycle

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Chapter 5: Interconnect

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RESP ID Urgent Signals R, W, B All channels Combined R/W Response Transaction ID IR Both IR Status of transfer, including error codes. Identification of transactions to allow interleaving of threads and different masters. AXI_HP

5.3.5

Clocks and Resets


Each interface has a single clock for all five channels that make up an interface. This clock is provided by the PL Fabric. Each interface has a common reset signal that is driven by the PS reset subsystem. As described in Section 5.1.4, clocks have to be active and resets inactive on all PS-PL AXI interfaces in order for the GPV to function properly. The entire PS may hang if the condition is not satisfied and a GPV access is attempted. Therefore, no GPV access should be attempted if not all the clocks for the PS-PL AXI interfaces are connected.

5.4

AXI_HP Interfaces
The four AXI_HP interfaces provides PL bus masters with high bandwidth datapaths to the DDR and OCM memories. Each interface includes two FIFO buffers for read and write traffic. The PL to Memory Interconnect routes the high-speed AXI_HP ports to two DDR memory ports or the OCM. The AXI_HP interfaces are also referenced as AFI (AXI FIFO Interface), to emphasize their buffering capabilities.

5.4.1

Features
The interfaces are designed to provide a high throughput data path between PL masters and PS memories including the DDR and on-chip RAM. Main features: 32- or 64-bit data wide master interfaces (independently programmed per port) Efficient resizing in 32-bit widths Efficient upsizing to 64-bits for aligned 32-bit transfers in 32-bit slave interface configuration mode. Automatic Expansion to 64-bits for unaligned 32-bit transfers in 32-bit slave interface configuration mode Dynamic command upsizing translation between 32-bit and 64-bit interfaces, controllable via AxCACHE[1] Programmable acceptance by Interconnect capability, separately for read and write commands Programmable release threshold of write commands Asynchronous clock frequency domain crossing for all AXI interfaces between PL Fabric and PS Smoothing out of long-latency transfers using 1 kB (128 by 64 bit) data FIFOs for both reads and writes QoS signaling available from PL Fabric ports Command and Data FIFO fill-level counts available to PL Fabric Standard AXI 3.0 interfaces supported Large slave interface read acceptance capability in the range of 14 to 70 commands (burst length dependent) Large slave interface write acceptance capability in the range of 8 to 32 commands (burst length dependent)

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