Title: Analysis and Optimization of Low-Power SRAM.

Abstract: Considerable attention has to be given to the design of low-power, high-performance SRAMs (Static Random Access Memories) since they are a critical component in both hand-held devices and high-performance processors. A key in improving the performance of the system is to use an optimum SRAM. This project explores the design and analysis of Static Random Access Memory (SRAM), focusing on optimizing power of SRAM cell. We will analyze many SRAM cell for example normal 6T SRAM cell, Proposed SRAM cell, SRAM cell with sleep transistors etc., The SRAM access path is split into two portions: from address input to word line rise (the row decoder) and from word line rise to data output (the read data path). Furthermore, we will also analyze various sense amplifiers, as we know clocked voltage sense amplifiers are essential for obtaining low sensing power, and accurate generation of their sense clock is required for high speed operation. References: [1] Vibhu Sharma et. al., “A 4.4 pJ/Access 80 MHz, 128 kbit Variability Resilient SRAM With Multi-Sized Sense Amplifier Redundancy”, IEEE journal of solid-state circuits, vol. 46, no. 10, 0018-9200/$26.00 October 2011. [2] Naveen Verma et. al., “A 256 kb 65 nm 8T Subthreshold SRAM Employing Sense-Amplifier Redundancy”, IEEE journal of solid-state circuits, vol. 43, no. 1, 0018-9200/$25.00 January 2008. [3] Hides Jamima, Yasuhiro Takahashi, and Toshikazu Sekine “Low-Power Adiabatic SRAM”, International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS) December 7-9, 2011. [4] S. Nakata, T. Kusumoto, M. Miyama, and Y.Matsuda, “Adiabatic SRAM with a large margin of VT variation by controlling the cell-power-line and word-line voltage”, in Proc. IEEE Int. Symp.Circuits and System (ISCAS 2009), Taipei, Taiwan, May 24-27, 2009, pp.393-396. [5] Kevin Zhang et. al., “SRAM Design on 65-nm CMOS Technology with Dynamic Sleep Transistor for Leakage Reduction”, IEEE journal of solid-state circuits, vol. 40, no. 4, 00189200/$20.00 April 2005.
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.9. February 2011. “Design and Sensitivity Analysis of a New Current-Mode Sense Amplifier for Low-Power SRAM”. al. “A Low Power SRAM Cell with High Read Stability”. vol.[6] Anh-Tuan Do et. Sivamangai & K. ii . Electronics & Communication vol. no. IEEE Transaction on Electronic Devices. January 2008. [8] N.M. no. vol. Gunavathi. [7] Kevin Zhang et. “Low-Power SRAMs in Nanoscale CMOS Technologies”. ECTI Transaction on Electrical engg. 1. 55. 2.1 February 2011. 19. al. IEEE Transavtion on Very Large Scale Integration (VLSI) Systems.. no.

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