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INTEGRATED CIRCUITS

DATA SHEET

TDA9850 I2C-bus controlled BTSC stereo/SAP decoder
Preliminary specification File under Integrated Circuits, IC02 1995 Jun 19

Philips Semiconductors

Preliminary specification

I2C-bus controlled BTSC stereo/SAP decoder
FEATURES • Quasi alignment-free application due to automatic adjustment of channel separation via I2C-bus • Dbx noise reduction circuit • Dbx decoded stereo, Second Audio Program (SAP) or mono selectable at the AF outputs • Additional SAP output without dbx, including de-emphasis • High integration level with automatically tuned integrated filters • Input level adjustment I2C-bus controlled • Alignment-free SAP processing • Stereo pilot PLL circuit with ceramic resonator, automatic adjustment procedure for stereo channel separation, two pilot thresholds selectable via I2C-bus • Automatic pilot cancellation • Composite input noise detector with I2C-bus selectable thresholds for stereo and SAP off • I2C-bus transceiver. QUICK REFERENCE DATA SYMBOL VCC ICC VoR(rms); VoL(rms) GLA αcs THDL,R S/N PARAMETER supply voltage supply current CONDITIONS MIN. 8.5 − 100% modulation L + R; fi = 300 Hz − TYP. 9 58 250 500 − 35 0.2 60 73 GENERAL DESCRIPTION

TDA9850

The TDA9850 is a bipolar-integrated BTSC stereo/SAP decoder (I2C-bus controlled) for application in TV sets, VCRs and multimedia.

MAX. 9.5 75 − − +4.0 − − − −

UNIT V mA mV mV dB dB % dB dBA

Vcomp(rms) input signal voltage (RMS value)

output signal voltage (RMS value) 100% modulation L + R; fi = 300 Hz − input level adjustment control stereo channel separation total harmonic distortion L + R signal-to-noise ratio fL = 300 Hz; fR = 3 kHz fi = 1 kHz 500 mV (RMS) mono output signal CCIR noise weighting filter (peak value) DIN noise weighting filter (RMS value) − − −3.5 25 −

ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TDA9850 TDA9850T SDIP32 SO32 DESCRIPTION plastic shrink dual in-line package; 32 leads (400 mil) plastic small outline package; 32 leads; body width 7.5 mm VERSION SOT232-1 SOT287-1

1995 Jun 19

2

Philips Semiconductors

Preliminary specification

I2C-bus controlled BTSC stereo/SAP decoder
License information A license is required for the use of this product. For further information, please contact: COMPANY THAT Corporation BRANCH Licensing Operations ADDRESS 734 Forest St. Marlborough, MA 01752 USA Tel.: (508) 229-2500 Fax: (508) 229-2590

TDA9850

Tokyo Office

405 Palm House, 1-20-2 Honmachi Shibuya-ku, Tokyo 151 Japan Tel.: (03) 3378-0915 Fax: (03) 3374-5191

1995 Jun 19

3

+ + + C2 + 1995 Jun 19 C3 C4 C5 Q1 ceramic resonator + BLOCK DIAGRAM Philips Semiconductors I2C-bus controlled BTSC stereo/SAP decoder C6 C7 19 27 stereo OUTL mono SAP to OUTR audio processing 21 22 4 7 LOGIC. ook. application and test diagram. full pagewidth R1 13 14 15 16 17 L+R 18 STEREO DECODER L − R/SAP DEMATRIX + MODE SELECT TDA9850 C8 composite baseband input 11 C1 INPUT LEVEL ADJUST NOISE DETECTOR STEREO/SAP SWITCH DE-EMPHASIS 23 SAP without DBX SAP DEMODULATOR DBX STEREO ADJUST SUPPLY 5 + 4 26 + 3 1 R2 2 + 32 + 31 + 30 + 29 + 25 + 20 10 + 12 6 + 24 C16 C15 C17 C19 C14 R3 C13 C18 SDA SCL C12 C11 C10 C9 CL CR only during adjustment VCC VCAP Vref Fig...1 Block.This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. I2CTRANSCEIVER 28 MAD 8 9 MHA010 Preliminary specification TDA9850 . white to force landscape pages to be .

2 µF 2. unless otherwise specified.2 µF 2.7 µF 100 nF 100 µF 100 µF 2. see Fig.5 µA 63 V 63 V 63 V TYPE electrolytic 63 V REMARK 1995 Jun 19 5 . resistors ±5%.7 µF 4. Ileak < 1. foil capacitors ±10%.Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder TDA9850 COMPONENT LIST Electrolytic capacitors ±20%.7 µF 15 nF 10 µF 10 µF 1 µF 1 µF 47 nF 10 µF 100 nF 4. COMPONENT C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 CR CL R1 R2 R3 Q1 10 µF 470 nF 4.7 µF 220 nF 10 µF 4.2 kΩ 160 Ω CSB503F58 CSB503JF958 ±2% ±2% radial leads alternative as SMD VALUE foil electrolytic foil electrolytic electrolytic electrolytic foil electrolytic electrolytic electrolytic electrolytic foil electrolytic foil electrolytic foil electrolytic electrolytic electrolytic electrolytic 16 V 16 V 63 V 63 V 63 V 63 V ±10% 63 V ±10% 63 V 63 V ±5% 63 V 63 V.2 kΩ 8.1.

left channel programmable address bit capacitor timing wideband for dbx capacitor timing spectral for dbx capacitor wideband for dbx capacitor spectral for dbx VEO VEI CNR CM CDEC AGND DGND SDA SCL 1 2 3 4 5 6 7 8 32 CS 31 CW 30 CTS 29 CTW 28 MAD 27 OUTL 26 CND 25 CL TDA9850 9 VCC 10 COMP 11 VCAP 12 CP1 13 CP2 14 CPH 15 CADJ 16 MHA012 24 Vref 23 SAP 22 CSDE 21 OUTR 20 CR 19 CSS 18 CMO 17 CER Fig.Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder PINNING SYMBOL VEO VEI CNR CM CDEC AGND DGND SDA SCL VCC COMP VCAP CP1 CP2 CPH CADJ CER CMO CSS CR OUTR CSDE SAP Vref CL CND OUTL MAD CTW CTS CW CS PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 DESCRIPTION variable emphasis output for dbx variable emphasis input for dbx capacitor noise reduction for dbx capacitor mute for SAP capacitor DC-decoupling for SAP fpage TDA9850 analog ground digital ground serial data input/output serial clock input supply voltage (+9 V) composite input signal capacitor for electronic filtering of supply capacitor for pilot detector capacitor for pilot detector capacitor for phase detector capacitor for filter adjustment ceramic resonator capacitor DC-decoupling mono capacitor DC-decoupling stereo/SAP adjustment capacitor.5 V) adjustment capacitor.2 Pin configuration. right channel output.5 × (VCC − 1. left channel noise detector capacitor output. 1995 Jun 19 6 . right channel capacitor SAP de-emphasis SAP output reference voltage 0.

the SAP signal is also available at pin SAP. This makes it necessary to switch stereo or SAP off at certain thresholds. The required filter accuracy is attained by an automatic filter alignment circuit. With ST0 to ST3 (see Table 6) the stereo threshold can be selected and with SP0 to SP3 the SAP threshold. Stereo decoder The output signal of the level adjustment stage is coupled to a low-pass filter which suppresses the baseband noise above 125 kHz. These thresholds can be set via the I2C-bus. The stereo channel separation is adjusted by an automatic procedure to be performed during set production. Mode selection The stereo/SAP switch feeds either the L − R signal or the SAP demodulator output signal via the internal dbx noise reduction circuit to the dematrix/switching circuit. The output signal is fed through a 73 µs fixed de-emphasis circuit to the dematrix block. The maximum input signal voltage is 2 V (RMS). The SAP identification signal can be read by the I2C-bus (see Table 2). Two different pilot thresholds (data STS = 1. The capacitor at SDE provides a recommended de-emphasis (150 µs) at SAP. SAP demodulator The composite signal is fed from the output of the input level adjustment stage to the SAP demodulator circuit through a 5fH band-pass filter. The control range is from −3. Table 8 shows the different switch modes provided at the output pins OUTR and OUTL. For a detailed description see Section “Adjustment procedure”.5 dB. The demodulator level is automatically controlled. Noise detector TDA9850 The composite input noise increases with decreasing antenna signal.Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder FUNCTIONAL DESCRIPTION Input level adjustment The composite input signal is fed to the input level adjustment stage.0 dB in steps of 0. The composite signal is then fed into a pilot detector/pilot cancellation circuit and into the MPX demodulator. The decoded sub-signal L − R is sent to the stereo/SAP switch. The stereo identification can be read by the I2C-bus (see Table 2).5 to +4. The main L + R signal passes a 75 µs fixed de-emphasis filter and is fed into the dematrix circuit. SAP output Independent of the stereo/SAP switch. the SAP signal is not dbx decoded. The subaddress control 4 of Tables 5 and 6 and the level adjust setting of Table 10 allows an optimum signal adjustment during the set alignment. Integrated filters The filter functions necessary for stereo and SAP demodulation and part of the dbx filter circuits are provided on-chip using transconductor circuits. At SAP. 1995 Jun 19 7 . dbx decoder The dbx circuit includes all blocks required for the noise reduction system in accordance with the BTSC system specification. STS = 0) can be selected via the I2C-bus (see Table 14). A hysteresis can be achieved via software by making the threshold dependent of the identification bits STP and SAPP (see Table 2). The SAP demodulator includes an internal field strength detector that mutes the SAP output in the event of insufficient signal conditions. To generate the pilot signal the stereo demodulator uses a PLL circuit including a ceramic resonator.

After every power-on. SAP = 0 (see Table 8). the timing current can be adjusted via I2C-bus. MANUAL ADJUSTMENT TDA9850 Manual adjustment is necessary when no dual tone generator is available (e. • Mode selection setting bits: STEREO = 1. AUTOMATIC ADJUSTMENT PROCEDURE • Connect 2. The alignment procedure overwrites the previous data stored in ALI1 and ALI2. the alignment data and the input level adjustment data must be loaded from the non-volatile memory. 14% modulation for each channel. as recommended by dbx. 14% modulation • Adjust channel separation by varying spectral data • Iterative spectral/wideband operation for optimum adjustment • Store data in non-volatile memory. • The capacitors from ACR and ACL may be disconnected after alignment. • Spectral and wideband data have to be set to 10000 (middle position for adjustment range) • Composite input L = 300 Hz. 1995 Jun 19 8 .Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder Adjustment procedure COMPOSITE INPUT LEVEL ADJUSTMENT Feed in from FM demodulator the composite signal with 100% modulation (25 kHz deviation) L + R. The decoder will align itself. • After 1 second minimum stop alignment by transmitting ADJ = 0 in register ALI3 read the alignment data by an I2C-bus read operation from ALR1 and ALR2 (see Chapter “I2C-bus protocol”) and store it in a non-volatile memory. TIMING CURRENT FOR RELEASE RATE Due to possible internal and external spreading. Set input level control via I2C-bus monitoring OUTL or OUTR (500 mV ±20 mV).2 µF capacitors from ACR and ACL to ground. R = 3.g.1 kHz. for service). fi = 300 Hz. • Composite input signal L = 300 Hz. • Start adjustment by transmission ADJ = 1 in register ALI3. see Table 9. 14% modulation • Adjust channel separation by varying wideband data • Composite input L = 3 kHz. Store the setting in a non-volatile memory.

Human Body Model (HBM): C = 100 pF. note 1 VCC ≥ 8. SYMBOL VCC VVCAP VVEO VSDA VSCL Vn Tamb Tstg Ves Note PARAMETER supply voltage voltage of VCAP to GND voltage of VEO to GND voltage of SDA to GND voltage of SCL to GND voltage of all other pins to GND operating ambient temperature storage temperature electrostatic handling HBM.Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134).5 8.5 VCC +70 +150 1. charge device model: C = 200 pF. R = 1.5 V VCC < 8. V = 300 V.5 V Tj < 125 °C CONDITIONS 0 0 0 0 0 0 0 −20 −65 MIN.5 8. TDA9850 MAX. V = 2 kV. THERMAL CHARACTERISTICS SYMBOL Rth j-a SOT232-1 SOT287-1 PARAMETER thermal resistance from junction to ambient in free air 55 68 K/W K/W VALUE UNIT 1995 Jun 19 9 . 10 VCC 1⁄ 2VCC UNIT V V V V V V V °C °C 8.5 kΩ. R = 0 Ω.

5. 25 kHz deviation fi = 1 kHz. 3. For example colour bar or flat field white. 2. note 2 −0.5 − +0. fi = 300 Hz ∆COMP composite input level spreading under operating conditions source impedance low frequency roll-off high frequency roll-off total harmonic distortion L + R Tamb = −20 to +70 °C. 4. L + R. note 3 with sync only CCIR 468-2 weighted quasi peak. SAP carrier/side band spectral spurious attenuation L + R/spurious n = 1. fi = 1 kHz. 125 kHz deviation. otherwise the signal loss and spreading at COMP. mainly n × fH. aging. −2 dB 25 kHz deviation L + R. 6 n = 2. 25 kHz deviation. In order to prevent clipping at over-modulation (maximum deviation in the BTSC system for 100% modulation is 73 kHz). power supply influence note 1 25 kHz deviation L + R.5 kΩ Hz kHz % % S/N signal-to-noise ratio L + R/noise critical picture modulation. row head “Input level adjustment control”) must be taken into account. side band: SAP carrier frequency ±1 kHz 50 Hz to 100 kHz. RMS value. L + R.R − − 100 − − low-ohmic 5 − − − − 5 − 0.Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder TDA9850 REQUIREMENTS FOR THE COMPOSITE INPUT SIGNAL TO ENSURE CORRECT SYSTEM PERFORMANCE SYMBOL PARAMETER CONDITIONS measured at COMP MIN. 75 µs de-emphasis 44 54 − − − − − − dB dB dB αSB side band suppression mono into unmodulated SAP carrier. 40 fi = 1 kHz. Low-ohmic preferred. 363 UNIT mV COMPL+R(rms) composite input level for 100% modulation L + R (25 kHz deviation). 250 MAX. 35 f = 1 kHz as reference 26 αSP − − − − dB dB Notes 1. 1995 Jun 19 10 . 162 TYP. caused by ZO and the composite input impedance (see Chapter “Characteristics”.5 1. 3 mono signal: 25 kHz deviation. 100% video modulation.5 dB Zsource flf fhf THDL. no de-emphasis. 25 kHz deviation. −2 dB fi = 1 kHz.

MAX. see Fig.5 − 2 29. SYMBOL Supply VCC Vripple(p-p) supply voltage allowed supply voltage ripple (peak-to-peak value) supply current internal reference voltage at pin Vref crosstalk between bus inputs and signal outputs notes 1 and 2 fi = 50 Hz to 100 kHz 8. L.1.5 100 V mV PARAMETER CONDITIONS MIN. OUTR fi = 300 Hz).7 110 75 − − mA V dB Input level adjustment control GLA Gstep Vi(rms) Zi MPXL+R input level adjustment control step resolution maximum input voltage level (RMS value) input impedance −3. VCC = 9 V. OUTL.5 − 9 − 9. 50 kHz deviation (peak value) maximum headroom for L + R. Tamb = +25 °C. fi = 1 kHz. UNIT ICC Vref αct − − − 58 3. THD < 15% input level adjusted via I2C-bus (L + R.Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder TDA9850 CHARACTERISTICS All voltages are measured relative to GND. fi = 300 Hz). TYP.0 − − 40. monitoring OUTL or OUTR 250 mV MPXL−R − 707 − mV MPX(max) MPXpilot STon(rms) SToff(rms) Hys OUTL+R 9 − − − 15 10 − 480 − 50 − − − − 2.5 − dB dB V kΩ Stereo decoder input voltage level for 100% modulation L + R. R nominal stereo pilot voltage level (RMS value) pilot threshold voltage stereo on (RMS value) pilot threshold voltage stereo off (RMS value) hysteresis output voltage level for input level adjusted via 100% modulation L + R at I2C-bus (L + R. CL = 2.5 500 − − 35 30 − − − 520 dB mV mV mV mV mV dB mV 1995 Jun 19 11 .5 nF.5 − − 0. RL = 10 kΩ.5 − 35 +4. monitoring OUTL or OUTR data STS = 1 data STS = 0 data STS = 1 data STS = 0 fmod < 15 kHz. 25 kHz deviation (RMS value) input voltage level for 100% modulation L − R. unless otherwise specified. AC-coupled. Rs = 600 Ω.

0 % 1995 Jun 19 12 .2 60 − − 1.R S/N total harmonic distortion L.Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder TDA9850 SYMBOL αcs PARAMETER CONDITIONS MIN. 50 Hz to 8 kHz. oscillator (VCXO). fR = 10 kHz 15 35 30 25 − − − dB dB dB fL. fR = 8 kHz 20 fL = 300 Hz.5 2.0 − kHz kHz Hz SAP demodulator. fi = 1 kHz mono mode. MAX. note 4 SAPi(rms) nominal SAP carrier input voltage level (RMS value) threshold voltage SAP on (RMS value) threshold voltage SAP off (RMS value) hysteresis SAP output voltage level at OUTL.0 ±190 503. see Section “Adjustment procedure” fL = 300 Hz. note 3 fo fof ∆fH nominal VCXO output frequency (32fH) spread of free-running frequency capture range frequency (nominal pilot) with nominal ceramic resonator with nominal ceramic resonator − 500. fmod = 300 Hz. UNIT stereo channel separation aligned with dual tone L/R 14% modulation for each channel. fref = 300 Hz fi = 1 kHz 15 kHz frequency deviation of intercarrier − 150 − mV SAPon(rms) SAPoff(rms) SAPhys SAPLEV − 28 − − − − 2 500 68 − − − mV mV dB mV fres frequency response −3 − − dB THD total harmonic distortion − 0. fref = 300 Hz L or R fi = 50 Hz to 10 kHz fi = 12 kHz −3 − − 50 − −3 0. quasi peak. CCIR 468-2 weighted. TYP. R signal-to-noise ratio modulation L or R 1% to 100%. 500 mV output signal Stereo decoder. OUTR mode selector in position SAP/SAP. 100% modulation 14% modulation.0 − dB dB % dB THDL.5 − ±265 − 507. fR = 3 kHz 25 fL = 300 Hz. R frequency response 14% modulation. R L.

3 0.5 − Outputs OUTL and OUTR Vo(rms) HEADo Zo VO RL CL αct nominal output voltage (RMS value) output headroom output impedance DC output voltage output load resistance (AC-coupled) output load capacitance crosstalk L.Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder TDA9850 SYMBOL SAP output Zo VO RL CL Vo(rms) PARAMETER CONDITIONS − − 5 − 150 µs de-emphasis MIN. mode selector switched to SAP/SAP 100% modulation. L or R.5 V crosstalk SAP into L. R 50 70 − dB ∆VST-SAP output voltage difference if switched from L. fi = 1 kHz. mode selector switched to stereo 250 Hz to 6. UNIT Ω V kΩ nF output impedance DC output voltage output load resistance (AC-coupled) output load capacitance nominal output voltage (RMS value) 80 − − 120 − 2.55VCC−1. TYP.5 0.5VCC−1.5 see Fig.5VCC−1.5 − mV dB Ω kΩ nF dB 0. R to SAP − − 3 dB Dbx noise reduction circuit tadj Is stereo adjustment time nominal timing current for nominal release rate of spectral RMS detector spread of timing current timing current range timing current for release rate of wideband RMS detector nominal RMS detector release rate wideband spectral 1995 Jun 19 13 nominal timing current and external capacitor values 7 steps via I2C-bus see Section “Adjustment procedure” − − 24 1 − s µA Is can be measured at pin − CTS via current meter connected to 1⁄ V 2 CC + 0.25 V −15 − − ∆Is Is range It − ±30 1⁄ 3Is +15 − − % % µA Relrate − − 125 381 − − dB/s dB/s . MAX.3 kHz 100% modulation − 9 − 5 − 50 500 − 80 − − 75 − − 120 − 2.45VCC−1. R into SAP 100% modulation.5 0. SAP. fi = 1 kHz.

SAP16 ∆Ster. The transmission contains: a) Total initialization with MAD and SAD for volume and 11 DATA words. OUTR mute) is set and the I2C-bus receiver is in the reset position. see also definition of characteristics b) Clock frequency = 50 kHz c) Repetition burst rate = 400 Hz d) Maximum bus signal amplitude = 5 V (p-p). note 5 VRESET(STA) start of reset voltage increasing supply voltage − decreasing supply voltage VRESET(END) end of reset voltage Digital part (I2C-bus pins). When reset is active the SMU-bit (SAP mute) and the LMU-bit (OUTL. 5.5 +10 +10 0. Crosstalk: 20 log -------------------V o(rms) 2. 4.8 6.Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder TDA9850 SYMBOL Noise detector f0 Q Ster1. UNIT noise band-pass centre frequency quality factor lowest noise threshold for stereo off respectively SAP off (RMS value. The internal SAP carrier level is determined by the composite input level and the level adjustment gain.3 −10 −10 − − − − − − 8. − − 34 MAX. ∆SAP fi = 185 kHz 210 290 400 mV noise threshold step width fi = 185 kHz 0 1. note 6 VIH VIL IIH IIL VOL HIGH level input voltage LOW level input voltage HIGH level input current LOW level input current LOW level output voltage IIL = 3 mA 3 −0. TYP. 3. see Tables 11 and 12) highest noise threshold for stereo off respectively SAP off (RMS value) composite input level 100 mV (RMS) 185 6 24 kHz − mV Ster16.2 − 5 6 2. SAP1 PARAMETER CONDITIONS − − fi = 185 kHz 17 MIN.5 5. 6.8 V V V increasing supply voltage 5.5 +1. The AC characteristics are in accordance with the I2C-bus specification for standard mode (clock frequency maximum 100 kHz). Information about the I2C-bus can be found in brochure “I2C-bus and how to use it” (order number 9398 393 40011). 1995 Jun 19 14 . can be used if all clock and data times are interpolated between standard mode (100 kHz) and fast mode (400 kHz) in accordance with the I2C-bus specification. up to 280 kHz. A higher frequency. The oscillator is designed to operate together with MURATA resonator CSB503F58 or CSB503JF958 as SMD.2 Notes to the characteristics V bus(p-p) 1.4 V V µA µA V 4.5 3 dB Power-on reset. but the resonator specification must be close to the specified ones. Change of the resonator supplier is possible.

The master next generates an acknowledge. generated by the master Definition of the transmitted bytes after read condition MSB FUNCTION BYTE D7 D6 SAPP SAPP D5 STP STP D4 A14 A24 D3 A13 A23 D2 A12 A22 D1 A11 A21 D0 A10 A20 ALR1 ALR2 Y Y LSB S Standard SLAVE ADDRESS (MAD) Pin programmable SLAVE ADDRESS R/W A DATA MA P Table 2 Alignment read 1 Alignment read 2 Table 3 Function of the bits in Table 2 BITS FUNCTION stereo pilot identification (stereo received = 1) SAP pilot identification (SAP received = 1) stereo alignment read data for wideband expander for spectral expander indefinite STP SAPP A1X to A2X A1X A2X Y The master generates an acknowledge when it has received the first data word. generated by the master STOP condition. generated by the slave slave transmits an 8-bit data word acknowledge.Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder I2C-BUS PROTOCOL I2C-bus format to read (slave transmits data) S Table 1 SLAVE ADDRESS R/W A DATA MA TDA9850 DATA P Explanation of I2C-bus format to read (slave transmits data) NAME DESCRIPTION START condition. generated by the master 1011011 pin MAD not connected 1011010 pin MAD connected to ground 1 (read). and so on until the master generates no acknowledge and transmits a STOP condition. then the slave transmits the next data word ALR2. ALR1. then slave begins transmitting the first data word ALR1. generated by the master acknowledge. 1995 Jun 19 15 .

generated by the slave see Table 5 see Table 6 STOP condition S Standard SLAVE ADDRESS (MAD) Pin programmable SLAVE ADDRESS R/W A SUBADDRESS (SAD) DATA P If more than 1 byte of DATA is transmitted. Table 5 Subaddress second byte after MAD MSB FUNCTION Control 1 Control 2 Control 3 Control 4 Alignment 1 Alignment 2 Alignment 3 Table 6 REGISTER D7 CON1 CON2 CON3 CON4 ALI1 ALI2 ALI3 0 0 0 0 0 0 0 D6 0 0 0 0 0 0 0 D5 0 0 0 0 0 0 0 D4 0 0 0 0 0 0 0 D3 0 0 0 0 1 1 1 D2 1 1 1 1 0 0 0 D1 0 0 1 1 0 0 1 D0 0 1 0 1 0 1 0 LSB Definition of third byte. third byte after MAD and SAD MSB LSB D6 0 0 STEREO 0 0 0 0 D5 0 0 0 0 0 0 0 D4 0 0 SMU 0 A14 A24 0 D3 ST3 SP3 LMU L3 A13 A23 0 D2 ST2 SP2 0 L2 A12 A22 TC2 D1 ST1 SP1 0 L1 A11 A21 TC1 D0 ST0 SP0 0 L0 A10 A20 TC0 REGISTER D7 CON1 CON2 CON3 CON4 ALI1 ALI2 ALI3 0 0 SAP 0 0 STS ADJ FUNCTION Control 1 Control 2 Control 3 Control 4 Alignment 1 Alignment 2 Alignment 3 1995 Jun 19 16 . starting from the transmitted subaddress and auto-increment of subaddress in accordance with the order of Table 5 is performed.Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder I2C-bus format to write (slave receives data) S Table 4 SLAVE ADDRESS R/W A SUBADDRESS A DATA TDA9850 A P Explanation of I2C-bus format to write (slave receives data) NAME DESCRIPTION START condition 101 101 1 pin MAD not connected 101 101 0 pin MAD connected to ground 0 (write) acknowledge. then auto-increment is performed.

SAPP SAP received no SAP received STEREO received no STEREO received SAP received no SAP received independent noise threshold for stereo noise threshold for SAP mode selection mute control OUTL and OUTR mute control SAP input level adjustment stereo adjustment on/off stereo alignment data for wideband expander for spectral expander timing current alignment data stereo level switch FUNCTION TDA9850 FUNCTION MODE AT OUTL SAP Mute Left Mono Mono Mono Mono Table 9 OUTR SAP mute right mono SAP mute mono SETTING BITS STEREO 1 1 1 1 0 0 0 SAP 1 1 0 0 1 1 0 Timing current setting FUNCTION IS RANGE DATA TC2 1 1 1 0 0 0 0 TC1 0 0 1 1 1 0 0 TC0 0 1 1 1 0 1 0 +30% +20% +10% Nominal −10% −20% −30% 1995 Jun 19 17 .Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder Table 7 Function of the bits in Table 6 BITS ST0 to ST3 SP0 to SP3 STEREO. READABLE BITS: STP. SAP LMU SMU L0 to L3 ADJ A1X to A2X A1X A2X TC0 to TC2 STS Table 8 Mode selection DATA TRANSMISSION STATUS INTERNAL SWITCH.

0 +1.5 DATA THRESHOLD L3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 L2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 L1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 L0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 SAP1 SAP2 SAP3 SAP4 SAP5 SAP6 SAP7 SAP8 SAP9 SAP10 SAP11 SAP12 SAP13 SAP14 SAP15 SAP16 SP3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 SP2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Table 12 SAP noise threshold (SAP) DATA TDA9850 SP1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SP0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Table 11 Stereo noise threshold (Ster) DATA THRESHOLD ST3 Ster1 Ster2 Ster3 Ster4 Ster5 Ster6 Ster7 Ster8 Ster9 Ster10 Ster11 Ster12 Ster13 Ster14 Ster15 Ster16 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 ST2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ST1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 ST0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Table 13 ADJ bit setting FUNCTION Stereo decoder operation mode Auto adjustment of channel separation DATA 0 1 Table 14 STS bit setting (pilot threshold stereo on) FUNCTION STon ≤ 35 mV STon ≤ 30 mV Table 15 Mute setting FUNCTION Forced mute at OUTR.0 +2.0 −3.0 −1.5 +3.0 −2.Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder Table 10 Level adjust setting GL (dB) +4.5 +2.5 −1.5 −2. OUTL DATA LMU 1 0 FUNCTION forced mute at SAP no forced mute at SAP DATA SMU 1 0 DATA 1 0 1995 Jun 19 18 .0 +0.5 0. OUTL No forced mute at OUTR.5 +1.0 +3.0 −0.5 −3.

Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder TDA9850 Table 16 Alignment data for expander in read register ALR1 and ALR2 and in write register ALI1 and ALI2 DATA FUNCTION Gain increase D4 AX4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Nominal gain Gain decrease 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D3 AX3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 D2 AX2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 D1 AX1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 D0 AX0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1995 Jun 19 19 .

3 Voltage at SAP output. (3) 1% modulation.Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder TDA9850 10 3 handbook. Fig. 1995 Jun 19 20 . full pagewidth VSAP (mV RMS) MHA011 (1) (2) 10 2 (3) 10 1 10 −1 1 fi (kHz) 10 150 µs de-emphasis. (2) 14% modulation. (1) 100% modulation.

. Fig. SDA. 5 Vb 8 1.Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder INTERNAL PIN CONFIGURATIONS TDA9850 2 1 Vb Vb MHA013 600 Ω MHA014 Fig. 1995 Jun 19 21 Fig.9 Pin 8. 3 Vb Vb 4 10 kΩ 10 kΩ MHA015 MHA016 Fig. VEI. VEO. CNR. CM.5 Pin 2.8 kΩ 20 kΩ 20 kΩ MHA017 MHA018 Fig.7 Pin 4.6 Pin 3. Fig. CDEC.8 Pin 5.4 Pin 1.

15 Pin 15. SCL.5 kΩ 12 kΩ 10 kΩ 10 kΩ MHA024 MHA023 Fig. VCC and pin 12.8 kΩ 200 Ω 10 MHA019 Vb MHA020 Fig. CP2.5 kΩ MHA022 MHA021 Fig.14 Pin 14. CPH. .Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder TDA9850 12 9 4.11 Pin 10.12 Pin 11. Fig. VCAP. COMP. CP1.10 Pin 9.13 Pin 13. 1995 Jun 19 22 Fig.7 kΩ 300 Ω 1. Vb 14 15 Vb 8. 11 Vb 13 Vb 30 kΩ 3. Fig.

CMO and pin 19. Fig. Vb 21 22 Vb 5 kΩ 10 kΩ MHA030 MHA029 Fig.18 Pin 18. CADJ. CER. CR and pin 25. CL. CSS. Fig. OUTR and pin 27 OUTL. 23 1995 Jun 19 .21 Pin 22.19 Pin 20. Fig. 20 18 Vb 20 kΩ 10 kΩ Vb 10 kΩ MHA027 20 kΩ MHA028 Fig.17 Pin 17.Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder TDA9850 16 Vb Vb 17 MHA025 3 kΩ MHA026 Fig.20 Pin 21. CSDE.16 Pin 16.

25 Pin 28.26 Pin 29. Fig.8 kΩ MHA033 MHA034 Fig. 29 Vb Vb 31 4. SAP.6 kΩ MHA035 MHA036 Fig. MAD.23 Pin 24. CW and pin 32. CTW and pin 30.27 Pin 31.22 Pin 23. . Vref.4 kΩ 3.Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder TDA9850 Vb 24 23 Vb 3.24 Pin 26. 26 Vb Vb 28 30 kΩ 1. 1995 Jun 19 24 Fig. Fig.4 kΩ MHA031 MHA032 Fig. CND. CS. CTS.

778 e1 10.2 10.51 A2 max.7 e 1. 0. OUTLINE VERSION SOT232-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 92-11-17 95-02-04 1995 Jun 19 25 .3 0.25 mm maximum per side are not included.5 w 0.5 E (1) 9. 4.32 0.18 Z (1) max.1 8.8 b 1.2 MH 12.16 L 3.8 b1 0. 1.53 0.23 D (1) 29.6 Note 1. 3.Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder PACKAGE OUTLINES SDIP32: plastic shrink dual in-line package.2 2.4 28. 32 leads (400 mil) TDA9850 SOT232-1 D seating plane ME A2 A L A1 c Z e b 32 17 b1 w M (e 1) MH pin 1 index E 1 16 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max.40 c 0.7 A1 min.7 10. Plastic or metal protrusions of 0.8 ME 10.

4 0.01 y 0.004 0.01 c 0. Plastic or metal protrusions of 0.3 0.29 e 1.007 D (1) 20. 32 leads.02 0.7 20.022 θ 0.00 0.6 7.27 0.30 0.01 w 0.4 0. body width 7.050 HE 10.096 0.0 0.5 mm SOT287-1 D E A X c y HE v M A Z 32 17 Q A2 A1 pin 1 index θ Lp 1 e bp 16 w M L detail X (A 3) A 0 5 scale 10 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max.2 1.1 A2 2.016 Q 1.15 mm maximum per side are not included.55 0.012 0.1 0.25 A3 0.043 0.004 Z (1) 0.36 0.25 0.95 0.086 8o 0o Note 1.10 A1 0.3 0.49 0.25 0.65 0. OUTLINE VERSION SOT287-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 95-01-25 97-05-22 1995 Jun 19 26 .45 2.011 0.047 0.18 0.4 0.65 10. 2.394 L 1.039 v 0.81 0.80 E (1) 7.01 bp 0.037 0.055 Lp 1.Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder TDA9850 SO32: plastic small outline package.419 0.27 0.25 0.1 0.

all other leads can be soldered in one operation within 2 to 5 seconds at between 270 and 320 °C. or for printed-circuits with high population densities. below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. The package can be soldered after the adhesive is cured. • The package footprint must incorporate solder thieves at the downstream end. Dwell times vary between 50 and 300 seconds depending on heating method. pin transfer or syringe dispensing. If the printed-circuit board has been pre-heated. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). Several techniques exist for reflowing. This text gives a very brief insight to a complex technology. Preheating duration: 45 minutes at 45 °C. Repairing soldered joints Fix the component by first soldering two diagonally-opposite end leads. However. The adhesive can be applied by screen printing. DBS and SIL Introduction There is no soldering method that is ideal for all IC packages. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. If the bit temperature is between 300 and 400 °C. and maximum duration of package immersion in solder is 10 seconds. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). flux and binding agent) to be applied to the printed-circuit board by screen printing. SDIP. but the temperature of the plastic body must not exceed the specified storage maximum. • The longitudinal axis of the package footprint must be parallel to the solder flow. Soldering by dip or wave The maximum permissible temperature of the solder is 260 °C. for example. However. Preheating is necessary to dry the paste and evaporate the binding agent. or for printed-circuits with high population densities. Typical dwell time is 4 seconds at 250 °C. Contact time must be limited to 10 seconds at up to 300 °C. stencilling or pressure-syringe dispensing before package placement. if cooled to less than 150 °C within 6 seconds. Repairing soldered joints Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package. The device may be mounted to the seating plane. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. Wave soldering Wave soldering techniques can be used for all SO packages if the following conditions are observed: • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. In these cases reflow soldering is often used. 1995 Jun 19 27 . wave soldering is not always suitable for surface mounted ICs. SOLDERING SO Introduction There is no soldering method that is ideal for all IC packages. When using a dedicated tool. solder at this temperature must not be in contact with the joint for more than 5 seconds. Typical reflow temperatures range from 215 to 250 °C. Reflow soldering requires solder paste (a suspension of fine solder particles. Reflow soldering TDA9850 Reflow soldering techniques are suitable for all SO packages. wave soldering is not always suitable for surface mounted ICs. In these cases reflow soldering is often used. During placement and before soldering. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. thermal conduction by heated belt. HDIP. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. The total contact time of successive solder waves must not exceed 5 seconds. the package must be fixed with a droplet of adhesive. This text gives a very brief insight to a complex technology. contact may be up to 5 seconds.Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder SOLDERING DIP. forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Maximum permissible solder temperature is 260 °C.

or systems where malfunction of these products can reasonably be expected to result in personal injury. This data sheet contains final product specifications. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. it is advisory and does not form part of the specification.Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values TDA9850 This data sheet contains target or goal specifications for product development. Exposure to limiting values for extended periods may affect device reliability. This specification can be ordered using the code 9398 393 40011. Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. 1995 Jun 19 28 . Application information Where application information is given. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances. This data sheet contains preliminary data. supplementary data may be published later. devices. Stress above one or more of the limiting values may cause permanent damage to the device.

Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder NOTES TDA9850 1995 Jun 19 29 .

Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder NOTES TDA9850 1995 Jun 19 30 .

Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder NOTES TDA9850 1995 Jun 19 31 .

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