Faults test generation algorithm based on threshold for digital circuit Liang Yingchun ; Yang Liyuan Mechatronic Science

, Electric Engineering and Computer (MEC), 2011 International Conference on Digital Object Identifier: 10.1109/MEC.2011.6025627 Publication Year: 2011 , Page(s): 974 - 977 IEEE CONFERENCE PUBLICATIONS Save to Project icon | Click to Reveal Quick AbstractQuick Abstract | PDF fil e iconPDF (260 KB) An effective test generation algorithm based on threshold for digital circuits i s proposed in this paper. Firstly, threshold test generation model for digital circuit is constructed, ac ceptable faults can be distinguished from unacceptable faults by using the model . Then threshold test patterns can be generated for unacceptable faults by using mature stuck-at faults test generation algorithm. The experimental results on ISCAS'85 and ISCAS'89 circuits demonstrate the algor ithm had high faults coverage and short test generation time. A Fast Threshold Test Generation Algorithm Based on 5-Valued Logic Inoue, T. ; Izumi, N. ; Yoshikawa, Y. ; Ichihara, H. Electronic Design, Test and Application, 2010. DELTA '10. Fifth IEEE Internation al Symposium on Digital Object Identifier: 10.1109/DELTA.2010.52 Publication Year: 2010 , Page(s): 345 - 349 Cited by: Papers (1) IEEE CONFERENCE PUBLICATIONS Threshold testing, which is a VLSI testing method based on the acceptability of faults, is effective in yield enhancement of VLSIs and in selectively hardening VLSI systems. A test generation algorithm for generating test patterns for unacceptable faults has been proposed, which is based on the 16-valued logic system. In this paper, we propose a fast test generation algorithm based on the 5-valued logic system. Experimental results show that our proposed algorithm can generate test patterns for unacceptable faults with small computational time, compared with that based on the 16-valued logic system. A Multiple Faults Test Generation Algorithm Based on Neural Networks and Chaotic Searching for Digital Circuits Zhao Ying ; Li Yanjuan Computational Intelligence and Software Engineering (CiSE), 2010 International C onference on Digital Object Identifier: 10.1109/CISE.2010.5676989 Publication Year: 2010 , Page(s): 1 - 3 Cited by: Papers (2) IEEE CONFERENCE PUBLICATIONS A multiple faults test generation algorithm based neural networks for digital ci rcuits is proposed in this paper because the test generation for multiple faults in digital circuits is more difficult. This algorithm change multiple faults in to single fault firstly and constructs the constraint network of the fault for t he single fault circuit with method of neural networks. The test vectors for mul tiple faults in the original circuit can be obtained by solving the minimum of e nergy function of the constraint network for the fault with chaotic searching me thod. The experimental results on some international standard circuits demonstra

te the feasibility of the algorithm. The Study on the Test Generation Algorithm of Sequential Circuit Zhou Xun ; Wang Xiao Li ; Ren Rui Control, Automation and Systems Engineering (CASE), 2011 International Conferenc e on Digital Object Identifier: 10.1109/ICCASE.2011.5997641 Publication Year: 2011 , Page(s): 1 - 2 IEEE CONFERENCE PUBLICATIONS The Study on the Test Generation Algorithm of Sequential Circuit Zhou Xun ; Wang Xiao Li ; Ren Rui Control, Automation and Systems Engineering (CASE), 2011 International Conferenc e on Digital Object Identifier: 10.1109/ICCASE.2011.5997641 Publication Year: 2011 , Page(s): 1 - 2 IEEE CONFERENCE PUBLICATIONS A kind of practical algorithm about the test generation of sequential circuit is introduced. The model and the framework are provided. The result of experiment indicated that the higher fault coverage can be obtained through the shorter tes t sequence by this algorithm. Reduced complexity test generation algorithms for transition fault diagnosis Yu Zhang ; Agrawal, V.D. Computer Design (ICCD), 2011 IEEE 29th International Conference on Digital Object Identifier: 10.1109/ICCD.2011.6081382 Publication Year: 2011 , Page(s): 96 - 101 Cited by: Papers (1) To distinguish between a pair of transition faults, we need to find a test vecto r pair (LOC or LOS type)that produces different output responses for the two fau lts. By adding a few logic gates and one modeling flip-flop to the circuit under test (CUT), we create a diagnostic ATPG model usable by a conventional single s tuck-at fault test pattern generator. Given a transition fault pair, this ATPG m odel either finds a distinguishing test or proves the faults to be equivalent. A n efficient diagnostic fault simulator is devised to find undistinguishable faul t pairs from a fault list by a test vector set. The number of fault pairs that n eeds to be targeted by the ATPG is greatly reduced after diagnostic fault simula tion. We use a previously proposed diagnostic coverage (DC) metric to determine the distinguishability (diagnosability) of a test vector set. Experimental resul ts show improved DC for benchmark circuits after applying the proposed diagnosti c ATPG algorithms. An Empirical Study of Pairwise Test Set Generation Using a Genetic Algorithm McCaffrey, J.D. Information Technology: New Generations (ITNG), 2010 Seventh International Confe rence on Digital Object Identifier: 10.1109/ITNG.2010.93 Publication Year: 2010 , Page(s): 992 - 997 Cited by: Papers (4) Pairwise test set generation is the process of producing a subset of all possibl e test case inputs to a system in situations where exhaustive testing is not pos sible or is prohibitively expensive. For a given system under test with a set of input parameters where each parameter can take on one of a discrete set of valu es, a pairwise test set consists of a collection of vectors which capture all po ssible combinations of pairs of parameter values. Generating pairwise test sets with a minimal size has been shown to be an NP-complete problem, and several det erministic generation algorithms have been published. This paper describes the r

esults of an investigation of pairwise test set generation using a genetic algor ithm. The genetic algorithm approach produced pairwise test sets with comparable or smaller (better) size compared with published results for deterministic algo rithms for 39 out of 40 benchmark problems. However, the genetic algorithm test set generation technique required significantly longer processing time in all ca ses. The results illustrate that generation of pairwise test sets using a geneti c algorithm is possible, and suggest that the technique may be both practical an d useful in certain software testing situations. Forward slicing algorithm based test data generation Samuel, P. ; Surendran, A. Computer Science and Information Technology (ICCSIT), 2010 3rd IEEE Internationa l Conference on Volume: 8 Digital Object Identifier: 10.1109/ICCSIT.2010.5564611 Publication Year: 2010 , Page(s): 270 - 274 Cited by: Papers (1) In this paper we have suggested a new method for test data generation using dyna mic forward slicing algorithm. Separating the suspicious parts of code from the original program will make the process of test data generation easier. In forwar d dynamic slicing, the slices produced are much smaller than the original progra m and the search space for testing is considerably reduced. In this paper, we di scuss the forward algorithm and the advantages of using forward dynamic algorith m for test data generation. The test cases are generated by analyzing the constr aints present in the slices constructed from forward dynamic slicing algorithm. In the proposed method, the program for which the test data to be generated is a nalyzed. Forward slicing of the program is done with respect to all the variable s whose value is changed during program execution. Slices obtained are then veri fied for statements which define certain constraints for test data generation. T his helps to clearly define the limits of test data and remove the ambiguities a bout the value of the test data which is to be generated. The test data is then generated based on the constraints. In the proposed method, since forward algori thm is used, the execution traces need not be recorded and analyzing the constra ints present in the slices will help in fault localization and debugging. This i s one of the most important advantages of our method. The Research of Path-Oriented Test Data Generation Based on a Mixed Ant Colony S ystem Algorithm and Genetic Algorithm Minjie Yi Wireless Communications, Networking and Mobile Computing (WiCOM), 2012 8th Inter national Conference on Digital Object Identifier: 10.1109/WiCOM.2012.6478716 Publication Year: 2012 , Page(s): 1 - 4 It is very practical significance to seek an effective path-oriented test data a utomatic generation method. The genetic algorithm, ant colony algorithm is commo nly used to generate test data, and the both can improve the efficiency of test data generation. But, for both algorithms, there was a little limitation to targ et path in path testing for being prone to local optimal solution. Some research ers have combined the genetic algorithm and ant colony algorithm to generate the test data path, in which the result was better. At the same time, they found hy brid ant colony algorithm was still subject to the limitation of global search a bility of ant colony algorithm. The Ant colony system algorithm is improved base d on the ant colony algorithm. It is proved that it is more suitable for global search. In the present study, we propose to combine the ant colony system algori thm and genetic algorithm (ACSGA) to generate path-oriented software testing dat a. Classical triangle discrimination problem in path-oriented software testing i s chose as a simulation experiment to verify ACSGA. The results show that the ge neration efficiency of target path has been improved apparently.