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Lab#1

Verilog code:

/* Gate Level modeling */
module mux4_1_gt(Y,i0,i1,i2,i3,s1,s0); //Port declaration output Y; input i0,i1,i2,i3,s1,s0; //Internal wire declaration wire s1n,s0n,u1,u2,u3,u4; wire y1,y2,y3,y4; //Gate Instantiation not(s1n,s1); not(s0n,s0); and(u1,s1n,s0n); and(u2,s1n,s0); and(u3,s1,s0n); and(u4,s1,s0); and(y1,i0,u1); and(y2,i1,u2); and(y3,i2,u3); and(y4,i3,u4); or(Y,y1,y2,y3,y4); endmodule

/* Data Flow Modeling */
module mux4_1df(Y,i0,i1,i2,i3,s0,s1); //Port Declaration input i0,i1,i2,i3; input s1,s0; output Y; //Logic Equation for Y assign Y=(~s1 & ~s0 & i0)| (~s1 & s0 & i1)| (s1 & ~s0 & i2)| (s1 & s0 & i3); endmodule

/* Behavioral modeling */
module mux4_1_bh(Y,i0,i1,i2,i3,s1,s0); //Port Declaration input i0,i1,i2,i3;

i0(i0). . //Output declared as a register reg Y.s0}) 2'b00: Y = i0.s0.i3(i3). . reg i3. // Instantiate the Unit Under Test (UUT) mux4_1_gt uut ( .input s1.s1(s1). always @(i0 or i1 or i2 or i3 or s1 or s0 ) begin case({s1. reg s1. . reg i2. // Wait 100 ns for global reset to finish #100. i1 = 1.s0(s0) ). output Y.i1(i1). 2'b11: Y = i3. . i3 = 0. . . 2'b10: Y = i2. reg s0. . // Outputs wire Y.i2(i2). 2'b01: Y = i1. // Inputs reg i0. initial begin // Initialize Inputs i0 = 0. endcase end endmodule Stimulus: module mux_4_1_v. i2 = 1. reg i1.Y(Y). default:Y = 1'bx.

//Port Declaration input A0.A1n. wire u0. #10 s1=1.A2). end endmodule Waveform: HOME ASSIGNMENT: Verilog code: /* Gate Level Modeling */ module decoder_3_8_gt(D. s0=0.A1. #10 s1=1. s0=1.A1. output[7:0] D. .A1).A0.A2. #10 s1=0. //Internal Wire Declaration wire A0n. s0=1. not(A1n.A2n.A0).// Add stimulus here s1=0.u3. s0=0.u1.u2. //Gate Instantiation not(A0n.

A1.A2n).A2n).A2).A2).A0.A0n.A2n).A2). //Port Declaration input A0.u0. and(D[5].A2).u2.A0n. endmodule /*Behavioral Modeling*/ module decoder_3_8_bh(sel. and(D[3]. 3'b100:res=8'b00001000. and(D[2].A1. // Port Declaration input[2:0] sel.A1n).A2). and(u1.A1n).A0. and(u3. default:res=8'b00000000. output[7:0] res.A2).u1. 3'b001:res=8'b01000000. and(D[6].u1. 3'b101:res=8'b00000100. 3'b011:res=8'b00010000. 3'b111:res=8'b00000001. //Logic Equation for D . 3'b010:res=8'b00100000.u3. output[7:0] D. //Two Input And Gate Instantiation and(u0. and(D[4].A2n). and(D[0].A1).u3.A0. // Output declared as register reg[7:0] res.A1). and(D[7].u2.not(A2n.u0.res). and(D[1]. always@(sel or res) begin case(sel) 3'b000:res=8'b10000000. 3'b110:res=8'b00000010. endcase end endmodule /*Data Flow Modeling*/ module dec_3_8_df(D. and(u2.A2.

D[7]=(A0 & A1 & A2). // Add stimulus here sel[2]=1'b0. Endmodule Stimulus: module dec_3_8_v.assign D[0]=(~A0 & ~A1 & ~A2).sel[0]=1'b1.sel[0]=1'b0. D[6]=(~A0 & A1 & A2).sel[1]=1'b0. #10 sel[2]=1'b0.sel[1]=1'b1.sel[0]=1'b0.sel[0]=1'b0.sel[0]=1'b1.sel[0]=1'b0. . #10 sel[2]=1'b1. #10 sel[2]=1'b0.sel[0]=1'b0. D[3]=(A0 & A1 & ~A2). D[2]=(~A0 & A1 & ~A2).sel[1]=1'b0. end endmodule Waveform: . // Wait 100 ns for global reset to finish #100.sel[1]=1'b1.sel[1]=1'b0. #10 sel[2]=1'b1.sel[1]=1'b0. // Instantiate the Unit Under Test (UUT) decoder_3_8_bh uut ( . // Inputs reg [2:0] sel. #10 sel[2]=1'b1. #10 sel[2]=1'b0. D[1]=(A0 & ~A1 & ~A2).sel[1]=1'b0.sel[0]=1'b1. #10 sel[2]=1'b1.sel[1]=1'b1. initial begin // Initialize Inputs sel = 0. D[5]=(A0 & ~A1 & A2). #10 sel[2]=1'b0.sel[0]=1'b1.sel[1]=1'b0. #10 sel[2]=1'b0.sel(sel).sel[0]=1'b0. D[4]=(~A0 & ~A1 & A2).sel[1]=1'b1.res(res) ). // Outputs wire [7:0] res.

a2.in2. assign out1= (ctrl == 0)? in1 : in2.a1.a1.ctrl_5. endmodule // 4’bit mux module mux4bit(out1.ctrl_4.in1.b3.a3.c1} + {c4.ctrl_4. c2.diff.a2. wire[7:0] sum. output[7:0] out.c1} .in2. mux4bit mux4(c4. input ctrl_1.in2.a3.ctrl_2). endmodule // 8’bit mux module mux8bit(out1.{c4.ctrl_1.b3. c4.b3.a0.a3.ctrl_2.in2.b2. mux4bit mux2(c2.sum.c3}.in1.b0.ctrl_3.ctrl).b2. // Declaration of internal wires wire[3:0] c1.ctrl_3).a0. input ctrl.a2. mux8bit mux5(out.b1.a1.ctrl). c3.b1. input[7:0] in1. assign sum = {c2.c3}.b0.ctrl_5). assign diff = {c2.b0.ctrl_1).Lab#4 Verilog code: Module cmx (out. input[3:0] in1. // Port Declaration input[3:0] a0. .ctrl_2.ctrl_3.diff. output[3:0] out1.b1.b2. mux4bit mux3(c3.ctrl_5).ctrl_4). // Module instantiation mux4bit mux1(c1.

b1(b1). reg [3:0] a2. .a3(a3). .ctrl_5(ctrl_5) ).a1(a1).ctrl_1(ctrl_1). reg ctrl_3.ctrl_2(ctrl_2). output[7:0] out1.b2(b2).b3(b3). .ctrl_3(ctrl_3).input ctrl. . reg [3:0] a3. . endmodule Stimulus: module Testbench_v. reg ctrl_5. . reg [3:0] a1. // Inputs reg [3:0] a0. reg ctrl_2. . .out(out). assign out1= (ctrl == 0) ? in1 : in2.b0(b0). reg [3:0] b1. reg ctrl_1. reg [3:0] b2. reg ctrl_4. reg [3:0] b0. . reg [3:0] b3.ctrl_4(ctrl_4). .a2(a2). . . . // Instantiate the Unit Under Test (UUT) complexcircuit uut ( . // Outputs wire [7:0] out. .a0(a0). initial begin // Initialize Inputs a0 = 0.

b0 = 4'b 1010. ctrl_3 = 0.b0 = 0.31 s | Elapsed : 0./xst CPU : 0.31 s | Elapsed : 0. a3 = 0. --> Parameter TMPDIR set to __projnav CPU : 0.00 / 0. a2 = 4'b 1101.1i . ctrl_4 = 0.00 s --> Reading design: complexcircuit. b3 = 0. ctrl_1 = 0. b2 = 4'b 1001. // Add stimulus here a0 = 4'b 0010. ctrl_2 = 0. Inc. ctrl_4 = 0.00 / 0. ctrl_1 = 0. a1 = 0. end endmodule Final report: Release 7. b2 = 0.prj TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) HDL Analysis 4) HDL Synthesis 5) Advanced HDL Synthesis .38 Copyright (c) 1995-2005 Xilinx.00 / 0.xst H. // Wait 100 ns for global reset to finish #100. b1 = 0. ctrl_5 = 0. ctrl_5 = 1.00 s --> Parameter xsthdpdir set to . b1 = 4'b 1100. a1 = 4'b 1000.00 / 0. a3 = 4'b 0100. ctrl_3 = 0. ctrl_2 = 0. All rights reserved. a2 = 0. b3 = 4'b 1000.

Source Options Top Module Name : complexcircuit Automatic FSM Extraction : YES FSM Encoding Algorithm : Auto FSM Style : lut RAM Extraction : Yes RAM Style : Auto ROM Extraction : Yes ROM Style : Auto Mux Extraction : YES Decoder Extraction : YES Priority Encoder Extraction : YES Shift Register Extraction : YES Logical Shifter Extraction : YES XOR Collapsing : YES Resource Sharing : YES Multiplier Style : lut Automatic Register Balancing : No ---.5.1) Device utilization summary 7.prj" Input Format : mixed Ignore Synthesis Constraint File : NO ---.General Options Optimization Goal : Speed Optimization Effort : 1 Keep Hierarchy : NO Global Optimization : AllClockNets RTL Output : Yes Write Timing Constraints : NO Hierarchy Separator : / Bus Delimiter : <> Case Specifier : maintain Slice Utilization Ratio : 100 Slice Utilization Ratio Delta : 5 .Target Parameters Output File Name : "complexcircuit" Output Format : NGC Target Device : xa2s50e-6-tq144 ---.Target Options Add IO Buffers : YES Global Maximum Fanout : 100 Add Generic Clock Buffer(BUFG) : 4 Register Duplication : YES Equivalent register Removal : YES Slice Packing : YES Pack IO Registers into IOBs : auto ---.2) TIMING REPORT ======================================================================= == * Synthesis Options Summary * ======================================================================= == ---.Source Parameters Input File Name : "complexcircuit.1) HDL Synthesis Report 6) Low Level Synthesis 7) Final Report 7.

lso Read Cores : YES cross_clock_analysis : NO verilog2001 : YES safe_implementation : No Optimize Instantiated Primitives : NO tristate2logic : Yes use_clock_enable : Yes use_sync_set : Yes use_sync_reset : Yes enable_auto_floorplanning : No ======================================================================= == ======================================================================= == * HDL Compilation * ======================================================================= == Compiling verilog file "complexcircuit. ====================================================================== * HDL Synthesis * ======================================================================= == Synthesizing Unit <mux8bit>.prj"> succeeded. Unit <complexcircuit> synthesized. Summary: inferred 2 Adder/Subtractor(s). Unit <mux8bit> synthesized. Module <mux4bit> is correct for synthesis.v" Module <complexcircuit> compiled Module <mux4bit> compiled Module <mux8bit> compiled No errors in compilation Analysis of file <"complexcircuit. Set property "resynthesize = true" for unit <complexcircuit>.v". Unit <mux4bit> synthesized. Related source file is "complexcircuit.---. Analyzing module <mux8bit>. Synthesizing Unit <mux4bit>.v". Module <complexcircuit> is correct for synthesis. Analyzing module <mux4bit>.v". Found 8-bit adder for signal <sum>.Other Options lso : complexcircuit. Module <mux8bit> is correct for synthesis. Synthesizing Unit <complexcircuit>. Found 8-bit subtractor for signal <diff>. Related source file is "complexcircuit. . Related source file is "complexcircuit. ======================================================================= == * HDL Analysis * ======================================================================= == Analyzing top module <complexcircuit>.

PACKER Warning: Lut complexcircuit_sum<3>lut driving carry complexcircuit_sum<3>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins... actual ratio is 2.. Optimizing unit <mux8bit> . This would result in an extra LUT for a feedthrough. Advanced multiplier inference . Found area constraint ratio of 100 (+ 5) on block complexcircuit. Loading device for application Rf_Device from file '2s50e.. This would result in an extra LUT for a feedthrough... PACKER Warning: Lut complexcircuit_sum<1>lut driving carry complexcircuit_sum<1>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. Building and optimizing final netlist . ======================================================================= == HDL Synthesis Report Macro Statistics # Adders/Subtractors : 2 8-bit adder : 1 8-bit subtractor : 1 ======================================================================= == ======================================================================= == * Low Level Synthesis * ======================================================================= == Optimizing unit <complexcircuit> . PACKER Warning: Lut complexcircuit_sum<5>lut driving carry complexcircuit_sum<5>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and . Advanced Registered AddSub inference .. PACKER Warning: Lut complexcircuit_sum<4>lut driving carry complexcircuit_sum<4>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. PACKER Warning: Lut complexcircuit_sum<2>lut driving carry complexcircuit_sum<2>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough..... Dynamic shift register inference ... Optimizing unit <mux4bit> .nph' in environment D:/Xilinx. This would result in an extra LUT for a feedthrough.... Mapping all equations..======================================================================= == * Advanced HDL Synthesis * ======================================================================= == Advanced RAM inference ..

PACKER Warning: Lut complexcircuit_diff<6>lut driving carry complexcircuit_diff<6>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. PACKER Warning: Lut complexcircuit_diff<3>lut driving carry complexcircuit_diff<3>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. PACKER Warning: Lut complexcircuit_diff<5>lut driving carry complexcircuit_diff<5>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough. PACKER Warning: Lut complexcircuit_diff<1>lut driving carry complexcircuit_diff<1>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough. This would result in an extra LUT for a feedthrough. This would result in an extra LUT for a feedthrough.ngr Top Level Output File Name : complexcircuit Output Format : NGC Optimization Goal : Speed Keep Hierarchy : NO Design Statistics # IOs : 45 Macro Statistics : # Adders/Subtractors : 2 # 8-bit adder : 1 # 8-bit subtractor : 1 Cell Usage : # BELS : 69 . PACKER Warning: Lut complexcircuit_sum<6>lut driving carry complexcircuit_sum<6>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough. This would result in an extra LUT for a feedthrough. This would result in an extra LUT for a feedthrough. PACKER Warning: Lut complexcircuit_diff<2>lut driving carry complexcircuit_diff<2>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. PACKER Warning: Lut complexcircuit_diff<4>lut driving carry complexcircuit_diff<4>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. ======================================================================= == * Final Report * ======================================================================= == Final Results RTL Top Level Output File Name : complexcircuit.

000 complexcircuit_sum<1>cy (complexcircuit_sum<1>_cyo) .# GND : 1 # LUT3 : 22 # LUT4 : 16 # MUXCY : 14 # VCC : 1 # XORCY : 15 # IO Buffers : 45 # IBUF : 37 # OBUF : 8 ======================================================================= == Device utilization summary: --------------------------Selected Device : xa2s50etq144-6 Number of Slices: 28 out of 768 3% Number of 4 input LUTs: 38 out of 1536 2% Number of bonded IOBs: 45 out of 102 44% ======================================================================= == TIMING REPORT NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.250 ctrl_1_IBUF (ctrl_1_IBUF) LUT3:I0->O 2 0.-----------IBUF:I->O 10 0.000 complexcircuit_sum<0>cy (complexcircuit_sum<0>_cyo) MUXCY:CI->O 1 0. Clock Information: -----------------No clock signals found in this design Timing Summary: --------------Speed Grade: -6 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found Maximum combinational path delay: 13.000 complexcircuit_sum<0>lut (sum<0>) MUXCY:S->O 1 0.468 1.554ns Timing Detail: -------------All values displayed in nanoseconds (ns) ======================================================================= == Timing constraint: Default path analysis Total number of paths / destination ports: 608 / 8 -----------------------------------------------------------------------Delay: 13.468 0.554ns (Levels of Logic = 13) Source: ctrl_1 (PAD) Destination: out<7> (PAD) Data Path: ctrl_1 to out<7> Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------.515 0.797 2.150 mux1/out1<0>1 (c1<0>) LUT4:I0->O 2 0. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE.058 0.

38.920 complexcircuit_sum<7>_xor (sum<7>) LUT3:I2->O 1 0.000 complexcircuit_sum<5>cy (complexcircuit_sum<5>_cyo) MUXCY:CI->O 0 0. reg [6:0] out.86 s | Elapsed : 3.7% route) ======================================================================= == CPU : 3. 4'd9:out=7'b1111011.920 mux5/out1<7>1 (out_7_OBUF) OBUF:I->O 4.468 0.000 complexcircuit_sum<3>cy (complexcircuit_sum<3>_cyo) MUXCY:CI->O 1 0. 4'd5:out=7'b1011011.058 0.240ns route) (61. . 4'd4:out=7'b0110011. input [3:0] in. 4'd7:out=7'b1110000. 4'd8:out=7'b1111111.554ns (8.00 / 3.602 out_7_OBUF (out<7>) ---------------------------------------Total 13.314ns logic.000 complexcircuit_sum<2>cy (complexcircuit_sum<2>_cyo) MUXCY:CI->O 1 0.000 complexcircuit_sum<6>cy (complexcircuit_sum<6>_cyo) XORCY:CI->O 1 0. 4'd3:out=7'b1111001.648 0.058 0. out). default:out=7'b0000000.3% logic.000 complexcircuit_sum<4>cy (complexcircuit_sum<4>_cyo) MUXCY:CI->O 1 0.50 / 3. output [6:0] out. 5.00 s --> Total memory usage is 84336 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) Home Assignment: Verilog code: module bcd7(in.058 0.058 0. always @(in) begin case({in}) 4'd0:out=7'b1111110. 4'd2:out=7'b1101101.058 0. 4'd6:out=7'b1011111.MUXCY:CI->O 1 0. 4'd1:out=7'b0110000.

endcase end endmodule Stimulus: .