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Ripple carry adder

When multiple full adders are used with the carry ins and carry outs chained together then this is called a ripple carry adder because the correct value of the carry bit ripples from one bit to the next. The ripple carry adder is relatively slow, since each full adder must wait for the carry bit to be calculated from the previous full adder.The gate delay can easily be calculated by inspection of the full adder circuit. For each full-adder block, there are two timing delays associated with it. First, there is the timing delay from the inputs to the sum output (t s). Second, there is the timing delay from the inputs to the carry output (t c). For a ripple carry adder of N bits, and assuming that ts >= tc, the total timing for the ripple carry adder will be (N -1)tc + ts. Therefore, as N increases, the time delay through a ripple carry adder increases accordingly. Therefore, as N increases, the time delay through a ripple carry adder increases accordingly.

Block diagram of ripple carry adder

Carry look-ahead adder

To reduce the computation time, we devised faster ways to add two binary numbers by using carry lookahead adders .We work by creating Propagate and Generate signals (P and G) for each bit position, based on whether a carry is propagated through from a least significant bit position(at least one input is a '1'), a carry is generated in that bit position (both inputs are '1'), or if a carry is killed in that bit position (both inputs are '0'). In most cases, P is simply the sum output of a half-adder and G is the carry output of the same adder. After P and G are generated the carries for every bit position are created. When the carry out signal will be 1, regardless of what the carry in signal will be. This is termed a generate of the carry out, and will occur when both inputs to a full adder are 1. Unlike generate, propagate does not determine what value carry out will be set to.

Instead, if a full adder will propagate the carry in, it means that the carry out will assume whatever value the carry in is set to. Therefore, the carry information is simply propagated through the full-adder.

The problem with the ripple-carry adder is that the carry out signal cannot be determined until the carry in input has arrived, causing the significant delay through the adder. But in case of carry look-ahead when carry in arrives, we can derive some information about the carry out. Now we analyze the timing for a four-bit adder in both the ripple carry and carry look-ahead cases. With a ripplecarry adder, the time to generate a carry out signal is usually the time propagation of a 2-bit and gate (t 2and) followed by a 3-input or gate (t3or). Therefore, the time to generate a carry out signal for a 4 bit adder will be 4(t2and + t3or). The carry look-ahead adder, on the other hand, will be limited by the time to compute a 5-bit or, a 5-bit and, and the time to compute the propagate and generate signals in each full adder. This leads to a timing delay of t5and + t5or + max(t2xor; t2and), a significant savings over the ripple-carry adder. To further reduce the time delay, it is possible to replace the xor gate used for creating the p signals with an or gate.