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International Journal of Electronics and Computer Science Engineering Available Online at www.ijecse.

org

411

ISSN- 2277-1956

Design of A Novel High Speed Dynamic Comparator with Low Power Dissipation for High Speed ADCs
Sougata Ghosh 1 ,Samraat Sharma 2 Department of Electronics and Communication Engineering 1 Assistant Professor, IFTM University, Moradabad, Uttarpradesh-244102 2 Department of Electrical Engineering 2 Assistant Professor, IFTM University, Moradabad, Uttarpradesh-244102 Email- sougata.vlsi@gmail.com , samraat3@gmail.com
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Abstract- A new CMOS dynamic comparator using dual input single output differential amplifier as latch stage suitable for high speed analog-to-digital converters with High Speed, low power dissipation and immune to noise than the previous reported work is proposed. Back to-back inverter in the latch stage is replaced with dual-input single output differential amplifier. This topology completely removes the noise that is present in the input. The structure shows lower power dissipation and higher speed than the conventional comparators. The circuit is simulated with 1V DC supply voltage and 250 MHz clock frequency. The proposed topology is based on two cross coupled differential pairs positive feedback and switchable current sources, has a lower power dissipation, higher speed, less area, and it is shown to be very robust against transistor mismatch, noise immunity. Previous reported comparators are designed and simulated their DC response and Transient response in Cadence®Virtuoso Analog Design Environment using GPDK 90nm technology. Layouts of the proposed comparator have been done in Cadence® Virtuoso Layout XL Design Environment. DRC and LVS has been checked and compared with the corresponding circuits and RC extracted diagram has been generated. After that post layout simulation with 1V supply voltage has been done and compared the speed, power dissipation, Area, delay with the results before layout and the superior features of the proposed comparator are established. Keywords – CMOS comparator, low power, High Speed, Analog-to-Digital Converter and Cadence

1. INTRODUCTION Comparators are most probably second most widely used electronic components after operational amplifiers in this world. Comparators are known as 1-bit analog-to digital converter and for that reason they are mostly used in large abundance in A/D converter. In the analog-to-digital conversion process, it is necessary to first sample the input. This sampled signal is then applied to a combination of comparators to determine the digital equivalent of the analog signal [16]. The conversion speed of comparator is limited by the decision making response time of the comparator. As the comparator is one which limits the speed of the converter, its optimization is of utmost importance. In today’s world, where demand for portable battery operated devices is increasing, a major thrust is given towards low power methodologies for high speed applications. This reduction in power can be achieved by moving towards smaller feature size processes. However, as we move towards smaller feature size processes, the process variations and other non-idealities will greatly affect the overall performance of the device. One such application where low power dissipation, low noise ,high speed, less hysteresis, less Offset voltage are required is Analog to Digital converters for mobile and portable devices. The performance limiting blocks in such ADCs are typically inter-stage gain amplifiers and comparators. The accuracy of such comparators, which is defined by its offset, along with power consumption, speed is of keen interest in achieving overall higher performance of ADCs. In the past, pre-amplifier based comparators [1] have been used for ADC architectures such as flash and pipeline. The main drawback of preamplifier based comparators is the more offset voltage. To overcome this problem, dynamic comparators are often used that make a comparison once every clock period and require much less offset voltage. However, these dynamic comparators suffer from large power dissipation compared to pre-amplifier based comparators. The main problem with all these dynamic comparators is the output signal of the latch stage is fluctuating during clock transition. This is happening due to the presence of noise in input terminals. In this paper we have designed all type of comparators

ISSN:2277-1956/V2N1-411-426

7V Table 2:TRANSISTOR DIMENSIONS(µm) (In above table for Preamplifier Based Comparator[1].412 Design of A Novel High Speed Dynamic Comparator with Low Power Dissipation for High Speed ADCs and proposed a circuit which removes the noise from the output and dissipates less power and provides high speed.[5]) ISSN: 2277-1956/V2N1-411-426 .9V 250 KHz 100 ps 100 ps 1 ns 2 ns 27 ◦C 0. 2. ANALYSIS OF DIFFERENT TYPE OF COMPARATORS: Table 1: INPUT SPECIFICATIONS SUPPLY VOLTAGE (VDD) 1V TECHNOLOGY INPUT VOLTAGE RANGE CLOCK FREQUENCY CLOCK RISE TIME CLOCK FALL TIME CLOCK DELAY CLOCK PULSE WIDTH TEMPARATURE REFERENCE VOLTAGE CADENCE GPDK 90 nm 0V‐0. Latch Type Voltage Sense Amplifier[2] Double Tail Latch Type Voltage SA[3] Dynamic Comparator without Calibration [4] Double Tail Dual Rail Dynamic Latched Comp. Keeping these things in mind we have designed a new differential amplifier based comparator.2V‐0.

The supply voltage of this comparator is 1 V.2 DC ANALYSIS: Figure 2. 2. Volume2. 2.1. Input voltage is . Back-to-back NMOS transistors in preamplifier stage keep the PMOS transistors in the preamplifier from turning off.3 TRANSIENT ANALYSIS: Figure 3. The input specifications are specified in detail in Table 1. ISSN: 2277-1956/V2N1-411-426 . both input and reference voltage is taken as the DC voltage source. Figure 2. For calculating DC analysis.1 CIRCUIT DIAGRAM: Figure 4.1.IJECSE.1 PREAMPLIFIER BASED COMPARATOR: 2. DC Response of the preamplifier based comparator.5 V. For calculating transient response a PULSE voltage source is used as input voltage source and reference voltage source is a DC voltage source. DC analysis states that the above comparator works perfectly.1 shows the schematic (designed in Cadence) of the Preamplifier based comparator circuit. Number 1 Sougata Ghosh and Samraat Sharma 413 2.1.9 V and Reference voltage is . The temperature is 27◦C. shows the DC analysis of the preamplifier based comparator. Fig:1 Preamplifier Based Comparator. shows the Transient response of the above circuit.

Transistor sizes are specified in Table 2. shows the Circuit Diagram (designed in Cadence) of Latch type voltage sense amplifier. 2. shows the DC analysis of the circuit. Transient response of the circuit.56 µW Delay: 0. Figure 4. From Figure 4.2 LATCH TYPE VOLTAGE SENSE AMPLIFIER: 2. we can say that the comparator is working fine. Input voltage is swept from -1V to +1V and reference voltage is taken as . Specifications are given in Table 1.3935 nS Speed: 2.2. ISSN: 2277-1956/V2N1-411-426 .23 V/nS 2.2 V.1 CIRCUIT DIAGRAM: Figure 4. Circuit Diagram of Latch Type Voltage Sense Amplifier.2.35 mV Static Power Dissipation: 10.54 GHz Slew Rate: 21.5.89 µW Dynamic Power Dissipation: 72. 2. The circuit comprises of a latch stage followed by buffer stage (which is nothing but a self biased differential amplifier followed by an inverter).414 Design of A Novel High Speed Dynamic Comparator with Low Power Dissipation for High Speed ADCs Figure 3.1.2 DC ANALYSIS: Figure 5.4 RESULTS: Offset Voltage: 64.

Transient response of the circuit ISSN: 2277-1956/V2N1-411-426 .3 TRANSIENT ANALYSIS: Figure 6. DC analysis of the circuit. Volume2.2. From transient response we can conclude that output of outp( as well as outn node) node which acts as an one of the input of the output buffer stage (which is mainly comprises of a self-biased differential amplifier followed by an inverter) is distorted by the noise present in the comparator. shows the transient response of the circuit. Figure 6.IJECSE. Number 1 Sougata Ghosh and Samraat Sharma 415 Figure 5. 2.

4.6 mV Dynamic Power Dissipation: 14.247 nS Speed: .2V. From the graph we can conclude that the comparator is working fine.3.416 Design of A Novel High Speed Dynamic Comparator with Low Power Dissipation for High Speed ADCs 2.27 V/nS 2.3 DOUBLE TAIL LATCH TYPE VOLTAGE SENSE AMPLIFIER: 2.2 DC ANALYSIS: Figure 8.1 CIRCUIT DIAGRAM: Figure 7. ISSN: 2277-1956/V2N1-411-426 .735 GHz Slew Rate: 18.3. Circuit Diagram of Double Tail Latch Type Voltage Sense Amplifier. Reference Voltage is taken as . shows the DC Analysis graph of the circuit.4 RESULTS: Before Layout Simulation: Offset Voltage: 339.84 Μw Delay: 1. Input voltage is taken as 1 V and swept from -1V to +1V.08 V/nS After Post Layout Simulation: Dynamic Power Dissipation: 16 µW Delay: 1.802 GHz Slew Rate: 11.35 nS Speed: . Figure 8.2.

Figure 9. Number 1 Sougata Ghosh and Samraat Sharma 417 4. shows the Dynamic Comparator without Calibration (Designed in Cadence).9 µW Delay: 1.1 CIRCUIT DIAGRAM: Figure 10.52 nS Speed: .IJECSE.3 TRANSIENT ANALYSIS: Figure 9.3.390 GHz Slew Rate: 2. Transient Analysis of the comparator. From this analysis we can say that the output of out+ node in latch stage is affected by noise and fluctuating with the clock transition as that was in the previous comparator. For the transient analysis we have taken pulse voltage source as Input stage and a dc voltage source as reference node.745 nS Speed: . shows the transient analysis of the circuit.4 DYNAMIC COMPARATOR WITHOUT CALIBRATION: 2.4.07 µW Delay: 2. 2. Specifications are given in Table 1.4 Results: Before Layout Simulation: Offset Voltage: 259. ISSN: 2277-1956/V2N1-411-426 .This figure also consists of a latch followed by a output buffer stage. Transistor sizes are specified in Table 2.16 V/nS 2.8 mV Dynamic Power Dissipation: 127.573 GHz Slew Rate: 39. Volume2.3.85 V/nS After Post Layout Simulation: Dynamic Power Dissipation: 145.

4V. Reference Voltage is taken as .2 DC ANALYSIS: Figure 11. shows the transient analysis of the circuit. DC Analysis of Comparator. Figure 11. From this analysis we can say that the output of out+ node in latch stage is affected by noise and fluctuating with the clock transition as that was in the previous comparator.4. For the transient analysis we have taken pulse voltage source as Input stage and a dc voltage source as reference node. shows the DC response of the circuit. ISSN: 2277-1956/V2N1-411-426 . From the graph we can conclude that the comparator is working fine. 2.4. 2. Dynamic Comparator without Calibration.418 Design of A Novel High Speed Dynamic Comparator with Low Power Dissipation for High Speed ADCs Figure 10.3 TRANSIENT ANALYSIS: Figure 12. Input voltage is taken as 1 V and swept from -1V to +1V.

Transistor sizes are specified in Table 2.1 mV Dynamic Power Dissipation: 105. Specifications are given in Table 1. This circuit also comprises of latch stage followed by buffer stage.1 CIRCUIT DIAGRAM: Figure 13.95 nS Speed: . ISSN: 2277-1956/V2N1-411-426 .09 V/nS After Post Layout Simulation: Dynamic Power Dissipation: 110 µW Delay: 1. Number 1 Sougata Ghosh and Samraat Sharma 419 Figure 12.570 GHz Slew Rate: 16.61 nS Speed: 1. Figure 4.37 V/nS 2.639 GHz Slew Rate: 3.5 DOUBLE-TAIL DUAL-RAIL DYNAMIC LATCHED COMPARATOR: 2.IJECSE. shows the schematic diagram of the Dynamic Comparator without Calibration (designed in Cadence). Volume2.13 Schematic Diagram of Double-Tail Dual-Rail Dynamic Latched Comparator.4 RESULTS: Before Layout Simulation: Offset Voltage: 300. 2.4.5. Transient Response of Comparator.33 µW Delay: .

420 Design of A Novel High Speed Dynamic Comparator with Low Power Dissipation for High Speed ADCs Figure 13. For the transient analysis we have taken pulse voltage source as Input stage and a dc voltage source as reference node. 2. DC Characteristics of the Comparator Figure 14.2 DC CHARACTERISTICS: Figure 14.4V. shows the DC response of the circuit. ISSN: 2277-1956/V2N1-411-426 . From the graph we can conclude that the comparator is working fine. Schematic Diagram of Double-Tail Dual-Rail Dynamic Latched Comparator. 2.5. From this analysis we can say that the output of out+ node in latch stage is affected by noise and fluctuating with the clock transition as that was in the previous comparator. Input voltage is taken as 1V and swept from -1V to +1V.3 TRANSIENT ANALYSIS: Figure 15. shows the transient analysis of the circuit.5. Reference Voltage is taken as .

The back-to-back latch stage is replaced with back-to-back dual input single output differential amplifier.37 µW Delay: 1. Another property of differential signaling is the increase in maximum achievable voltage swings.77 V/Ns After Post Layout Simulation: Dynamic Power Dissipation: 65 µW Delay: 2.15 nS Speed: . This circuit mainly is a derived version of the [5]. Here our main purpose is to eliminate the noise that is present in the latch stage and for which output is getting fluctuated with clock transition. PROPOSED COMPARATOR: Circuit Diagram of Proposed Comparator is shown in Figure 16. Number 1 Sougata Ghosh and Samraat Sharma 421 Figure 15. Volume2.49 nS Speed: .4 RESULTS: Before Layout Simulation Dynamic Power Dissipation: 57.IJECSE. 2.671 GHz Slew Rate: 10.460 GHz Slew Rate: 11. Transient Response of Double-Tail Dual-Rail Dynamic Latched Comparator. Differential amplifier has so many advantages over the conventional latch which nothing but an inverter.07 V/nS 3. It also provides simpler biasing and higher linearity. It has higher immunity to environmental noise and it rejects common mode noise or in other words it has better CMRR.5. ISSN: 2277-1956/V2N1-411-426 .

shows the DC response of the circuit. Schematic of the proposed comparator.422 Design of A Novel High Speed Dynamic Comparator with Low Power Dissipation for High Speed ADCs 3. The circuit diagram drawn in Cadence® Virtuoso Analog Design Environment is shown in Figure 16. DC response of the Proposed Comparator. ISSN: 2277-1956/V2N1-411-426 .1 CIRCUIT DIAGRAM OF PROPOSED COMPARATOR: Figure 16. Figure 17. Figure 17.

Transient Response. From table 5 we can say that though proposed comparator have highest transistor count but it still consumes less power than [2]. Table 3 shows the result summary before post layout simulation. after post layout simulation is increased by 31% but it is still less than [5]. we can say that the power dissipation of proposed comparator. each circuit was simulated in Cadence® virtuoso analog design environment. We can also say that from Table 3. 4. Figure 18. shows the transient response of the circuit. Input specifications are mentioned in Table 1. Number 1 Sougata Ghosh and Samraat Sharma 423 Figure 18. ISSN: 2277-1956/V2N1-411-426 . RESULTS & DISCUSSIONS: To compare the performance of the proposed comparators with previous works.910 GHz to 0. After post layout simulation the speed of proposed comparator is decreased from 0. From transient response it is evident that the output of the buffer stage and the output of the out+ node are almost equal which was not seen in the previous comparators either. The layout diagrams and RC extracted diagrams has been given in fig. Table 4 shows the result summary after post layout simulation. Table 2 shows the sizes of the transistors. the speed is improved with respect to [5]. [5].485 GHz but is still better than that of [5]. [4]. Technology used is gpdk 90nm technology with VDD=1V as supply voltage. Volume2. [3].IJECSE. from Table 4.

15 0.510 0.35 Speed (GHz) 0.07 110 65 2.09 10.[5] 349.8 300.24 124.23 110.52 1.85 3.424 Design of A Novel High Speed Dynamic Comparator with Low Power Dissipation for High Speed ADCs Table 3: Result summary before layout: COMPARATORS Preamplifier Based Comparator[1] Latch Type Voltage Sense Amplifier [2] Double Tail Latch Type Voltage SA[3] Dynamic Comparator without Calibration [4] Double Tail Dual Rail Dynamic Latched Comp.33 57.24 145.84 127.16 16.573 1.37 Speed (GHz) 2.77 339.671 Slew Rate (V/nS) 21.95 2.27 Latch Type Voltage Sense Amplifier [2] Double Tail Latch Type Voltage SA[3] Dynamic Comparator without Calibration [4] Double Tail Dual Rail Dynamic Latched Comp.37 11.6 259.393 14.35 19 22 23 27 Power Delay Dissipation (nS) (µW) 83.9 105.08 86.802 0.390 0.735 Slew Rate (V/nS) 18.[5] Transistor Offset Count Voltage (mV) 22 64.247 1.08 39.54 0.49 Table 4: Result summary after post layout simulation: COMPARATORS Area(µm2) Power Dissipation (µW) 16 Delay (nS) 1.460 2.639 0.745 0.23 11.1 300 1.45 0.07 ISSN: 2277-1956/V2N1-411-426 .61 1.

RC EXTRACTED ISSN: 2277-1956/V2N1-411-426 . Volume2. LAYOUT OF PROPOSED COMPARATOR: 6. Number 1 Sougata Ghosh and Samraat Sharma 425 5.IJECSE.

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