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Lecture 6: Virtual Memory Reading: Text, Chapter 8.1

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Lecture Overview
Today well cover more paging mechanisms: n Optimizations
n n n

Managing page tables (space) Efficient translations (TLBs) (time) Demand paged virtual memory (space)

n n

Recap address translation Advanced Functionality

n n n

Sharing memory Copy on Write Mapped files

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Last Time
n

We talked about memory management with the restriction that processes had to be entirely in or out of physical memory
n n n

Partitioning (fixed or dynamic) Paging Segmentation

We discussed translation between logical addresses used by program and physical addresses used by machine
n

With virtual memory schemes, logical addresses are called virtual addresses
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Recall Page Lookups

Physical Memory Virtual Address Page number Offset

Page table

Physical Address Page frame Offset

Page frame

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Paging Example
n n

Assume 32-bit virtual address space Pages are 4K (4096 bytes)

n n

Offset must be 12 bits (212 = 4096) Leaves 20 bits for virtual page number (VPN) Vpage is 0x7, offset is 0x468 Page frame number is 0x2 Seventh virtual page is stored in second physical page

Virtual address is 0x7468

n

Page table entry 0x7 contains 0x2

n n

Physical address = 0x2 << 12 + 0x468 = 0x2468

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Page Table Entries

n1 n1 n1 n2 nM nR nV nProt
n
n

n20 nPage Frame Number

Page table entries (PTEs) control mapping

Modify bit (M) says whether or not page has been written
n

Set when a write to a page occurs Set when a read or write to the page occurs Checked on each use of virtual address Read/write/execute
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Reference bit (R) says whether page has been accessed

n

Valid bit (V) says whether PTE can be used

n

Protection bits specify what operations are allowed on page

n

Page frame number (PFN) determines physical page

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Paging Limitations
n

Memory reference overhead (time)

n

2 references per address lookup (first page table, then actual memory) Solution: use a hardware cache of lookups (TLB) Need one PTE per page 32 bit address space w/ 4K pages = 220 PTEs 4 bytes/PTE = 4MB/page table 25 processes = 100MB just for page tables! Solution: page the page tables

Memory required for page table can be large (space)

n n n n n

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Managing Page Tables

n

How can we reduce this overhead?

n

Observation: Only need to map the portion of the address space actually being used (tiny fraction of entire addr space) Can dynamically extend page table Does not work if addr space is sparce (internal fragmentation)

How do we only map what is being used?

n n

Use another level of indirection: two-level page tables

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Two-Level Page Tables

n

Two-level page tables

n

Virtual addresses (VAs) have three parts:

n

Master page number, secondary page number, and offset

n n n

Master page table maps VAs to secondary page table Secondary page table maps page number to physical page Offset indicates where in physical page address is located 4K pages, 4 bytes/PTE How many bits in offset? 4K = 12 bits Want master page table in 1 page: 4K/4 bytes = 1K entries Hence, 1K secondary page tables. How many bits? Master (1K) = 10, offset = 12, inner = 32 10 12 = 10 bits CSC 468 / CSC 2204

Example
n n n n n

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Two-Level Page Tables

Physical Memory Virtual Address Master page number Secondary Offset

Physical Address Page table Page frame Offset

Master Page Table

Page frame

Secondary Page Table

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Addressing Page Tables

Where do we store page tables (which address space)? n Physical memory
n n

Easy to address, no translation required But, allocated page tables consume memory for lifetime of VAS Cold (unused) page table pages can be paged out to disk But, addressing page tables requires translation How do we stop recursion? Do not page the outer page table (called wiring)

Virtual memory (OS virtual address space)

n n n n

If were going to page the page tables, might as well page the entire OS address space, too
n

Need to wire special code and data (fault, interrupt handlers)

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Efficient Translations
n

Our original page table scheme already doubled the cost of doing memory lookups
n

One lookup into the page table, another to fetch the data Two lookups into the page tables, a third to fetch the data And this assumes the page table is in memory

Now two-level page tables triple the cost!

n n

How can we use paging but also have lookups cost about the same as fetching from memory?
n n n

Cache translations in hardware Translation Lookaside Buffer (TLB) TLB managed by Memory Management Unit (MMU)
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TLBs
n

Translation Lookaside Buffers

n n

Translate virtual page #s into PTEs (not physical addrs) Can be done in a single machine cycle Fully associative cache (all entries looked up in parallel) Cache tags are virtual page numbers Cache values are PTEs (entries from page tables) With PTE + offset, can directly calculate physical address Processes only use a handful of pages at a time
n n

TLBs implemented in hardware

n n n n

TLBs exploit locality

n

16-48 entries/pages (64-192K) Only need those pages to be mapped

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Hit rates are therefore very important

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Managing TLBs
n

Address translations for most instructions are handled using the TLB
n

>99% of translations, but there are misses (TLB miss) Hardware (Memory Management Unit)
n n n

Who places translations into the TLB (loads the TLB)?

n

Knows where page tables are in main memory OS maintains tables, HW accesses them directly Tables have to be in HW-defined format (inflexible) TLB faults to the OS, OS finds appropriate PTE, loads it in TLB Must be fast (but still 20-200 cycles) CPU ISA has instructions for manipulating TLB Tables can be in any format convenient for OS (flexible)
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Software loaded TLB (OS)

n n n n

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Managing TLBs (2)

n

OS ensures that TLB and page tables are consistent

n

When it changes the protection bits of a PTE, it needs to invalidate the PTE if it is in the TLB Invalidate all entries Why? What is one way to fix it?

Reload TLB on a process context switch

n n

When the TLB misses and a new PTE has to be loaded, a cached PTE must be evicted
n n

Choosing PTE to evict is called the TLB replacement policy Implemented in hardware, often simple (e.g., Last-NotUsed)
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Paged Virtual Memory

n

Weve mentioned before that pages can be moved between memory and disk
n

This process is called demand paging

OS uses main memory as a page cache of all the data allocated by processes in the system
n n

Initially, pages are allocated from memory When memory fills up, allocating a page in memory requires some other page to be evicted from memory
n

This is why physical memory pages are called frames

n n

Evicted pages go to disk (where? the swap file) The movement of pages between memory and disk is done by the OS, and is transparent to the application
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Page Faults
n

What happens when a process accesses a page that has been evicted?
1. When it evicts a page, the OS sets the PTE as invalid and stores the location of the page in the swap file in the PTE 2. When a process accesses the page, the invalid PTE will cause a trap (page fault) 3. The trap will run the OS page fault handler 4. Handler uses the invalid PTE to locate page in swap file 5. Reads page into a physical frame, updates PTE to point to it 6. Restarts process

But where does it put it? Have to evict something else

n

OS usually keeps a pool of free pages around so that allocations do not always cause evictions
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Address Translation Redux

n n

We started this topic with the high-level problem of translating virtual addresses into physical address Weve covered all of the pieces
n n n n n

Virtual and physical addresses Virtual pages and physical page frames Page tables and page table entries (PTEs), protection TLBs Demand paging

Now lets put it together, bottom to top

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The Common Case

n

Situation: Process is executing on the CPU, and it issues a read to an address

n

What kind of address is it? Virtual or physical?

The read goes to the TLB in the MMU

1. TLB does a lookup using the page number of the address 2. Common case is that the page number matches, returning a page table entry (PTE) for the mapping for this address 3. TLB validates that the PTE protection allows reads 4. PTE specifies which physical frame holds the page 5. MMU combines physical frame & offset into a physical addr 6. MMU reads from that physical addr, returns value to CPU

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Note: This is all done by the hardware

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TLB Misses
n

At this point, two other things can happen

1. TLB does not have a PTE mapping this virtual address 2. PTE exists, but memory access violates PTE protection bits

Well consider each in turn

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Reloading the TLB

n

If the TLB does not have mapping, two possibilities:

n

1. MMU loads PTE from page table in memory

n n

Hardware managed TLB, OS not involved in this step OS has already set up the page tables so that the hardware can access it directly Software managed TLB, OS intervenes at this point OS does lookup in page table, loads PTE into TLB OS returns from exception, TLB continues

2. Trap to the OS
n n n

n n

A machine will only support one method or the other At this point, there is a PTE for the address in the TLB
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TLB Misses (2)

Note that: n Page table lookup (by HW or OS) can cause a recursive fault if page table is paged out
n n n

Assuming page tables are in OS virtual address space Not a problem if tables are in physical memory Yes, this is a complicated situation Common case is that the PTE refers to a valid page in memory
n

When TLB has PTE, it restarts translation

n

These faults are handled quickly, just read PTE from the page table in memory and load into TLB

Uncommon case is that TLB faults again on PTE because of PTE protection bits (e.g., page is invalid)
n

Becomes a page fault

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Page Faults
n

PTE can indicate a protection fault

n n

Read/write/execute operation not permitted on page Invalid virtual page not allocated, or page not in physical memory R/W/E OS usually will send fault back up to process, or might be playing games (e.g., copy on write, mapped files) Invalid
n

TLB traps to the OS (software takes over)

n

Virtual page not allocated in address space n OS sends fault to process (e.g., segmentation fault) Page not in physical memory n OS allocates frame, reads from disk, maps PTE to physical frame
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Advanced Functionality
n

Now were going to look at some advanced functionality that the OS can provide applications using virtual memory tricks
n n n

Shared memory Copy on Write Mapped files

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Sharing
n

Private virtual address spaces protect applications from each other

n

Usually exactly what we want

But this makes it difficult to share data (have to copy)

n

Parents and children in a forking Web server or proxy will want to share an in-memory cache without copying

We can use shared memory to allow processes to share data using direct memory references
n

Both processes see updates to the shared memory segment

n

Process B can immediately read an update by process A

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How are we going to coordinate access to shared data?

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Sharing (2)
n

How can we implement sharing using page tables?

n n n

Have PTEs in both tables map to the same physical frame Each PTE can have different protection values Must update both PTEs when page becomes invalid

Can map shared memory at same or different virtual addresses in each process address space
n

Different: Flexible (no address space conflicts), but pointers inside the shared memory segment are invalid (Why?) Same: Less flexible, but shared pointers are valid (Why?)

What happens if a pointer inside the shared segment references an address outside the segment?
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Copy on Write
n

OSes spend a lot of time copying data

n n

System call arguments between user/kernel space Entire address spaces to implement fork()

Use Copy on Write (CoW) to defer large copies as long as possible, hoping to avoid them altogether
n n

Instead of copying pages, create shared mappings of parent pages in child virtual address space Shared pages are protected as read-only in child
n n

Reads happen as usual Writes generate a protection fault, trap to OS, copy page, change page mapping in client page table, restart write instruction

How does this help fork()? (Implemented as Unix vfork())

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Mapped Files
n

Mapped files enable processes to do file I/O using loads and stores
n

Instead of open, read into buffer, operate on buffer, PTEs map virtual addresses to physical frames holding file data Virtual address base + N refers to offset N in file OS reads a page from file when invalid page is accessed OS writes a page to file when evicted, or region unmapped If page is not dirty (has not been written to), no write needed
n

Bind a file to a virtual memory region (mmap() in Unix)

n n

Initially, all pages mapped to file are invalid

n n n

Another use of the dirty bit in PTE

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Mapped Files (2)

n

File is essentially backing store for that region of the virtual address space (instead of using the swap file)
n

Virtual address space not backed by real files also called Anonymous VM Uniform access for files and memory (just use pointers) Less copying Process has less control over data movement
n

Advantages
n n

Drawbacks
n

OS handles faults transparently

Does not generalize to streamed I/O (pipes, sockets, etc.)

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Summary
Paging mechanisms: n Optimizations
n n n

Managing page tables (space) Efficient translations (TLBs) (time) Demand paged virtual memory (space)

n n

Recap address translation Advanced Functionality

n n n

Sharing memory Copy on Write Mapped files

Next time: Paging policies, Read Chapter 8.2

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Midterm
n

Processes and Threads

n

3.1-3.3, 4.1 5.1 - 5.7, skip the Barbershop Problem in 5.4, and dont worry about message format in 5.6 6.1 - 6.6 9.1-9.3, but skip the queuing analysis in the performance comparison of 9.2 (you should be familiar with terms like turnaround time and be able to compute average waits for a specific (small) set of processes 7.1-7.4, skip the Buddy System
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Synchronization
n

Deadlock
n

Scheduling
n

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Memory Management
n

Projects & Assignments

n n

P1 Due tomorrow at Midnight (11:59pm) Remember: Each group has 3 grace days for the projects. A2 will be available online today. Use it as a study aid for the midterm, dont put serious time into it yet!

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