You are on page 1of 29

Introduction to VHDL

Muhammad Ali Raza Anjum

AIR University AU, E-9, Islamabad

What is VHDL?
VHDL = VHSIC Hardware Description Language VHSIC = Very High Speed Integrated Circuit A Technology Independent, Standard Language for Hardware description, simulation, and synthesis

It is a Standard (IEEE 1164) Data Exchange medium between Vendors Communications medium between CAD Tools Not Proprietary Promotes Intellectual Property and design reuse Not technology-specific Human-Readable Can be used to describe the behavior of a design, or to synthesize the design itself Supports a wide range of abstraction levels Can model a system, board, chip, registertransfer-level (RTL), or gate level designs

Outgrowth of the DARPA VHSIC Program Vendors designing large chips needed to exchange data describing their designs IBM, Texas Instruments, and Intermetrics got the contract in 83 and released VHDL 7.2 in 85 Released to the IEEE for standardization in 86 Became IEEE Std 1076-1987 Reballoted/upgraded IEEE Std 1076-1993 Also released IEEE Std 1164-1993, called STD_LOGIC_1164.

VHDL is used to: document circuits simulate circuits synthesize design descriptions Synthesis is the realization of design descriptions into circuits. In other words, it is the process by which logic circuits are created from design descriptions This lecture will at times draw upon the concepts of VHDL as a simulation language

VHDL Design Descriptions

VHDL design descriptions consist of an ENTITY and ARCHITECTURE pair The ENTITY describes the design I/O The ARCHITECTURE describes the content of the design

The Entity
A BLACK BOX The ENTITY describes the periphery of the black box (the design I/O)

d[7:0] clk

q[7:0] co

The Entity (BLACK BOX) has PORTS PORTS are points of communication PORTS are often associated with the device pins or I/Os of a component PORTS are a special class of SIGNAL PORTS have an associated SIGNAL name, MODE, and TYPE

PORT modes
A ports MODE is the direction data is transferred: IN OUT INOUT Data that goes into the entity but not out Data that goes out of the entity but not in (and is not used internally) Data that is bi-directional (goes into and out of the entity)

BUFFER Data that goes out of the entity and is also fed-back internally within the entity

PORT modes

VHDL is a strongly typed language (you cannot assign a signal of one type to the signal of another type) BIT a signal of type bit that can only take values of '0' or '1' BIT_VECTOR a grouping of bits (each bit can take value of '0' or '1') e.g.,
SIGNAL a: BIT_VECTOR(0 SIGNAL b: BIT_VECTOR(3 a <= "0111"; b <= "0101"; This means that: a(0) a(1) a(2) a(3) TO 3); -- e.g... ascending range DOWNTO 0); -- e.g... descending range

= = = =

'0' '1' '1' '1'

b(0) b(1) b(2) b(3)

= = = =

'1' '0' '1' '0'

TYPES (contd.)
INTEGER useful as index holders for loops, constants, or generics BOOLEAN can take values TRUE or FALSE ENUMERATED has user-defined set of possible values example:
TYPE states IS (start, slow, fast, stop);

The Entity declaration

VHDL description of the black box:
ENTITY black_box IS PORT ( clk, rst: IN BIT; d: IN BIT_VECTOR(7 DOWNTO 0); q: OUT BIT_VECTOR(7 DOWNTO 0); co: OUT BIT); END black_box; BLACK_BOX rst d[7:0] clk co q[7:0] MODE TYPE

The Entity: An Example

Write an entity declaration for the following: Port D is a 12-bit bus, input only Port OE and CLK are each input bits Port AD is a 12-bit, bi-directional bus Port A is a 12-bit bus, output only Port INT is a three-state output Port AS is an output only
my_design d[11:0] oe clk ad[11:0] a[11:0] int as

The Entity: Example solution

ENTITY my_design IS d: IN oe, clk: IN ad: INOUT a: OUT int: OUT as: OUT END my_design; PORT ( BIT_VECTOR(11 DOWNTO 0); BIT; x01z_VECTOR(11 DOWNTO 0); BIT_VECTOR(11 DOWNTO 0); x01z; BIT);

my_design d[11:0] oe clk ad[11:0] a[11:0] int as

Exercise #1: Entity Declaration

Write an entity declaration for the following: Port A is a 4-bit bus, input only Port EN, LD and CLK are input only Port W is an output only Port X is a 12-bit bi-directional bus Port Y is an output that is also used internally Port Z is a three-state output
your_design en ld clk a[3:0] w x[11:0] y z

Exercise #1: Solution

ENTITY your_design IS PORT ( clk, ld, en: IN BIT; a: IN BIT_VECTOR(3 DOWNTO 0); w: OUT BIT; x: INOUT x01z_VECTOR(11 DOWNTO 0); y: BUFFER BIT; z: OUT x01z); END your_design;
your_design en ld clk a[3:0] w x[11:0] y z

The Architecture
Architectures describe what is in the black box (i.e., the structure or behavior of entities) Descriptions can be either a combination of Structural descriptions Instantiations (placements of logic gates - much like in a schematic - and their connections) of building blocks referred to as components Behavioral descriptions Abstract (or high-level) descriptions, e.g.,
IF a = b THEN state <= state5;

Boolean equations, e.g.,

x <= (a OR b) AND c;

Why use behavioral VHDL?

increased productivity, e.g., a 4-bit comparator a VHDL behavioral description:
aeqb <= '1' WHEN a = b ELSE '0';

a VHDL structural description:

x1: x2: x3: x4: eq: aeqb); xnor2 PORT MAP (a(0), xnor2 PORT MAP (a(1), xnor2 PORT MAP (a(2), xnor2 PORT MAP (a(3), or4 PORT MAP (xnr(0), b(0), xnr(0)); b(1), xnr(1)); b(2), xnr(2)); b(3), xnr(3)); xnr(1), xnr(2), xnr(3),

increased portability, i.e., designs are not dependent on a library of vendor or device-specific components more readable design flow

Standard VHDL operators

Logical - defined for type BIT AND, NAND OR, NOR XOR, XNOR NOT Relational - defined for types BIT, BIT_VECTOR, INTEGER = (equal to) /= (not equal to) < (less than) <= (less than or equal to) > (greater than) >= (greater than or equal to)

Standard VHDL operators (contd.)

Unary Arithmetic - defined for type INTEGER - (arithmetic negate) Arithmetic - defined for type INTEGER + (addition) - (subtraction) Concatenation - defined for types STRING,


Introductory Examples 2 Input NAND Gate

Introductory Examples 3-input NOR gate

Introductory Examples VHDL code for a function

S = (M D' V) + (M D V') + (M D V).

Introductory Examples DFF with Asynchronous Reset

DFF with Asynchronous Reset

Introductory Examples DFF with Asynchronous Reset

Introductory Examples DFF with Asynchronous Reset

VHDL design flow

Thank you for your patience & time