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MC14001UB, MC14011UB

UB-Suffix Series
CMOS Gates
The UB Series logic gates are constructed with P and N channel
enhancement mode devices in a single monolithic structure
(Complementary MOS). Their primary use is where low power
dissipation and/or high noise immunity is desired. The UB set of
CMOS gates are inverting nonbuffered functions.

Supply Voltage Range = 3.0 Vdc to 18 Vdc


Linear and Oscillator Applications
Capable of Driving Two Lowpower TTL Loads or One Lowpower

Schottky TTL Load Over the Rated Temperature Range


Double Diode Protection on All Inputs
PinforPin Replacements for Corresponding CD4000 Series UB
Suffix Devices

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MC14001UB
Quad 2Input NOR Gate
MC14011UB
Quad 2Input NAND Gate

MARKING
DIAGRAMS
14
PDIP14
P SUFFIX
CASE 646

MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1.)


Symbol
VDD
Vin, Vout

Parameter
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)

Value

Unit

0.5 to +18.0

0.5 to VDD + 0.5

1
14

Input or Output Current


(DC or Transient) per Pin

10

mA

PD

Power Dissipation,
per Package (Note 2.)

500

mW

TA

Ambient Temperature Range

55 to +125

Tstg

Storage Temperature Range

65 to +150

TL

Lead Temperature
(8Second Soldering)

260

Iin, Iout

MC140xxUBCP
AWLYYWW

1. Maximum Ratings are those values beyond which damage to the device
may occur.
2. Temperature Derating:
Plastic P and D/DW Packages: 7.0 mW/C From 65C To 125C

SOIC14
D SUFFIX
CASE 751A

140xxU
AWLYWW
1

xx
A
WL, L
YY, Y
WW, W

= Specific Device Code


= Assembly Location
= Wafer Lot
= Year
= Work Week

ORDERING INFORMATION
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
highimpedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS  (Vin or Vout)  VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.

Semiconductor Components Industries, LLC, 2000

August, 2000 Rev. 4

Device

Package

Shipping

MC14001UBCP

PDIP14

2000/Box

MC14001UBD

SOIC14

55/Rail

MC14001UBDR2

SOIC14

2500/Tape & Reel

MC14011UBCP

PDIP14

2000/Box

MC14011UBD

SOIC14

55/Rail

MC14011UBDR2

SOIC14

2500/Tape & Reel

Publication Order Number:


MC14001UB/D

MC14001UB, MC14011UB
LOGIC DIAGRAMS
MC14001UB
Quad 2Input
NOR Gate
1
2
5
6
8
9
12
13

MC14011UB
Quad 2Input
NAND Gate
1

2
5

6
8

10

10

9
12

11

11

13

VDD = PIN 14
VSS = PIN 7
FOR ALL DEVICES

PIN ASSIGNMENTS
MC14001UB
Quad 2Input NOR Gate

MC14011UB
Quad 2Input NAND Gate

IN 1A

14

VDD

IN 1A

14

VDD

IN 2A

13

IN 2D

IN 2A

13

IN 2D

OUTA

12

IN 1D

OUTA

12

IN 1D

OUTB

11

OUTD

OUTB

11

OUTD

IN 1B

10

OUTC

IN 1B

10

OUTC

IN 2B

IN 2C

IN 2B

IN 2C

VSS

IN 1C

VSS

IN 1C

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MC14001UB, MC14011UB

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)


Characteristic

Symbol

55C

25C

125C

VDD
Vdc

Min

Max

Min

Typ (3.)

Max

Min

Max

Unit

Output Voltage
Vin = VDD or 0

0 Level

VOL

5.0
10
15

0.05
0.05
0.05

0
0
0

0.05
0.05
0.05

0.05
0.05
0.05

Vdc

Vin = 0 or VDD

1 Level

VOH

5.0
10
15

4.95
9.95
14.95

4.95
9.95
14.95

5.0
10
15

4.95
9.95
14.95

Vdc

0 Level

VIL

5.0
10
15

1.0
2.0
2.5

2.25
4.50
6.75

1.0
2.0
2.5

1.0
2.0
2.5

5.0
10
15

4.0
8.0
12.5

4.0
8.0
12.5

2.75
5.50
8.25

4.0
8.0
12.5

5.0
5.0
10
15

1.2
0.25
0.62
1.8

1.0
0.2
0.5
1.5

1.7
0.36
0.9
3.5

0.7
0.14
0.35
1.1

IOL

5.0
10
15

0.64
1.6
4.2

0.51
1.3
3.4

0.88
2.25
8.8

0.36
0.9
2.4

mAdc

Input Current

Iin

15

0.1

0.00001

0.1

1.0

Adc

Input Capacitance
(Vin = 0)

Cin

5.0

7.5

pF

Quiescent Current
(Per Package)

IDD

5.0
10
15

0.25
0.5
1.0

0.0005
0.0010
0.0015

0.25
0.5
1.0

7.5
15
30

Adc

IT

5.0
10
15

Input Voltage
(VO = 4.5 Vdc)
(VO = 9.0 Vdc)
(VO = 13.5 Vdc)
(VO = 0.5 Vdc)
(VO = 1.0 Vdc)
(VO = 1.5 Vdc)

Output Drive Current


(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)

1 Level

IIH

Vdc

IOH

Source

(VOL = 0.4 Vdc)


(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)

Total Supply Current (4.) (5.)


(Dynamic plus Quiescent,
Per Gate CL = 50 pF)

Sink

Vdc

mAdc

IT = (0.3 A/kHz) f + IDD/N


IT = (0.6 A/kHz) f + IDD/N
IT = (0.8 A/kHz) f + IDD/N

Adc

3. Data labelled Typ is not to be used for design purposes but is intended as an indication of the ICs potential performance.
4. The formulas given are for the typical characteristics only at 25C.
5. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL 50) Vfk

where: IT is in H (per package), CL in pF, V = (VDD VSS) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates
per package.

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MC14001UB, MC14011UB

SWITCHING CHARACTERISTICS (6.) (CL = 50 pF, TA = 25C)


Characteristic

Symbol

Output Rise Time


tTLH = (3.0 ns/pF) CL + 30 ns
tTLH = (1.5 ns/pF) CL + 15 ns
tTLH = (1.1 ns/pF) CL + 10 ns

tTLH

Output Fall Time


tTHL = (1.5 ns/pF) CL + 25 ns
tTHL = (0.75 ns/pF) CL + 12.5 ns
tTHL = (0.55 ns/pF) CL + 9.5 ns

tTHL

Propagation Delay Time


tPLH, tPHL = (1.7 ns/pF) CL + 30 ns
tPLH, tPHL = (0.66 ns/pF) CL + 22 ns
tPLH, tPHL = (0.50 ns/pF) CL + 15 ns

VDD
Vdc

Min

Typ (7.)

Max

5.0
10
15

180
90
65

360
180
130

5.0
10
15

100
50
40

200
100
80

5.0
10
15

90
50
40

180
100
80

Unit
ns

ns

tPLH, tPHL

ns

6. The formulas given are for the typical characteristics only at 25C.
7. Data labelled Typ is not to be used for design purposes but is intended as an indication of the ICs potential performance.

20 ns
14

VDD

INPUT

PULSE
GENERATOR

INPUT
OUTPUT

VDD

90%
50%
10%
tPLH

tPHL

CL

90%
50%
10%

OUTPUT
INVERTING

VSS

20 ns

*All unused inputs of AND, NAND gates must be


connected to VDD.
All unused inputs of OR, NOR gates must be
connected to VSS.

tTLH

Figure 1. Switching Time Test Circuit and Waveforms

VDD
14

MC14011UB CIRCUIT SCHEMATIC


(1/4 of Device Shown)

10

14 VDD

3, 4, 10, 11
1, 6, 8, 13
2, 5, 9, 12

13

12

7
VSS

7 VSS

11

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4

VOH
VOL

tTHL

MC14001UB CIRCUIT SCHEMATIC

0V

MC14001UB, MC14011UB

12
10
8.0
6.0

5.0 Vdc

4.0
b

2.0
0

8.0

6.0

15 Vdc

b a
a

10 Vdc

4.0

Vout , OUTPUT VOLTAGE (Vdc)

14

16

VDD = 15 Vdc TA = +25C


Unused input
connected to
VSS.
a One input only
10 Vdc
b Both inputs

I D, DRAIN CURRENT (mAdc)

Vout , OUTPUT VOLTAGE (Vdc)

16

2.0

-10 Vdc

-10
-10

-15 Vdc

b
a

-8.0

6.0

-6.0
-4.0
VDS, DRAIN VOLTAGE (Vdc)

a b

2.0 4.0 6.0 8.0 10 12 14 16


Vin, INPUT VOLTAGE (Vdc)

8.0

15 Vdc
b

VGS = 10 Vdc

b
c

6.0

a TA = -55C
b TA = +25C
c TA = +125C

4.0
a

2.0

a
-2.0

5.0 Vdc

4.0

10

c
b

-8.0

a TA = +125C
b TA = -55C

Figure 3. Typical Voltage Transfer


Characteristics versus
Temperature

a TA = -55C
b TA = +25C
c TA = +125C

-6.0

8.0

I D, DRAIN CURRENT (mAdc)

I D, DRAIN CURRENT (mAdc)

-4.0

VGS = -5.0 Vdc

10 Vdc

10

2.0

Figure 2. Typical Voltage and


Current Transfer Characteristics

-2.0

12

0
2.0 4.0 6.0 8.0 10 12 14 16
Vin, INPUT VOLTAGE (Vdc)

VDD = 15 Vdc Unused input


connected to
b
VSS.
a

14

Figure 4. Typical Output Source


Characteristics

2.0

5.0 Vdc

4.0
6.0
VDS, DRAIN VOLTAGE (Vdc)

8.0

Figure 5. Typical Output Sink


Characteristics

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10

MC14001UB, MC14011UB
PACKAGE DIMENSIONS

P SUFFIX
PLASTIC DIP PACKAGE
CASE 64606
ISSUE M
14

A
F

T
SEATING
PLANE

K
H

D 14 PL
0.13 (0.005)

M
M

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6

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.

DIM
A
B
C
D
F
G
H
J
K
L
M
N

INCHES
MIN
MAX
0.715
0.770
0.240
0.260
0.145
0.185
0.015
0.021
0.040
0.070
0.100 BSC
0.052
0.095
0.008
0.015
0.115
0.135
0.290
0.310
--10
0.015
0.039

MILLIMETERS
MIN
MAX
18.16
18.80
6.10
6.60
3.69
4.69
0.38
0.53
1.02
1.78
2.54 BSC
1.32
2.41
0.20
0.38
2.92
3.43
7.37
7.87
--10
0.38
1.01

MC14001UB, MC14011UB
PACKAGE DIMENSIONS

D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A03
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

A
14

B
1

P 7 PL
0.25 (0.010)

R X 45 

T
SEATING
PLANE

0.25 (0.010)

D 14 PL
M

T B

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DIM
A
B
C
D
F
G
J
K
M
P
R

MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0
7
5.80
6.20
0.25
0.50

INCHES
MIN
MAX
0.337
0.344
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0
7
0.228
0.244
0.010
0.019

MC14001UB, MC14011UB

ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be
validated for each customer application by customers technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
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alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

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MC14001UB/D