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5, MAY 2012


Synchronous FPGA-Based High-Resolution Implementations of Digital Pulse-Width Modulators
´ Denis Navarro, Oscar Luc´ ıa, Member, IEEE, Luis Angel Barrag´ an, Jos´ e Ignacio Artigas, Isidro Urriza, ´ and Oscar Jim´ enez, Student Member, IEEE

Abstract—Advantages of digital control in power electronics have led to an increasing use of digital pulse-width modulators (DPWM). However, the clock frequency requirements may exceed the operational limits when the power converter switching frequency is increased, while using classical DPWM architectures. In this paper, we present two synchronous designs to increase the resolution of the DPWM implemented on field programmable gate arrays (FPGA). The proposed circuits are based on the on-chip digital clock manager block present in the low-cost Spartan-3 FPGA series and on the I/O delay element (IODELAYE1) available in the high-end Virtex-6 FPGA series. These solutions have been implemented, tested, and compared to verify the performance of these architectures. Index Terms—Field programmable gate arrays (FPGA), power conversion, pulse-width modulated power converters.



IGITAL pulse-width modulators (DPWMs) have become a basic building block in digital control architectures of any power converter [1]–[7]. The DPWM frequency is mainly determined by the power converter operating conditions, whereas the DPWM resolution determines the accuracy in the output voltage/current control. As a consequence, the DPWM resolution has a direct impact in the power converter performance. Traditional DPWM implementations are based on counters and comparators, which generate the power converter gating signals according to several predefined thresholds [8]–[14]. For these designs, the minimum on-time step is equal to the counterclock period. Its equivalent number of bits nDPW M is nDPW M = log2 fCLK fSW (1)

where fSW is the DPWM frequency and fCLK is the counterclock frequency. Nowadays, power converters are evolving toward designs with higher switching frequencies in order to reduce the

Manuscript received February 8, 2011; revised July 13, 2011 and August 29, 2011; accepted October 20, 2011. Date of current version February 27, 2012. This research was supported in part by the Spanish MICINN under Project TEC2010-19207, Project CSD2009-00046, Project IPT-2011-1158920000, and the FPU grant AP2010-5267, and by the Bosch and Siemens Home Appliances Group. Recommended for publication by Associate Editor L. M. Tolbert. The authors are with the Department of Electronic Engineering and Communications, University of Zaragoza, Zaragoza 50018, Spain (e-mail:;;;;; Color versions of one or more of the figures in this paper are available online at Digital Object Identifier 10.1109/TPEL.2011.2173702

size of inductors and capacitors. Besides, for the digital implementation, the number of bits nDPW M has to be higher than the A/D converter resolution to avoid limit cycling [15]–[17]. As a consequence, an unfeasibly high clock frequency can result, increasing the complexity and the cost of the final implementation [18]. Moreover, recent developments in semiconductor technology enable the use of higher switching frequencies through SiC [19] and GaN [20] power devices. This allows the design of power converters with reduced size and cost, and improved dynamic behavior and power density, as shown in [21] and [22]. However, these designs require high-frequency high-resolution PWMs (HRPWMs) in order to take the most of the power converter. Another field of application for HRPWMs is the dc–dc converters, where either the output voltage [voltage regulator modules (VRMs)], the duty cycle for output-power control [23], or the switching delay mismatch between power devices [24], [25] need to be accurately tuned. As a conclusion, the evolution of both power electronics and digital control techniques makes the development of higher resolution DPWMs [26] necessary. To overcome this problem, different solutions have been proposed depending on whether the digital controller is implemented on a digital signal processor (DSP), an applicationspecific integrated circuit (ASIC), or a field programmable gate array (FPGA). In the case of DSPs, some of them include HRPWM peripherals [27]. The HRPWM module extends the time resolution capabilities of the conventional PWM allowing a minimum time step that is a fraction of the system clock. Besides, several architectures have been proposed for IC implementation [28]–[30]. They are usually based on a tapped delay line in combination with a multiplexer [28] or a hybrid counter/delay line [30]. Several FPGA-based solutions have also been proposed in the literature [31]–[38]. One common solution is to use a coarse resolution counter-based stage plus one or several on-chip digital clock manager (DCM) blocks. The PWM signal is set at the beginning of the counter period, and it is reset after a given number of clock cycles plus a certain fraction of the clock period established by the DCM. Apart from [35] and [38], the circuits previously published for delaying the reset signal are not fully synchronous. Asynchronous circuits make harder to perform static timing analysis and can result in glitching since controlling the logic and routing delays in an FPGA is more difficult than in ASIC implementations. A synchronous design, therefore, improves the reliability

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The proposed highresolution DPWM architectures using DCM blocks and IODELAYE1 blocks are explained in Sections II and III. due to the combinational circuit usage. HIGH-RESOLUTION DPWM ARCHITECTURE USING DCM BLOCKS The key of this architecture is the on-chip DCM block provided in almost every state of the art FPGA (see Fig. cycle. Fixed fine phase shifting effect. all the outputs of the DCM can be phase shifted with finer resolution. is a generalization of the DCMbased circuit in [35]. The experimental results for the proposed architectures are shown in Section IV. 3). Besides. degrading the dynamic performance. 2 shows the fine phase shift effects in the fixed mode of operation. The following DCM clock management features [40] will be used. an asynchronous circuit is used to divide the clock cycle into four quadrants. an integer in the range [−255. Section V includes further discussion and some guidelines for the architecture selection. The second proposal is based on the I/O delay element (IODELAYE1) available in the Virtex-6 FPGAs. Besides. The variable phase-shifting feature has been used in [33]. Besides phase shifting. A. the achieved resolution. In Table I. The aim of this paper is to propose two fully synchronous high-resolution DPWM architectures in order to avoid the need of using unfeasible high clock frequencies.2516 IEEE TRANSACTIONS ON POWER ELECTRONICS. A phase-shifted output with a resolution of (1/256)th of the input clock period can be obtained. the harder the design of a monotonic DPWM is. the DCM also provides the CLK90. let us consider a first version to obtain a 2-bit resolution increase (see Fig. and it allows operating the circuit at higher clock frequencies [39]. The clock feedback signal CLKFB is used to compare and lock the output signals with the input CLKIN signal. First Approach In order to introduce the proposed DCM-based highresolution DPWM architecture. it is pointed out if they are fully synchronous and glitch-free designs. 27. 2) Frequency synthesis: The DCM can generate a wide range of output clock frequencies (CLKFX output port). 1 Simplified pinout description of the DCM block. and 270◦ phase-shifted signals. CLK180. The fine phase shifting can be fixed (specified at design time and set during the FPGA configuration process) or variable. the DCM is able to condition the clock input CLKIN in order to obtain clock outputs with 50% duty Fig. 180◦ . This paper is organized as follows. This architecture is basically the one presented in [35]. easing the design portability. Finally. VOL. NO. respectively. +255]. 1) Phase shifting: The DCM provides four phase-shifted clock signals derived from the source clock CLKIN. 5. The higher the number of paths to equilibrate is. and it provides higher resolution with a straightforward implementation. Fig. It is set by means of the DCM attribute PHASE_SHIFT. Fig. In this paper. Besides. a fully synchronous design with fixed phase shifting is proposed. the conclusions of this study are drawn in Section VI. Besides. and the number of paths to manually equilibrate is given. this operating mode requires several clock cycles to change the duty cycle. respectively. and CLK270 outputs for 90◦ . 2. However. performing clock frequency division and multiplication. presented in [39]. MAY 2012 TABLE I HRPWM ARCHITECTURE COMPARISON of the circuit and eases the design process. providing a more convenient final implementation. The first proposed architecture. II. 1). . a brief comparison of the FPGA-based architectures classified according to the coarse counter frequency. Both of them are based on the resources available in modern FPGAs. it makes the design more independent of the technology. In addition to CLK0 for zero-phase alignment to the CLKIN signal.

the proposed circuit is made up of a synchronous m-bit counter. 180◦ . The two least-significant bits (LSBs) of the duty command are used by the multiplexer to select the phase-shifted signal that clears the SR latch. “CLRD” signal is set when the m−1 most-significant bits (MSBs). when the counter CNT is equal to the m−1 MSBs of the duty command dc. These signals are used to generate the SET and RESET signals that control the SR latch. 4 shows how the circuit works with m = 4. All clock signals CKi have the same period TCK with 50% duty cycle. signal CLRD activates. Generalization of the DCM-Based Architecture The previous architecture can be scaled to enhance the HRPWM resolution. Being the minimum phase shift 1/256 of TCK (k ≤ 8). are equal to CNT. Basically. with k ≥ 2. and CLK270 of DCMs are used to generate a set of p phase-shifted clocks {CKi } with 0 ≤ i < p. 3. The modulus of the counter is configurable. a p-to-1 multiplexer. In this first version. Basically. and 270◦ by flip-flops FF1. The next section presents an improved and scalable architecture in order to improve the HRPWM resolution. The advantage of this proposal in relation to others is that the digital circuit that generates the reset of the SR latch is synchronous. These four FFs implement a multiphase synchronous circuit [41]. The CLRD signal is set when the counter is equal to the m MSBs of dc. and phase shifted 90◦ .: SYNCHRONOUS FPGA-BASED HIGH-RESOLUTION IMPLEMENTATIONS OF DIGITAL PULSE-WIDTH MODULATORS 2517 Fig. FF2. dc(m:2). p = 4×r edge-triggered flip-flops. . and an SR latch whose output is the PWM signal. The use of asynchronous circuits to reset the latch makes harder to calculate timing using static timing analysis and can result in glitching since controlling the logic and routing delays in an FPGA is more difficult than in ASIC implementations. respectively.NAVARRO et al. r DCMs. DCM-based HRPWM first approach. the quadrant phase-shifted outputs of a single DCM are used. The duty cycle command dc(m:0) has m+1 bits. The SETD signal is set when the counter is zero and dc is different from zero. CLK180. and the counter “CNT” has m−1 bits. 5(a)].” Quadrant phase-shifted outputs CLK0. The resulting pulse is captured in the next clock cycle by FF0. and FF3. The counter and all DCMs are clocked by the same input clock signal “CK. and dc = “10010”. and SETD signal is set when CNT is equal to zero and dc(m:2) is different from zero. Fig. CLK90. The fine phase shifting in the fixed mode shifts the phase of all DCM output signals by a fixed fraction of the input clock period. ranging from m to 0. B. Let n = m + k be the bits of the duty cycle command dc. CKi is phase-shifted TCK /p time with respect to CKi −1 [see Fig.

the number of global clock lines that each DCM block can drive up. . Implementation This section describes an implementation example carried out to show the feasibility of the DCM-based HRPWM architecture proposed in this study. The p flip-flops [see Fig. 5. is TCK /2. MAY 2012 Fig.” the circuit is designed. and a higher clock frequency can be achieved: tp m ax (FFi ) + tp m ax (net) + tSU FFp/ 2+ i < TCK i − δm ax CKi . As the FPGA has four DCMs. and it can be easily scaled to the required p number. DCM-based HRPWM operation with dc = “10010.2518 IEEE TRANSACTIONS ON POWER ELECTRONICS. For a particular FPGA series. 5. 5(b). C. CK2) is the maximum difference in the arrival time of the rising edges of CK0 and CK2 in relation to its nominal value. the parameter k can be up to 4. (b) Multiphase synchronous circuit. the value of p is constrained by the number of DCM blocks available. 4. In order to improve speed. in which the source and destination clocks are different. the period constraint is less restrictive than in the previous design. 5(b)] implement a multiphase synchronous circuit. regardless the phase number. Fig. In the circuit shown in Fig. FFi is triggered by the rising edge of CKi . As the implementation depends on the FPGA. CKp/ 2+ i 2 (2) where tp m ax (FFi ) and tSU FFp /2+ i are the maximum clockto-output propagation time and the setup time of a flip-flop. the phase-shift value for DCMj must be set to j×64/r with 0 ≤ j < r. and the need to ensure that the routing delay of the multiplexer inputs is less than TCK /p for a monotonic behavior. As an example. This board includes a 50-MHz clock oscillator that is used as the input clock. let assume that the high-resolution DPWM is implemented in the Xilinx XC3S500E Spartan-3E FPGA of the S-3E Starter Kit board by Digilent. and δ m ax (CK0. VOL. NO. respectively. (a) Phased clock signals. 6 shows an implementation with m = 8. 27. such as the minimum allowable delay for paths. By doing so. CLRi is delayed by a fraction 1/p of TCK with respect to CLRi −1 . Fig. TCK0 /2 is the nominal time difference between rising edges of CK0 and CK2. the maximum clock frequency is not limited by the multiphase circuit but for the DCM. A p-to-1 multiplexer uses the k LSBs of dc to select the CLRi signal that clears the SR latch. tp m ax (net) is the routing delay.

However. respectively. These two DCMs can drive up to four global clock lines. in order to be close to each other and reduce routing delays. In the implementation step of the design flow. which is the maximum operating frequency for the CLK90 and CLK270 DCM outputs according to the FPGA datasheet. The proposed architecture can also be implemented using the high-end Virtex-6 FPGA series. DCM0 and DCM1 generate eight phased clocks {CK0 . The MMCM provides output signals with a 45◦ phase shift. For instance. Negativeedge-triggered flip-flops FFc and FFd avoid malfunctions due to the phase offset between CK and CK0 (±200 ps max. FF5. and CK6 . The CLKFX output of DCMx4 is connected to the input clock of the counter. CK1 . Then. and CK7 . the DCM block has been replaced by the mixed-mode clock manager (MMCM). FF6. as it occurs in Fig. according to the data sheet).: SYNCHRONOUS FPGA-BASED HIGH-RESOLUTION IMPLEMENTATIONS OF DIGITAL PULSE-WIDTH MODULATORS 2519 Fig. CK2 . CK3 }. DCM0 generates clocks CK0 . FFa and FFb store these signals. the maximum clock frequency is limited to 200 MHz. . would lead to the 168-MHz maximum operating frequency.NAVARRO et al. CK3 . which provides improved functionalities and jitter performance. Implemented high-resolution DPWM with m = 8 and k = 3. the multiphase circuit would limit the operation instead of making the most of the FPGA DCM resources. CK7 }. it is important to note that if there were paths in the implementation in which the difference between active clock edges of source and destination flip-flops were lower than the one present in this design (TCK /2). the circuit must work with the rising and falling edges of only four phased clocks {CK0 . 6. the timing constraint would be more restrictive than the one expressed in (2) and the maximum clock frequency would be reduced. DCMx4 multiplies its input clock frequency by 4. This introduces nonlinearity in the on-time step due to duty-cycle variation but this effect cannot be solved due to the routing architecture of this FPGA. and FF7 must be negative-edge triggered. . It has been described in VHDL. a clock difference of TCK /4. PHASE-SHIFT attribute of DCM0 is set to 0. and its outputs are shifted 32/256 of TCK . DCM1 generates clocks CK1 . DCM0 and DCM1 are manually placed at DCM_X0Y0 and DCM_X1Y0. and a higher resolution can be achieved . PHASE-SHIFT attribute of DCM1 is set to 32. The binary counter has 8 bits. and SETD and CLRD signals are generated from the counter output and the eight MSBs of dc as explained earlier.. DCM0 and DCM1 . In these FPGAs. CK5 . 3. and FF4. CK2 . For this implementation.. The DCM0 and DCM1 can therefore be replaced by a single MMCM. In this case. CK4 . and k = 3.

which has to be synchronized with the C clock. an MMCM. FFa and FFb are placed in order to avoid the glitches that may be present in the output of the comparator. When the enable increment/decrement signal (CE) is activated. Considering that the maximum 32-tap delay covers half a period of CK_REF. the loadable variable mode for the IODELAYE1 block is used. the CK2 clock frequency for the counter and the flip-flops is 400 MHz. 3) Loadable variable: This mode has the same functionality as the variable mode. This signal clears the SR latch to generate the desired PWM signal. This block continuously calibrates the delay elements in order to reduce the influence of process. an IODELAYE1 block. and it can be either 200 ± 10 or 300 ± 10 MHz. NO. the IDELAYCTRL is instantiated in order to autocalibrate the delay tap as previously explained. Proposed Architecture Fig. a clock that doubles the CK_REF frequency is required to clock the counter. 27. B. Implementation The proposed IODELAYE1-based HRPWM architecture has been implemented in a Xilinx Virtex-6 XC6VLX240T1FFG1156 in the ML605 Evaluation Kit featuring a 200-MHz oscillator that is used as the input clock. as it is shown in the experimental results. delaying the input signal through a 5-bit value CNTVALUEIN updated when the NVALUE signal is activated. D = 2. 9 shows the proposed implementation for an m+1-bit HRPWM. using this architecture. Virtex-6 FPGAs provides additional resources. The main difference with the previous proposal is that the multiphase synchronous circuit used to generate the signal RESET is replaced by the IODELAYE1 block. For this implementation.2520 IEEE TRANSACTIONS ON POWER ELECTRONICS. Simplified pinout description of (a) I/O delay element IODELAYE1 and (b) IDELAYCTRL block. Therefore. Fig. and O2 = 4. Fig. The REF_CK clock frequency for the IODELAYE1 block has been set to 200 MHz.” The CLRD signal is activated when dc(7:5) = CNT(7:5) = “100” = 4. allowing generating up to 10-s-width pulses with 78-ps resolution. These signals are synchronized with the clock signal C. and reset (RST). Besides. A. The output frequency for the MMCM output i is set through its attributes M. If required by the Fig. therefore. 2) Variable: The number of delay taps can be dynamically changed after configuration through the control signals CE and INC. Signals SETD and CLRD are generated as previously explained by comparing the counter output CNT with the most m−5 significant bits of the duty command dc(m:5). it allows loading the delay value through the 5-bit input CNTVALUEIN. 1) Fixed: The number of delay taps is predefined through the block attributes and it cannot be changed during operation. 10 shows the basic operation of the proposed IODELAYE1-based HRPWM architecture with dc = “10010011. calculated as td = ttap · CNTVALUEIN. the IODELAYE1 reset signal resets the delay value to a value set by the CNTVALUEIN. therefore. the delay value is reset to a predefined value. The delay time is. The resulting pulse is captured in the next clock cycle by FFb. which generates the input signal for the IODELAYE1 block DATAIN. . the IDELAYCTRL block must be also instantiated. When using the IODELAYE1 block. two edgetriggered flip-flops. increment/decrement delay (INC). VOL. it provides additional ports to configure the increment/decrement mode (CE). The IODELAYE1 block offers three different operational modes when operating in the unidirectional input delay configuration. D. achieving a resolution ttap = Δton = (1/ (32 · 2 · fCK REF )) = 78 ps. The IODELAYE1 block generates the RESET signal by delaying the CLR signal a number of tap cycles given by dc(4:0) = “10011” = 19. The IODELAYE1 block allows generating a signal (DATAOUT) delayed by a certain number of tap delays with respect to the input (DATAIN). voltage. O1 = 2. providing a fine delay-time td adjustment. Basically. and an SR latch whose output is the PWM signal. and the current delay value can be read in the CNTVALUEOUT signal. which allows controlling the desired delay. The IODELAYE1 block allows. In addition to this. as shown in Fig. depending on the mechanism used to select the number of delay taps. The reference frequency fCK REF is set through the block attribute REFCLK. In spite of this. making the implementation easier. III. In the next section. we present the proposed architecture to implement the HRPWM based on the IODELAYE1 block. 7. In addition to this. MAY 2012 When in this mode. the proposed circuit is made up of a synchronous m−4 bit counter. the number of delay taps increases or decreases depending on whether the INC signal is activated or not. The proposed design can operate correctly with 32-bit counters. If the reset signal RST is activated. 7 shows the pinout description of the IODELAYE1 and IDELAYCTRL blocks. and temperature variations by using the supplied REFCLK. 5. 8. These clock signals are generated through the MMCM configured with M = 8. These clock signals are generated through the MMCM using as a reference the board base clock CK. which allow obtaining better HRPWM resolution. and Oi as fCK O i = M/(D · Oi ). The IODELAYE1 tap resolution is given by ttap = 1/(32 · 2 · fCK REF ). HIGH-RESOLUTION DPWM ARCHITECTURE USING IODELAYE1 BLOCKS The second approach uses the I/O delay element (IODELAYE1) [42] present in Virtex-6 series FPGAs.

the complete pulse and minimum Δton can be captured and measured in a single oscilloscope screen. 10. Fig. Implemented high-resolution DPWM with the IODELAYE1 block.5-GHz bandwidth) as can be seen in Fig. and connected through a coaxial cable to a Tektronix DPO7354 oscilloscope (3. This approach has been tested using a 400-MHz clock for the MMCMs. Fig. As has been explained in Section II. 8. 11. Fig. IODELAYE1-based HRPWM operation with dc = “10010011. IV. so. the tap resolution could be improved up to 56 ps by selecting a 300-MHz clock for the IODELAYE1 block. the DCM-based architecture can also be implemented by using the MMCM blocks present in Virtex-6 FPGAs. but normally the offset will be compensated by the digital controller. The expected on-time step Δton was 625 ps. There is an offset due to the fact that the RESET signal goes through a multiplexer and the SET signal does not (as seen in Fig. The monotonic behavior can be noticed. 12 from the maximum duty (top) to the minimum (bottom). the different values of the three LSBs of the duty cycle are tested. 9. 12 shows the pulse width and pulse-width increment for the DCM-based HRPWM architecture. The DPWM signal frequency and duty cycle have been selected for test purposes.NAVARRO et al. 6). The values have been measured with the oscilloscope for nine consecutive duty commands differing in one LSB from each other. EXPERIMENTAL RESULTS This section presents the main experimental results for the proposed DCM-based and IODELAYE1-based HRPWM architectures. The DPWM output has been assigned to the SMA connector of the development boards. 13 shows the traces of the DCM-based DPWM pulses corresponding to the duty commands shown in Fig.: SYNCHRONOUS FPGA-BASED HIGH-RESOLUTION IMPLEMENTATIONS OF DIGITAL PULSE-WIDTH MODULATORS 2521 Fig. It could have been reduced as in [35] or by triggering FFe with the rising edge of CK2. IODELAYE1 operation in the loadable variable mode.” application. which leads to a 312-ps . This way. Fig.

15(a) and (b). we summarize the characteristics of the proposed HRPWM architectures. where the pulse width and pulse-width increment are shown. (b) Pulse-width increment. 14. the obtained results are within the device specifications. V. Compared to the previous implementations (see Table I). Measured DPWM pulses with horizontal scale 2. 5. mainly due to the improvement of clocking jitter in Virtex-6 FPGAs. so. 12.2522 IEEE TRANSACTIONS ON POWER ELECTRONICS. Fig. This may be solved by using only 30 taps. the maximum clock resolution. respectively. these are glitch-free designs. The experimental results for the IODELAYE1-based HRPWM architecture are shown in Fig. The experimental results including the pulse width and pulse-width increment for the MMCM-based architecture are shown in Fig. and number of PWM outputs.” (a) Pulse width. from (a) duty command “11000” to “10100”. and using the appropriate scale factor as explained in [27]. Each duty command differs in one LSB from each other. In Table II. 16 shows the traces of the IODELAYE1-based DPWM pulses for a four-tap increment. Fig. Fig. The designer should select the most suitable one according the specifications of resolution. 27. The datasheet for the Virtex-6 FPGAS specifies a ±5-ps-per-tap jitter. These results show a lower deviation than the DCM-based architecture. Experimental setup for measurements: S-3E Starter Kit board with (a) Xilinx XC3S500E and (b) ML605 Evaluation Kit with Xilinx XC6VLX240T. 11. DISCUSSION This paper details two HRPWM implementations based on the DCM and the IODELAYE1 blocks available in modern FPGAs. VOL.5 ns/div. Some guidelines are given in the following. while keeping a fully synchronous design. The DCM-based architecture uses the DCM blocks present in almost every modern FPGA. Besides. The nonmonotonic behavior of the last point “100000” is due to the jitter in the delay chain inside the IODELAYE1 block. The results show a monotonic behavior and a more stable value of the on-time step than . These measurements have been also performed for 32 consecutive values of the duty command. 13. which improve the circuit reliability. DCM-based HRPWM architecture performance for duty commands from “10000” to “11000. the proposed architectures achieves higher resolution. which correspond to one tap delay of the IODELAYE1 block. Unlike other high-resolution architectures proposed in the literature. NO. and the number of paths to equilibrate in order to achieve a monotonic behavior is minimized. instead of the 31. The expected on-time step Δton for this architecture is 78 ps. in the previous implementation. and (b) “10100” to “10000” for the DCMbased architecture. cost. MAY 2012 Fig.

MMCM-based HRPWM architecture performance for duty commands from “10000” to “11000. the increased cost compared to the Spartan-based solution does not justify it. This allows an efficient HRPWM implementation for low-cost systems. m in as a measure of the architecture efficiency. from (a) duty command dc (5:0) “100000” to “010000”. the DCM and IODELAYE1-based proposals can be compared. (b) Pulse-width increment. The DCM-based architecture can also be implemented in the Virtex-6 FPGA series using the MMCM blocks available. as each I/O tile in Virtex-6 FPGAs contains two IODELAYE1 blocks. Measured DPWM pulses for a four-tap increment with horizontal scale 2. As the number of DCM blocks is limited. . 16. recommended for systems requiring higher resolution or a high number of PWM outputs.NAVARRO et al. The DCMbased architecture obtains ηDCM = 1/(200 MHz · 625 ps) = 8. Fig. whereas the IODELAYE1-based architecture obtains ηDCM = Fig. The architecture is simplified and there is no need to equilibrate the propagation paths.” (a) Pulse width. the IODELAYE1-based architecture achieves a higher resolution by using the resources present in the high-end Virtex-6 FPGA series. This architecture is. (b) Pulse-width increment. In contrast. One of the main advantages of this proposal compared to the previous one is that it allows generating as many PWMs as needed. This architecture features a straightforward implementation as it uses a single block instead of the multiphase circuit.5 ns/div. However.” (a) Pulse width. as the IODELAYE1 block achieves better performance. and (b) “001100” to “000000” for the IODELAYE1-based architecture.: SYNCHRONOUS FPGA-BASED HIGH-RESOLUTION IMPLEMENTATIONS OF DIGITAL PULSE-WIDTH MODULATORS 2523 Fig. therefore. 14. If we consider the ratio η = 1/f clk. this architecture is recommended for systems requiring a few PWM outputs. 15. IODELAYE1-based HRPWM architecture performance for duty commands from “000000” to “100000. max · Δton . frequency is determined by the DCMs instead of the multiphase circuit.

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