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Vinod p koujalgi

Dept of ECE,Revaitm

Vinod.pk49@ymail.com

Vishwanath c

Dept of ECE,Revaitm

Vishwa.mitk@gmail.com

Abstract—

Single electron devices have ultra-low power consumption and high integration density which makes them promising candidates as basic circuit elements of the next generation ultra-dense VLSI and ULSI circuits. In this paper, implementation, simulation and analysis of 4to-2 encoder, 2-to-4 decoder, 4-to-1 multiplexer, 1-to-4 Demultiplexer using single-electron tunneling technology is presented. The logical operations of the circuits are simulated using Simon 2.0 tool based on Monte Carlo Simulation method. SIMON is a single-electron device and circuit simulator which is meant for simulating Nano Structures. Keywords- Coulomb Blockade, Single Electron Transistor SET, Tunnelling, Quantum Dot, SIMON, Monte Carlo.

known as the island the electrical potential of the island can be tuned by a third electrode known as gate, capacitively coupled to the island. Figure 1a shows the schematic of Single Electron Transistors (SETs).Since SETs are three terminal devices, the structure of SETs resembles to that of MOSFET. However, SETs have quantum dots and tunnel junctions as counter parts to the channel and p-n junctions of MOSFETs.

I.

INTRODUCTION

CMOS Technology has advanced for decades under the rule of Moore’s law. But all good things must come to an end. Researchers estimate that CMOS will reach a lower limit on feature size within the next 10 to 15 years. In order to assure further progress in the field, new computing architectures must be investigated. These nanoscale architectures are many and varied. It remains to be seen if any will become a legitimate successor to CMOS. Single electron tunneling is a process by which electrons can be transported (tunnel) across a thin insulating surface. A conducting island separated by a pair of quantum tunnel junctions creates a Single Electron Transistor (SET). SETs exhibit higher functionality than traditional MOSFETs and function best at very small feature sizes, in the neighborhood of 1nm. Many circuits must be developed before SETs can be considered a viable contender to CMOS technology. Important circuits are multiplexers, demultiplexers, encoders and decoders. We propose these possible SET circuit designs and characterize them with an SIMON simulation model. II. SINGLE ELECTRON TRANSISTOR

Schematic structure of single-electron transistor

Equivalent circuit model of Single Electron Transistor

The operation of SET relies on single electron tunneling through a nanoscale junction. The electrons tunnels are transferred one by one through the channel as shown in the below figure.

The simplest device in which the effect of Coulomb blockade can be observed is the Single Electron Transistor which consists of two electrodes known as drain and source connected through tunnel junctions to one common electrode with a low self capacitance

Basic physics of SET operation Single Electron Transistor [SET] have been made with critical dimensions of just a few nanometer using metal. The nanoparticle is separated from the electrodes by vacuum or insulation layer such as oxide or organic molecules so that only tunneling is allowed between them. the current starts to increase again. an electron is added to (removed from) the nanoparticles. like those in atoms and molecules. Single electron device based on an intrinsically quantum phenomenon. It simulates the stochastic nature of charge tunneling utilizing random number. The electrical behaviour of the tunnel junction depends on how effectively barrier transmit the electron wave. Current start to flow through the nanoparticles only when the applied voltage V is large enough to establish a voltage _ at the nanoparticles such that exp ≥ Ec = e2 / 2C This voltage is called threshold voltage and denoted by Vth. the probability that the tunneling will occur in t is R(t)=1-exp(-Γt) Therefore. semiconductor. and the applied voltage between the electrodes by V. no current can flow between the electrodes because movement of an electron onto (charging) or off (discharging) from an initially neutral nanoparticle cost energy by an amount given by equation Ec = e2 / 2C Where C is the capacitance of this system. The resistance is determined by the electron tunneling and the capacitance depends on the size of the particle. called Coulomb staircase. calculates their probabilities and chooses one of the possible events randomly. So in the I-V curve. The simulation procedure is as follows. This is done many times to simulate the transport of electrons through the network. which cost a greater amount of energy. This leads to a stepwise increase in IV curve. the discrete energy level of the electrons in the QD becomes pronounced. Unlike Field Effect transistor. To understand the electron transport properties in QD. Quantum dot [QD] is a mesoscopic system in which the addition or removal of a single electron can cause a change in the electrostatic energy or Coulomb energy that is greater than the thermal energy and can control the electron transport into and out of the QD. carbon nanotubes or individual molecules. The Monte Carlo approach starts with all possible tunnel events. This sensitivity to individual electrons has led to electronics based on single electrons. MONTE CARLO METHOD The Monte Carlo has widely been used for single electron simulation. the tunnel effect. the coupled quantum dots exhibit the properties of a molecule.A. When we start to increase V from zero. which decrease exponentially with the thickness and on the number of electron waves modes that impinge on the barrier. Once the applied voltage is large enough to overcome the Coulomb energy of two electrons. the current does not increase proportionally because it requires us to add (or remove) two electrons onto the nanoparticles. which is given by the area of tunnel junction divided by the square of wave length. For QD. This suppression of electron flow is called Coulomb blockade. Further increasing the voltage. We will discuss how the current. fig 1 III. So we can model each of the nanoparticleselectrode junctions with a resistor in parallel with a capacitor. weighted according to their probabilities. When the wave functions between two quantum dots overlap. We denote the resistors and capacitors by R1. When the applied voltage reaches Vth. Tunnel events are considered to be independent and exponentially distributed. we expect a flat zero-current regime with a width of 2Vth. R2. Let us consider a metal nanoparticle sandwiched between two metal electrodes shown in figure 1. so one can talk about “artificial atoms and molecules”. time to tunneling event is determined as ∆t= -ln(1-r)/ Γ . C1 and C2. Given a tunneling rate Γ for tunneling event. I depends on V. A SET consist of a small conducting island [Quantum Dot] coupled to source and drain leads by tunnel junctions and capacitively coupled to one or more gate.

Co=9af. The following circuit parameters were used. The junctions j1.7af and Cy=10.6af. which in turn influences the propagation of electrons.5af. 1:2 Demultiplexer A demultiplexer is a digital switch. IMPLEMENTATION OF LOGIC CIRCUITS data input lines but only one output line.6af.25af. because the voltage sources can vary with time and the distribution of electrons in the network changes with every tunnel event. Cx=11. Vin high = 16 mV. When combined with the bias capacitor C b. Cj 0. one output and one select line. In general the probabilities for possible tunnel events will change over time. B. Cx=11. Cb=4. If select line is low. a structure is formed with a switching behavior similar to that of a MOS transistor. input D0 is routed to the output else D1 is routed to output. This procedure is followed repeatedly. The tunneling event with the shortest ∆t of all is chosen as the one actually occurs. ∆t is calculated for each tunneling event starting from the present state. When cascading two tunnel junctions and attaching a capacitor to the interlaying circuit node. Cg=0. Co=9af. A 1:2 multiplexer has two input. SIMON basically calculates probabilities for every possible tunnel event and uses a Monte-Carlo scheme to choose one event from the set of possible events. It allows digital information from one source to be routed on to a several output line. Truth Table: A.25aF = Cb. The selection of particular input line is controlled by the select line. one output and one select line. input D is routed to the output Y0 else D is routed to output Y1. A 2:1 multiplexer has two input.25af.Where Γ is the tunnel rate and r is a random number uniformly distributed over the interval 0 ≤ r ˂ 1.5aF. The basic demultiplexer has one data input line but several output lines. It allows digital information from several sources to be routed on to a single output line. The selection of particular input line is controlled by the select line. IV. Cb=4. their switching behavior becomes similar to that of a CMOS p-type transistor. C0 = 9 aF. Logic equations: In SET implementation: Cg=0.5af. j2 and capacitor Cg form a SET transistor.1 aF. 2:1 Multiplexer A multiplexer is a digital switch. If select line is low. Thus for every tunnel step a new set of probabilities has to be calculated. Input Vin Output Vout C. The Inverter The circuit shown in figure 5a shows the implementation of inverter. The basic multiplexer has several . Vs = 16 mV.7af and Cy=10. Cb= 4. Logic equation: In SET implementation: Cg=0.

When input code is 00. regardless of other inputs output is 11. Cb=4. When D2 is 0 and D2 is 1 regardless of D0 and D1 output is 10. Each input code word produces a different code word at its output.6af.7af Truth Table: . If D3 is high. When input code is 01. Cx=11.25af. Cb=4. The implementation is done for 4 bit msb priority encoder ie D3 has highest priority and D0 has lowest priority. output is 1000. output code is 0100 and When input code is 11. Truth Table: E. Cx=11. Logic equations: In SET implementation: Cg=0. When input code is 10.output code is 0010.5af.5af. the input having the highest priority will take precedence. Co=9af.Truth Table: D. When D3=D2=0 and D1 is 1 regardless of D0 input output is 01.25af. The validity ouput V goes high only when any one of the input goes high. output code is 000. We have implemented 2-to-4 decoder using SET.7af and Cy=10. Co=9af. 4 bit Priority encoder A priority encoder is an encoder circuit that includes the priority function. When D3=D2=D1=0 and D0 is 1 then the ouput is 00. Decoder A decoder is a multiple input and multiple output logic circuit which converts coded inputs into coded outputs wher input and output codes are different. This indicates validity of the code. if two or more inputs are equal to 1at the same time. Logic equations: In SET implementation: Cg=0. In priority encoder.

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103. 2009. 2. Since SETs are found to be much more efficient than cmos and any other existing technologies since they consume very less power REFERENCES [1] Ken Uchida. Uchida. by H. Drouin. vol. Hiroshi Inokawa . “Single Electron Transistors and Circuits for Future Ubiquitous Computing Applications” 2006. pp. and D. Wasshuber. Fujita. and Analog Pattern [4] Katsuhiko Nishiguchi. Tanamoto. p 167-216. The implementation and simulation of a encoder. VOL. Dubuc. [7] Casper Lageweg. IEEE.H. Uchida. “Room temperature singleelectron transistor featuring gate-enhanced on-state current. [12] H. 25. S. Staring. Mar. VOL. A. 7. in Single Charge Tunneling. Jul. Akira Fujiwara. Kosina. done using monte carlo based tool. Nanotechnol. Selberherr S. multiplexer and demultiplexer has been presented in this paper. “Automatic Control of Oscillation Phase of a SingleElectron Transistor” . pp.” J. Member.W. H. IEEE. A step wise procedure was followed. Oda. Kobayashi and T. Beenakker.” V. no.IEEE Electron device Letters. H. C. Uchida. Pruvost.for Current Switching Matching”. pages 937-944 ISSN0278-0070 [11] K. Phys. IEEE.Single-Electron Random-Number Generator (RNG) for Highly Secure Ubiquitous Computing Applications. [8] B. 8. 2. 1992. Hidehiro Harata and Toshiro Hiramoto “Room-Temperature Demonstration of Integrated Silicon Single-Electron Transistor Circuits . “Design of New Logic Architectures Utilizing Optimized Suspended Gate SingleElectron Transistors. 766–768. New York: Plenum. no. “Design optimization of NEMS switches for suspended-gate single-electron transistor applications.16 Issue 9. IEEE. IEEE. vol. “Experimental study on quantum confinement effects in silicon nanowire metal-oxide-semiconductor fieldeffect transistors and single-electron transistors. JUNE 2004.J. 1. J. 30.pp 1623-1630. Member.A.. and S. Beaumont.Yukinori Ono. Fellow.IEEE “Programmable Single-Electron Transistor Logic for Future Low-Power Intelligent LSI: Proposal and Room-Temperature Operation” . IEEE. 2003. [10] SIMON. R. IEEE. Student Member. Ohba. 2. 2010. and S. Oda.” IEEE Electron Device Lett. pp. September 1997 Vol. NO. pp. 053709-1– 053709-6. “Coulomb Blockade Oscillations in Semiconductor Nanostructures”. K. Pruvost. Yasuda. ed. Hiramoto. designing first the basic gates. [3] Masumi Saitoh. Mizuta.. Member. vol. Member. T. H. StamatisVassiliadis... Mizuta. and S. [2] M. no.Technical Digest of the IEDM. Junji Koga.” IEEE Trans. C. 2009.”IEEE Trans. Appl. decoder.A. [9] A. 174–184. Grabert and M.A Simulator for Single Electronics Devices and Circuits”. Devoret. 174–184. [6] B. K. 8. Nanotechnol. January 2004. and Akira Toriumi. CONCLUSION Single Electron Encoded Latches and FlipFlopsIEEE TRANSACTIONS ON NANOTECHNOLOGY. Van Houten. NO. 177-180. [5] Ken Uchida Member. Mar..2004. 2008. C. Ryuji Ohba. vol. 3. Beauvais. 2002. exploring its operational characteristics and then designing the above mentioned logic circuits with the use of these gates.

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