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International Journal of Scientific Research Engineering & Technology (IJSRET

)
Volume 2 Issue1 pp 037-040 April 2013 www.ijsret.org ISSN 2278 - 0882

Low-Power CMOS SRAM Cell with Sleep Transistors to Control Leakage Currents
Sunil Kumar Ojha , 2Subrato Howlader Department of E.C.E 1 Amrita School of Engineering, Kasavanahalli, Carmelaram, P.O.Bangalore (INDIA) - 560 035, sunilrirt07@gmail.com 2 Oriental College of Technology, OGI campus, Thakral Nagar P.O. Bhopal (INDIA) – 462021, subrato11_howlader@yahoo.com
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ABSTRACT- As we know power consumption of
any CMOS circuit includes two major phenomena the first one is switching power & the second one is power dissipated by leakage currents from various part of the circuit. Currently the sub- threshold current becomes one of the main factors for power dissipation. To minimize the leakage current in SRAM, the power gating technique can be used & the majority of power gating technique is to use sleep transistors for controlling sub- threshold current. In this paper we have designed & analyzed two architecture of CMOS SRAM with sleep transistors and their power consumption. KEYWORDS- Conventional SRAM Cell with sleep transistors, Modified design of SRAM Cell with sleep transistors, Simulation & results, Conclusion.

Figure.1. Drain current plotted from weak to strong inversion. Furthermore, the sub-threshold region is often characterized using the log ID plotted against VGS (see Figure.1). Here an applied electric field, when the MOSFET is operating in the strong inversion region, causes carriers to drift from the channel to the drain across the depletion region. In the weak inversion, or sub-threshold region, the carriers diffuse from the source to the drain. In a MOSFET operating in sub-threshold, the carriers are emitted by the source, diffuse across the body of the device (under the gate oxide) and are collected at the drain. We can write the drain current of the MOSFET in the sub-threshold region a ID = ID0 * W/L * - Vth )/(n*kt) ----1 eq(V gs n Taking the log of both the sides with VT= KT/q (The thermal voltage) we get: log ID = log W/L + log ID0 –Vthn/n*VT –log e + [(1/(VT*n))*log e]*Vgs ----2. Now the reciprocal of sub-threshold slope is given by: Sub-threshold -1 = VT*n/log e(mv/decade) ---3.

I. INTRODUCTION
As we know that the MOSFET starts to conduct a current when Vgs = Vthn. But in reality there is a drain current, much small, when Vgs < Vthn. This current is called sub- threshold current. When the MOSFET is operating in the weak inversion region it can also be said to be operating in the subthreshold region. Sub-threshold operation can be very useful for low-power operation. CMOS imagers or battery- operated watches are examples of devices using CMOS ICs operating in the sub-threshold region. The main problems that plague circuits designed to operate in the subthreshold region are matching, noise, and bandwidth. For example, since the drain current is exponentially related to the gate-source voltage, any mismatch in these voltages can cause significant differences in the drain current.

IJSRET @ 2013

International Journal of Scientific Research Engineering & Technology (IJSRET)
Volume 2 Issue1 pp 037-040 April 2013 www.ijsret.org ISSN 2278 - 0882

If kT/q = 0.026 V = VT and n (the slope parameter) = 1, the reciprocal of the sub- threshold slope is 60 mV/decade. For the ideal MOSFET used as a switch when Vgs is less than the threshold voltage, the drain current goes to zero. The slope of the curve below Vthn in Figure.1 is then infinite. The subthreshold slope can be a very important MOSFET parameter in many applications.

II. CONVENTIONAL SRAM CELL WITH SLEEP TRANSISTORS
Below figure.2 shows the conventional SRAM cell with sleep transistors. The sleep transistors (P3, P4, N3, & N4) for pull-up and pull-down network are used to 6T SRAM cell for the purpose of reducing the leakage current. The sizing of these transistors should be done in such a way that it should maintain proper read & write operation of the cell. Here for sleep transistors we use high threshold voltage and for remain we use normal conventional threshold voltage. Other parameters are given in table-1. Figure.3. Modified design of SRAM cell with sleep transistors.

IV. SIMULATION & RESULTS
Both the circuits are simulated by HSPICE simulator using a 90nm standard CMOS process technology. The parameters of the circuit and simulation conditions are summarized in Table - I.

Table-I
Device Name PMOS (P1, P2, P3, & P4) Other than those Simulation Condition Vdd WL BL Figure.2. Conventional SRAM cell with sleep transistors. MOS Size (nm) W/L = 800/100 W/L = 400/100 Values 1.0V (DC) 1.0V @ Trapezoidal 1.0V @ Trapezoidal

A. Simulation for conventional
SRAM cell with sleep transistors Input & output waveforms of conventional SRAM cell with sleep transistors is shown in the following given figures. Given below Screenshot - 1: Shows the input wordline voltage (WL).

III. MODIFIED DESIGN OF SRAM CELL WITH SLEEP TRANSISTORS
In the shown figure.3 we have proposed a new model for SRAM cell with sleep transistors here for word line access transistors we replace the pass transistors with transmission gate so as it can pass strongly both the signal values (strong 0 & strong 1) also we use one NMOS transistor which will act as a switch at the bottom. It is used because it will help to restrict a short circuit current when the data is written in the elementary cell. The parameters are shown in table-I.

IJSRET @ 2013

International Journal of Scientific Research Engineering & Technology (IJSRET)
Volume 2 Issue1 pp 037-040 April 2013 www.ijsret.org ISSN 2278 - 0882

Given below screenshot – 2: Shows the input bit-line voltages BL (from 0 to 1) & BLB (from 1 to 0).

Given below screenshot 5: - Shows the word- line voltages WL (from 0 to 1) & WLB (from 1 to 0).

Given below screenshot – 3: Shows the output voltages out (from 0 to 1) & out_bar (from 1 to 0).

Given below screenshot – 6: Shows the input bit-line voltages BL (from 0 to 1) & BLB (from 1 to 0).

Given below screenshot – 4: Shows the power dissipation of the circuit.

Given below screenshot – 7: Shows the output voltages out (from 0 to 1) & out_bar (from 1 to 0).

B. Simulation for modified design of SRAM cell with sleep transistors
Input & output waveforms of modified SRAM cell with sleep transistors is shown in the following given figures.

Given below screenshot – 8: Shows the output power dissipation of the circuit.

IJSRET @ 2013

International Journal of Scientific Research Engineering & Technology (IJSRET)
Volume 2 Issue1 pp 037-040 April 2013 www.ijsret.org ISSN 2278 - 0882

V. Results
By simulating both the circuits we observe that the power dissipation of proposed SRAM cell with sleep transistors is much less than that of conventional SRAM cell with sleep transistors. Also we have shown the comparison of power & currents of both the circuits in the given table-II.

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 17, NO. 9, SEPTEMBER 2009. [5]. Houman Homayoun, Avesta Sasan, Alexander V. Veidenbaum, “MZZ-HVS: Multiple Sleep Modes ZigZag Horizontal and Vertical Sleep Transistor Sharing to Reduce Leakage Power in On-Chip SRAM Peripheral Circuits”, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 19, NO. 12, DECEMBER 2011. [6]. Vishal Khandelwal, and Ankur Srivastava, “Leakage Control through Fine-Grained Placement and Sizing of Sleep Transistors”, IEEE TRANSACTIONS ON COMPUTER- AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 7, JULY 2007. [7]. Sung-Mo Kang, Yusuf Leblebici, “CMOS Digital Integrated Circuits: Analysis and Design”, Tata McGraw-Hill Education.

Table-II
Conventional SRAM Proposed SRAM cell cell with sleep transistors. with sleep transistors.

Pmax ≈ 18µw Pmin ≈ 16µw PTotal ≈ 34µw Conclusion: -

Pmax ≈ 10µw Pmin ≈ 8µw PTotal ≈ 18µw

In this paper, we have design & implemented SRAM cell by using sleep transistors. We have also analyzed the power consumption of conventional SRAM cell with sleep transistors as well as proposed SRAM cell with sleep transistors. The proposed SRAM cell has used trapezoidal wave pulses for controlled switching current flow. Also to control leakage currents we have used sleep transistors. We found that it is possible to reduce the power as well as leakage currents of conventional CMOS 6T SRAM cell.

References: [1]. Ding-Ming Kwai, “Standby Current Reduction of Compilable SRAM Using Sleep Transistor and Source Line Self Bias”, 0-7803- 9735-5/06/$20.00 ©2006 IEEE. [2]. Afshin Nourivand, Chunyan Wang, And M. Omair Ahmad, “An Adaptive Sleep Transistor Biasing Scheme for Low Leakage SRAM”, 1-4244-0921-7/07 $25.00 © 2007 IEEE. [3]. B.Rajendra Naik, Rameshwar Rao ,And P.Chandrasekhar, “Design of SRAM with Sleep Transistor for Leakage Reduction”, 978- 1-4244-23156/08/$25.00 ©2008 IEEE. [4]. De-Shiuan Chiou, Shih-Hsin Chen, and ShihChieh Chang, “Sleep Transistor Sizing for Leakage Power Minimization Considering Charge Balancing”, IJSRET @ 2013