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Short channel effects in MOST

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Short-channel device: channel length is comparable to
depth of drain and source junctions and depletion
width
In general, short channel effects visible when L s 1µm
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If we shrink all length scales, a number of physical effects
can become relevant that are unimportant in larger
MOSFETs:
Channel shortening, Punch-through, Tunneling,
Thermionic leakage, Threshold voltage variation with
drain bias, Velocity saturation, Field-dependent
mobility, Avalanche breakdown, Oxide failure …..
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1) Channel shortening
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Happens when V
DS
approaches V
DSsat
= V
GS
- V
T
In long channel devices, we get pinch-off and saturation
of I
D
In short devices, AL can be a significant fraction of L
Electric field is large over AL - that’s where most of the
source-drain voltage is dropped.
Drift is enhanced by high electric field there: result is a
boost in I
D
as V
DS
is increased beyond V
DSsat
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2) Threshold voltage variation
In threshold voltage equation, channel depletion region
is assumed to be created by gate voltage only -
Depletion regions around source and drain neglected:
valid if channel length is much larger than depletion
region depths
In short-channel devices, depletion regions from drain
and source extend into channel
As channel length L decreases, threshold voltage
decreases
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Source
depletion
region
Drain
depletion
region
Gate-induced depletion region
N+
source
N+
drain
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Drain-induced barrier lowering (DIBL)
– As V
DS
increases, threshold voltage decreases
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3) Carrier velocity saturation
• Field along channel - As channel length is reduced,
electric field increases
• Electron drift velocity is proportional to electric field
only for small field values - For large electric field,
velocity saturates
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If the velocity of carriers becomes large enough,
they can lose energy through inelastic processes.
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If L is large compared to the inelastic scattering length,
one sees velocity saturation
Results:
• There is a significant reduction in current.
• Saturation current now depends linearly on V
GS
- V
T
rather than quadratically in longer devices.
I
Dsat
= W C
ox
(V
GS
– V
T
) v
sat
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Ballistic Devices
If the channel is short enough (below the mean free path
length scales), then the carriers can travel from source to
drain without going through any significant scattering
events. This is called ballistic transport.
Carriers can often gain an average velocity over v
sat
.
This phenomena is known as velocity overshoot.
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4) Avalanche breakdown
• At high enough energies/fields (in regions with large
electric fields, like drain pinch-off area), carriers can
produce electron-hole pairs through collisions.
• These pairs may not be bound, and can also get
accelerated, leading to more pairs.
• Result is runaway I
D
not controlled by V
G
.
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5) Thermionic leakage / tunneling
• Both processes can be relevant.
• Tunneling matters more for smaller devices
• Thermionic emission matters more at higher
temperatures.
• Biggest problem is that these can lead to substantial
off-currents and power dissipation
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Tunneling Leakage Current
For SiO
2
films thinner than 1.5 nm, tunneling leakage
current has become the limiting factor.
HfO
2
has several orders lower leakage for the same EOT.
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Unless a new gate dielectric (other than SiO
2
) is
developed, leakage current due to tunneling will force
minimum transistor dimensions to be 25-50 nm.
HfO
2
has a relative dielectric constant of ~ 24, six times
larger than that of SiO
2
.
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• Fowler-NordheimTunneling
• For very thin gate oxide, electrons can tunnel through
the gate oxide, resulting in current from gate to drain or
source
ox
E
E
ox FN
e WLE C I
0
2
1
÷
=
E
0
, C
1
constants
E
ox
= electric field across
oxide
Gate leakage
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To keep V
T
variations under control, the gate oxide
thickness is reduced. Eventually this leads to tunneling
of electrons from the gate to the silicon substrate which
results in leakage current.
Gate oxide considerations
The maximum acceptable leakage current for a device
with V
dd
= 1V is about 1A/cm
2
.
This corresponds to an oxide thickness of roughly 2 nm.
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Leakage
Power consumed even when circuit is inactive - Leakage
power raises temperature of chip - Can cause
functionality problem in some circuits
Reducing transistor leakage
– Long-channel devices
– Small drain voltage
– Large threshold voltage V
T
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Leakage
• Leakage vs. performance tradeoff:
For high-speed, need small V
T
and L
For low leakage, need high V
T
and large L
• Process scaling
– V
T
reduces with each new process (historically)
– Leakage increases ~10X!
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6) Mobility degradation
• In short-channel devices, µ
n
and µ
p
are not constant -
As vertical electric field increases, surface mobility
decreases
( )
T GS
V V ÷ +
=
q
µ
µ
1
0
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As V
DS
is increased, drain depletion region gets
deeper and extends further into channel –
For very large V
DS
, source and drain depletion
regions can meet → punch-through
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7) Punch-through
8) Hot-carrier effect
– Increased electric fields causes increased electron
velocity
– High energy electrons can tunnel into gate oxide
– This changes the threshold voltage (increases V
T
for NMOS)
– Can lead to long-term reliability problems
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High-velocity electrons can also impact the drain,
dislodging holes
Holes are swept towards the substrate → cause
substrate current – impact ionization
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Both devices have same W/L ratio
Short-channel device has ~ 40% lesser current
Linear dependence of current on V
GS
in short-channel
device – it is quadratic in long channel device
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MOS I
D
-V
GS
Characteristics
0
1
2
3
4
5
6
0 0.5 1 1.5 2 2.5
V
GS
(V)
(for V
DS
= 2.5V, W/L = 1.5)
X 10
-4
9) Subthreshold conduction
When V
GS
< V
T
, transistor is “off”
– However, small drain current I
D
still flows -
subthresholdleakagecurrent
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10) Oxide failure
High energy electrons accelerated by large fields can
break bonds - can effectively introduce enough defect
states in gap to permit sufficient conduction to get
runaway failure.
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Trends:
• Shorter channel lower threshold voltage
• Higher V
D
lower threshold voltage.
• Thinner oxide higher threshold voltage.
To keep up with source-drain field, we must scale oxide
to be thinner.
Thinner oxide higher gate field enhanced
surface scattering at channel-oxide interface
lower effective mobility. 29
MOSFET Technology Scaling
New technology node every three years or so.
Defined by minimum metal line width.
All feature sizes, e.g. gate length, are ~70% of previous
node.
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MOSFET Scaling
• Constant Field
– Ideal, helps reliability
• Constant Voltage
– Traditional, board-level compatible
• Hybrid - practical
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Constant Field Scaling
• Uniformly scale all linear dimensions by factor of s > 1
• Also reduce supply voltage by s
• Preserves field strength
• Also known as full scaling
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Before
Scaling
After Scaling
Length L L/s
Width W W/s
Oxide Thickness t
ox
t
ox
/s
Junction Depth X
j
X
j
/s
Supply Voltage V
DD
V
DD
/s
Threshold Voltage V
T
V
T
/s
Doping Densities N
A
,N
D
sN
A
,sN
D
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ox scaled ox
sC C =
,
s
C
C
g
scaled g
=
,
Capacitance:
s
I
s
V
s
V
s L
s W
s t
I
D
T GS
ox
ox
scaled D
=
|
.
|

\
|
÷ =
2
,
2
µc
Current:
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Power:
2
s
P
s
I
s
V
P
D DS
scaled
( )( ) A
P
s L s W
s P
A
P
scaled
scaled
= =
2
Power density :
Delay:
( )( )
s s I
s V s C
scaled
t
t = =
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Constant Voltage scaling
Before Scaling After Scaling
Length L L/s
Width W W/s
Oxide Thickness t
ox
t
ox
/s
Junction Depth X
j
X
j
/s
Supply Voltage V
DD
V
DD
Threshold Voltage V
T
V
T
Doping Densities N
A
,N
D
s
2
N
A
,s
2
N
D
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(for velocity non-saturated devices)
ox scaled ox
sC C =
,
s
C
C
g
scaled g
=
,
Capacitance:
Current:
D T GS
ox
ox
scaled D
sI V V
s L
s W
s t
I
2
,
2
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( )( )
2
s sI
V s C
scaled
t
t = =
Delay:
Power:
sP sI V P
D DS scaled
Power density:
( )( )
A P s
s L s W
sP
A
P
scaled
scaled
/
3
= =
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Current:
Power:
D scaled D
I I =
,
P I V P
D DS scaled
= =
(for velocity-saturated devices)
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( )( )
s I
V s C
scaled
t
t = =
Delay:
Power density:
( )( )
A P s
s L s W
P
A
P
scaled
scaled
/
2
= =
(velocity-saturated case)
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Hybrid scaling
Scale voltage, but not as fast as process
Some circuits need a minimum voltage (band-gap,
analog circuits, etc) - Low thresholds have leakage
problems
Result is somewhere between constant field and
constant voltage - delay ~ 1/s, higher power than
constant field but less than constant voltage
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0
5
10
15
20
25
30
35
40
45
0.65um 0.5um 0.35um 0.25um 0.18um 0.13um 0.1um
D
e
l
a
y

(
p
s
)Gate
Cu Interconnect
Al Interconnect
Cu + Gate
Al + Gate
gate
Cu interconnect
Al interconnect
Cu + gate
Al + gate
Scaled Width
Delay in ps
Wire - 43um long & 0.8um high
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