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**ECE/Comp Sci 352 Digital Systems Fundamentals
**

Charles R. Kime Section 2 – Fall 2001

Logic and Computer Design Fundamentals

**Chapter 2 – Combinational Logic Circuits – Part 7
**

Charles Kime & Thomas Kaminski © 2001 Prentice Hall, Inc

**NAND and NOR Implementation
**

We found that we could implement general Boolean equations with these three primitives:

• AND • OR • NOT

In this section we will find that either of two gates, the NAND gate or the NOR gate can be used to implement arbitrary logic functions. We use the Positive Logic Convention (where all signals are active high) and a small circle to on a symbol to represent NOT or invert.

Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc

Chapter 2-Part 7 2

1

S A NAND gate with one input degenerates to an inverter. Z ) = X + Y + Z S We call this symbol for a NAND gate the Invert - OR since all inputs are inverted. Z ) = X ⋅ Y ⋅ Z S NAND comes from NOT AND.NAND Gates S The basic positive logic NAND gate is denoted by the following symbol: • AND-Invert (NAND) X Y Z F( X . We call this symbol for a NAND gate an AND-Invert.) S Applying DeMorgan's Law gives: • Invert-OR (NAND) X Y Z F( X . the AND function with a NOT applied.it is sometimes more logically descriptive to use one form over the other. Logic and Computer Design Fundamentals © 2001 Prentice Hall. The small circle represents the invert function. S Both symbols represent the NAND gate . followed by the OR function.. e. Y . Inc X⋅Y⋅Z = X + Y + Z Chapter 2-Part 7 3 NAND Gates (Cont. S If we apply DeMorgan's Law we get: Logic and Computer Design Fundamentals © 2001 Prentice Hall. I. Y . Inc Chapter 2-Part 7 4 2 .

B. Inc 5 NAND Implementation (Cont. The second level is one 2-input NAND gate using Invert-OR.NAND Function Implementation S NAND gates can implement a simplified Sum-of- Products form.C. C. B. Thus. D ) = A ⋅ B + C ⋅ D S The first level is two 2-input NAND gates using AND- Invert. note that the bubbles are on opposite ends of the same line. C. Inc Chapter 2-Part 7 6 3 . we have: G( A . Using the NAND relationship.D) C D This form of the implementation is the Sum-of-Products form. B. they can be combined and deleted: A B G(A. Constructing two level NAND-NAND gate circuit: A B C D G( A. D ) = A⋅B ⋅ C⋅D = A⋅B + C⋅D = A ⋅B + C⋅D Logic and Computer Design Fundamentals Chapter 2-Part 7 © 2001 Prentice Hall.) In the implementation. Logic and Computer Design Fundamentals © 2001 Prentice Hall.

D) C D S A sum-of-products (SOP) form results S To implement an equation like: F(A.B. S By X = X . the bubbles are on opposite ends of the same line. they can be combined and deleted: A B G(A.) S In the implementation.B.NAND Implementation (Cont.C) = A + BC.B.B. add an inverter to the output: A F'(A.C) B C S To implement the complement of F using NAND gates. the NAND for A degenerates to a NOT since there is only one input Logic and Computer Design Fundamentals © 2001 Prentice Hall.C) B C Logic and Computer Design Fundamentals © 2001 Prentice Hall. Inc Chapter 2-Part 7 8 4 . Inc Chapter 2-Part 7 7 Degenerate AND Term S The degenerate NAND becomes an inverter: A F(A.C.

y . Inc Chapter 2-Part 7 9 Summary: Two-Level NAND Circuits S Find minimum literal SOP form for F and F S Select SOP form with smallest literal count S Convert selected form to NAND circuit using AND-invert (inverters for single literal AND terms) and invert-OR symbols S If SOP form for F used.z) Logic and Computer Design Fundamentals © 2001 Prentice Hall.z) z F’ (w. Logic and Computer Design Fundamentals © 2001 Prentice Hall.y.y. Inc Chapter 2-Part 7 10 5 .x. add inverter to circuit output. x .x. z ) = y z + w x + x y + yw z 1 1 1 w 1 0 4 12 8 1 0 0 1 1 5 13 9 1 0 0 0 3 7 15 11 1 1 0 0 2 6 14 10 1 1 x w 0 4 1 0 1 5 1 0 3 7 1 1 2 6 1 12 1 8 0 13 1 9 0 15 0 11 0 14 0 10 x z F(w.NAND-NAND Example S Implement:y F( w .

since it is logically an OR function followed by an invert. Inc X +Y +Z = X Y Z Chapter 2-Part 7 12 6 . We call this symbol for a NOR gate an OR-Invert. Z) = X +Y+Z S NOR comes from NOT OR. e. I. too. Y. By DeMorgan's Law we have the following Invert-AND symbol for a NOR gate: Invert-AND X Y Z A single-input NOR gate is an inverter. Y.NOR Gates The basic positive logic NOR gate (Not-OR) is denoted by the following symbol: OR-Invert (NOR) X Y Z F(X. The small circle represents the invert function. Z) = X +Y+Z This is called the OR-Invert. Logic and Computer Design Fundamentals © 2001 Prentice Hall. S If we apply DeMorgan's Law we get: Logic and Computer Design Fundamentals © 2001 Prentice Hall. the OR function with a NOT applied.. Inc Chapter 2-Part 7 11 NOR Gates S The basic positive logic NOR gate is denoted by the following symbol: • OR-Invert (NOR) X Y Z F(X.

Constructing two-level NOR-NOR circuit: A B C D G( A. Z ) = X Y Z S We call this symbol for a NOR gate the Invert- AND since all inputs are inverted. S Using the NOR relationship. C. Y . Inc Chapter 2-Part 7 14 7 .NOR Gates (Cont. C. S A NOR gate with one input degenerates to an inverter. B. The second level is one 2-input NOR gate using Invert-AND. Logic and Computer Design Fundamentals © 2001 Prentice Hall. D) = (A + B)⋅ (C + D ) S The first level is two 2-input NOR gates using OR- Invert. S Both symbols represent the NOR gate . D) =(A+B)+(C+D) = (A+B) (C+D) = (A+B) (C+ D) Logic and Computer Design Fundamentals © 2001 Prentice Hall. B. we have: G( A .) S Applying DeMorgan's Law gives: • Invert-AND (NOR) X Y Z F( X . Inc Chapter 2-Part 7 13 NOR Function Implementation S NAND gates can implement a simplified Sum-of- Products form. followed by the AND function.it is sometimes more logically descriptive to use one form over the other.

Inc Chapter 2-Part 7 15 Graphical Transformations The relations from the previous slide lead to the following transformations: (A • B ) = ((A • B )')' ⇔ (A '+ B ')' (A ' • B ')' (A '+ B ') (A ' • B ') (A + B ) = ⇔ ((A +B )')' (A • B )' ⇔ (A + B )' ⇔ Recall that two bubbles in series can be removed from the circuit Logic and Computer Design Fundamentals © 2001 Prentice Hall. Inc Chapter 2-Part 7 16 8 .e.Useful Transformations From Involution (i. we get the following useful equivalences: (A•B) = ((A•B)')' ⇔ (A+B) = ⇔ ((A+B)')' (A•B)' ⇔ (A'+B')' (A'•B')' (A'+B') (A+B)' ⇔ (A'•B') These simple transformations can be used to manipulate a two level network. (A')' = A) and DeMorgan's Law. Logic and Computer Design Fundamentals © 2001 Prentice Hall.

General Two-level Implementations We need to consider whether the form of a two-level implementation is to be: 1.) Given a two level implementation desired. Given a function F expressed as a Karnaugh Map. AND-NOR or ORNAND) can be handled by complementing the function. SOP (AND-OR) or POS (OR-AND). Complemented output functions (i. Logic and Computer Design Fundamentals © 2001 Prentice Hall. (Also use for NOR-NOR) OR-NAND Circle 1's in the K-Map and minimize (POS complemented) SOP. 2. Inc Chapter 2-Part 7 17 General Implementations (Cont. Use DeMorgan's to transform to POS. we can use the same general procedures we have used before to minimize the function and express it in SOP or POS form. Inc Chapter 2-Part 7 18 9 . Logic and Computer Design Fundamentals © 2001 Prentice Hall.e. Use DeMorgan's to transform to POS. use the previous transfromations to get it into one of the below forms. Then follow the steps to transform the function to the desired form: For Type: Use: AND-OR Circle 1's in the K-Map and minimize (SOP Form) (Also use for NAND-NAND) AND-NOR Circle 0's in the K-Map and minimize (SOP complemented) OR-AND Circle 0's in the K-Map and minimize (POS Form) SOP.

Inc Chapter 2-Part 7 19 Implementation Example 2 B Implement the function in AND-NOR. 1 0 We can remove the "Inverter" and replace it with the complement of the input variable Logic and Computer Design Fundamentals © 2001 Prentice Hall. 1 1 A 1 1 0 0 1 0 Logic and Computer Design Fundamentals © 2001 Prentice Hall.Implementation Example 1 B 1 A 1 1 C 0 0 1 Implement the function in NOR-OR. Inc Chapter 2-Part 7 20 10 .

Inc Chapter 2-Part 7 21 Multi-level NAND Example 1 S F = A B’ + A C’ + B A’ + B C’ 15 inputs and 8 gates* = A A’ + A B’ + A C’ + B A’ + B B’ + B C’ = A (A’ + B’ + C’) + B (A’ + B’ + C’) 7 inputs and 4 gates A B C * Counting inverters (NOTS) as 1 input and 1 gate Logic and Computer Design Fundamentals © 2001 Prentice Hall. Inc F Chapter 2-Part 7 22 11 .Multi-level NAND Implementations S Add inverters in two-level implementation into the cost picture S Attempt to “combine” inverters to reduce the term count S Attempt to reduce literal + term count by factoring expression into POSOP or SOPOS Logic and Computer Design Fundamentals © 2001 Prentice Hall.

Inc Chapter 2-Part 7 23 12 .Multilevel NAND Example 2 S F = AB + AD’ + BC + CD’ Logic and Computer Design Fundamentals © 2001 Prentice Hall.

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