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HFC0100

QUASI RESONANT CONTROLLER
The Future of Analog IC Technology

DESCRIPTION
The HFC0100 is a peak current mode controller with Green Mode Operation. Its high efficiency feature over the entire line and load range meets the stringent world-wide energy efficiency requirements. The HFC0100 integrated with a high voltage current source, its valley detector ensures minimum Drain-Source voltage switching (Quasi-Resonant operation). When the output power falls below a given level, the controller enters the burst mode. The HFC0100 features variable protections like Thermal Shutdown (TSD), Vcc Under voltage Lockout (UVLO), Over Load Protection (OLP), Over Voltage Protection (OVP). The HFC0100 is available in the 8-pin SOIC8 package.

FEATURES
• • • • • • • • • • • • • Universal Main Input Voltage (85~265VAC) Quasi-Resonant Operation Valley Switching for high efficiency and EMI Active Burst Mode for low standby power consumption Internal High Voltage Current Source High level of integration, allows a very low number external component count Maximum Frequency Limited Internal Soft Start Internal 250nS Leading Edge Blanking Thermal shutdown (auto restart with hysteresis) Vcc Under Voltage Lockout with Hysteresis (UVLO) Over Voltage Protection Over Load Protection.

APPLICATIONS
• • • Battery charger: cellular phone, digital camera, video camera, electrical shaver, emergency lighting system, etc Standby power supply: CRT-TV, ProjectionTV, LCD-TV, PDP-TV, Desk top PC, Audio system, etc SMPS: Inc jet printer, DVD player/recorder, VCR, CD player, Set top box, Air conditioner, refrigerator, washing machine, dish washer, Adapter for NB, etc

For MPS green status, please visit MPS website under Quality Assurance. “MPS” and “The Future of Analog IC Technology” are Registered Trademarks of Monolithic Power Systems, Inc.

HFC0100 Rev. 1.01 www.MonolithicPower.com 9/23/2011 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved.

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Patent Protected.01 www. 1.com 9/23/2011 MPS Proprietary Information. All Rights Reserved.HFC0100—QUASI RESONANT CONTROLLER TYPICAL APPLICATION T1 * + + * RTN * HV N/C VCC VSD 4 3 2 1 5 6 7 8 Drive CS GND FB HFC0100 Rev. Unauthorized Photocopy and Duplication Prohibited.MonolithicPower. 2 . © 2011 MPS.

.... -60°C to +150°C ESD Capability Human Body Model (All Pins except HV) ........ -0...................g... 3 . 4-layer PCB..... and the ambient temperature TA......150°C Thermal Shut Down ....... Unauthorized Photocopy and Duplication Prohibited................... °C/W Notes: 1) Exceeding these ratings may damage the device............. For RoHS compliant packaging....7V to 700V Vcc.01 www... DRV to GND ........-0.... HFC0100HS–LF–Z) PACKAGE REFERENCE TOP VIEW VSD VCC NC HV 1 2 3 4 8 7 6 5 FB GND CS Drive ABSOLUTE MAXIMUM RATINGS (1) Recommended Operation Conditions (3) HV Break Down Voltage ........... 4) Measured on JESD51-7.....3W Junction Temperature ... the junction-toambient thermal resistance θJA.........3V to 7V (2) Continuous Power Dissipation…(TA = +25°C) ………………………………………………................3V to 22V FB.................... Exceeding the maximum allowable power dissipation will cause excessive die temperature..... (TJ) ...1..................... and the regulator will go into thermal shutdown....... 45 . Patent Protected... VSD to GND .......260°C Storage Temperature ......... All Rights Reserved.... HFC0100HS–Z)...... +125°C Thermal Resistance (4) SOIC8 .com 9/23/2011 MPS Proprietary Information. 3) The device is not guaranteed to function outside of its operating conditions......0kV ESD Capability Machine Model .-0........................ 200V Operating Vcc range ......96 .....50°C Lead Temperature ........................ The maximum allowable continuous power dissipation at any ambient temperature is calculated by PD (MAX) = (TJ (MAX)-TA)/θJA...150°C Thermal Shut Down Hysteresis .. © 2011 MPS....... 1...MonolithicPower. Internal thermal shutdown circuitry protects the device from permanent damage......8V to 20V Maximum Junction Temp. add suffix –Z (e............ CS.......HFC0100—QUASI RESONANT CONTROLLER ORDERING INFORMATION Part Number* HFC0100HS Package SOIC8 Top Marking HFC100 Free Air Temperature (TA) -40°C to +125°C *For Tape & Reel.................. add suffix –LF (e.. 2... θJA θJC HFC0100 Rev......... 2) The maximum allowable power dissipation is a function of the maximum junction temperature TJ (MAX)...........g.

4 .4 -700 10.65 160 7.8 ----------70 -8 V -0. All Rights Reserved. Vcc=13V Min 1. Latch off Icc2 phase.8 120 6.5 200 9 -------nS μS μS μS V kΩ nS Ω Ω Unit mA μA V V V V mA μA kΩ V -mS V V V mV mV Break Down Voltage VBR Supply Voltage Management (Pin Vcc) Vcc Upper Level at which the Internal VCCH High Voltage Current Source Stops Vcc Lower Level at which the Internal VCCL High Voltage Current Source Triggers Vcc Re-charge Level at which the Vccp protection occurs Internal IC Consumption.6 3. Unauthorized Photocopy and Duplication Prohibited.HFC0100—QUASI RESONANT CONTROLLER ELECTRICAL CHARACTERICS For typical value TJ=25℃ Parameter Start-up Current Source (Pin HV) Charging current from Pin HV Leakage current from Pin HV Symbol Icharge Ileak Conditions Vcc=6V. Vcc=12V VCC=6V ---------40 -High State.5 -0.7 55 10 7.0 450 10 4. 1.VHV=400V With auxiliary supply.01 www.8 4. Ipin2=3.0mA Low State. 1nF Load on Icc1 Drive Pin.5 2. Ipin2=-2.2 -Fs=100kHz. © 2011 MPS.0mA Pull down from 2V to -100mV 7 -0. Feedback Management (Pin FB) Internal Pull Up Resistor RFB Internal Pull Up Voltage Vup FB Pin to Current Limit Division Ratio Idiv Internal Soft-Start Time Tss FB Decreasing Level at which the VBURL controller enter the Burst Mode FB Increasing Level at which the VBURH controller leave the Burst Mode Over Load Set Point VOLP Valley Switching Management (Pin VSD) Valley Switching Threshold Voltage VVSD Valley Switching Hysteresis Vhys Pin VSD Clamp Voltage Valley Switching Propagation Delay VVSDH VVSDL TVSD Minimum Off Time Tmin Re-start time After Last Valley detect Trestart Transition OVP Sampling Delay TOVPS Pin VSD OVP reference level VOVP Internal Impedance Rint Current Sampling Management (Pin CS) Leading Edge Blanking TLEB Driving Signal (Pin DRIVE) Sourcing Resistor RH Sinking Resistor RL HFC0100 Rev. Patent Protected.8 8 5.5 3 2.6 7.6 -------Typ 2 20 -11.4 0.com 9/23/2011 MPS Proprietary Information. VHV=400V.7 3.5 0. Internal IC Consumption.6 --13 8.5 6 24 250 17 7 Max 2.MonolithicPower.

5V will trigger a burst mode operation. This Pin ensures adequate creepage distance. Unauthorized Photocopy and Duplication Prohibited. 1. © 2011 MPS.HFC0100—QUASI RESONANT CONTROLLER PIN FUNCTIONS Pin # 1 2 3 4 5 6 7 8 Name VSD Vcc N/C HV Drive CS GND FB Description Input from the auxiliary flyback signal.7V will trigger an over load protection. This pin is connected to an external bulk capacitor of typically 22uf and a ceramic capacitor of typically 0. All Rights Reserved. It also offers a fixed OVP detection. Input of the current sense.1uF.01 www. Input for the start up current unit. 5 . Output of the driving signal.com 9/23/2011 MPS Proprietary Information. Supply voltage Pin. Patent Protected. it ensures discontinuous operation and valley switching.MonolithicPower. Ground. by connecting an optocoupler to this Pin. A feedback voltage of 3. The Pin sets the peak current limit. and a feedback voltage of 0. HFC0100 Rev.

2 11 -40 -20 10 7.com 9/23/2011 MPS Proprietary Information. 1.7 7.4 -40 -20 0 25 50 85 105 125 30 -40 -20 0 25 50 85 105 125 7 -40 -20 0 25 50 85 105 125 TEMPERATURE (OC) TEMPERATURE (OC) TEMPERATURE (OC) HFC0100 Rev. VHV=400V) Vs Temperature 800 700 600 500 400 ICHARGE (mA) ICC1 (uA) 900 2.5 10 11 12 13 14 15 16 17 18 VCC (V) 1 -40 -20 0 25 50 85 105 125 TEMPERATURE (oC) 12 11. All Rights Reserved.1 Vcc Lower Level at which the Internal High Voltage Current Source Triggers Vs Temperature Pin FB Internal Pull Up Resistor Vs Temperature 12 11 VCCH (V) VCCL (V) 11.HFC0100—QUASI RESONANT CONTROLLER TYPICAL PERFORMANCE CHARACTERISTICS TA=25℃ IC Consumption Vs Vcc (No Output Load) 1100 1000 3400 3000 FS=100kHz FS=60kHz 2600 FS=100kHz IC Consumption Vs Vcc (1nF Output Load) 3 Charging Current From Pin HV (Vcc=6V.3 8. Unauthorized Photocopy and Duplication Prohibited.5 VVSD (mV) 3. 6 . Patent Protected.5 ICC1 (uA) 2200 1800 1400 1000 10 11 12 13 14 15 16 17 18 VCC (V) FS=60kHz 2 1.4 11.5 8.9 7.6 7.8 Vcc Upper Level at which the Internal High Voltage Current Source Stops Vs Temperature 8.8 VOLP (V) TMIN (us) 60 50 40 8 3.MonolithicPower.5 3.5 -40 -20 9 0 25 50 85 105 125 0 25 50 85 105 125 8 -40 -20 0 25 50 85 105 125 TEMPERATURE (oC) TEMPERATURE (oC) TEMPERATURE (oC) Over Load Set Point Vs Temperature 4 Valley Switching Threshold Voltage Vs Temperature 80 70 Minimum Off Time Vs Temperature 9 8.6 11.01 www. © 2011 MPS.

© 2011 MPS. 7 .2 Pin VSD Internal Impedance Vs Temperature 30 28 26 6. Unauthorized Photocopy and Duplication Prohibited.01 www. Patent Protected.8 TSAMPLE (us) VREF (V) Pin VSD OVP reference level Vs Temperature 6.com 9/23/2011 MPS Proprietary Information.1 3.MonolithicPower.6 3.9 22 20 -40 -20 5. All Rights Reserved.2 3 -40 -20 0 25 50 85 105 125 TEMPERATURE (OC) 6 24 5. 1.4 3.8 -40 -20 0 25 50 85 105 125 TEMPERATURE (OC) 0 25 50 85 105 125 TEMPERATURE (OC) Sourcing Resistor Vs Temperature 30 Sinking Resistor Vs Temperature 20 600 FB Decreasing Level at which the controller enter the Burst Mode Vs Temperature 25 15 VBURH(mV) 550 20 10 500 15 5 450 10 -40 -20 0 25 50 85 105 125 0 -40 -20 0 25 50 85 105 125 400 -40 -20 0 25 50 85 105 125 TEMPERATURE (OC) TEMPERATURE (OC) TEMPERATURE (OC) 800 FB Increasing Level at which the controller leave the Burst Mode Vs Temperature 750 VBURH(mV) 700 650 600 -40 -20 0 25 50 85 105 125 TEMPERATURE (OC) HFC0100 Rev.HFC0100—QUASI RESONANT CONTROLLER TYPICAL PERFORMANCE CHARACTERISTICS (continues) TA=25℃ OVP Sampling Delay Vs Temperature 4 3.

(3) Protection Unit CS(6) GND(7) FB(8) Figure 1— Block Diagram HFC0100 Rev.HFC0100—QUASI RESONANT CONTROLLER BLOCK DIAGRAME Vcc(2) Power Management Start Up Unit HV(4) VSD(1) Valley Detector Driving Signal Managment Peak Current Limitation Burst Mode Control Drive(5) N. © 2011 MPS. All Rights Reserved. Patent Protected.MonolithicPower.C. 8 .01 www. 1. Unauthorized Photocopy and Duplication Prohibited.com 9/23/2011 MPS Proprietary Information.

Quasi-Resonant Operation The HFC0100 operates in Discontinuous Conduction Mode (DCM).8μS. When the output power falls below a given level. there are virtually no primary switch turn on losses and no secondary diode recovery losses.8V.01 www. the regulator enters the burst mode. shows as figure 4.HFC0100—QUASI RESONANT CONTROLLER OPERATION The HFC0100 incorporates all the necessary features needed to a reliable Switch Mode Power Supply.com 9/23/2011 MPS Proprietary Information. the Vcc capacitor supplies HFC0100 to maintain Vcc. © 2011 MPS. Start-Up Initially. 9 . 1. It ensures the reduction of the EMI noise. HFC0100 employs an internal minimum off time limiter---7. VDS 100V/div Toff≥7. When the voltage: (VDS − Vin )x Naux 24kΩ x < 55mV Npri 24kΩ + R VSD Figure 2—Valley Detector VDS 100V/div Valley Switching 4us/div Figure 3—Valley Switching To ensure the switching frequency below the EN55022 start limit---150kHz. Patent Protected. The IC starts switching and the internal high voltage current source unit is stopped as soon as the voltage on Pin Vcc reaches the threshold VCCH—11. VDS —Drain Source Voltage of the primary FET VIN—Input Voltage Naux —Auxiliary Winding Turns of the transformer Npri —Primary Winding Turns of the transformer The valley detector sends out a valley signal to turn on the primary FET. An internal minimum off time limiter prevents the free running frequency to exceed 150kHz. Before the supply is taken over by the auxiliary winding of the transformer.MonolithicPower. the IC is self supplying from the internal high voltage current source unit which drawn from the HV pin. Its valley detector ensures minimum Drain-Source voltage switching (Quasi-Resonant operation). Figure3 shows a typical drain source voltage waveform with valley switching.8uS 2us/div Figure 4—Minimum Off Time Limit HFC0100 Rev. Unauthorized Photocopy and Duplication Prohibited. Figure2 shows the valley detector unit. All Rights Reserved. The valley detector ensures minimum Drain-Source voltage switching (Quasi-Resonant operation) As a result.

01 www. The auxiliary winding take over VCC VCCH=11. typical 3.5V. when the feedback voltage exceeds the threshold VOLP—3. the output voltage is drawn below the set point. HFC0100 Rev. the FB voltage will be high enough temporarily to mistrigger the OLP. VVSD Sampling Here Driving Signal Figure 5—Vcc Under-Voltage Lock Out Over-Voltage Protection (OVP) The positive plateau of auxiliary winding voltage is proportional to the output voltage. this reduces the current through the optocoupler LED.com 9/23/2011 MPS Proprietary Information. If the voltage: VO × N aux 24kΩ × > 6V N SEC 24kΩ + R VSD 0V TOVPS Figure 7 Over Load Protection (OLP) The maximum output power is limited by the maximum switching frequency and maximum primary peak current.5μS. the Vcc external bulk capacitor is re-charged by it. The controller stays fully latched in this position until the Vcc is decreased down to 3V. shows as Figure 7. and the HFC0100 stops the switching cycle and goes into latched fault condition. it shuts off the switching cycle. During the start up or load transient. Unauthorized Photocopy and Duplication Prohibited.HFC0100—QUASI RESONANT CONTROLLER VCC Under-Voltage Lock-out When the Vcc below the UVLO threshold-8V. As soon as the default disappears. the HFC0100 stops switching and the internal high voltage current source unit re-starts. By continuously monitoring the Pin FB voltage. the power supply resumes operation. VO—Output voltage Naux —Auxiliary Winding Turns of the transformer NSEC—Secondary transformer Winding Turns of the The OVP circuit is triggered. the OVP use the auxiliary winding voltage instead of directly monitoring the output voltage. e. 1.7V.g. Figure 5 shows the typical waveform with Vcc under voltage lock out.8V V CCL=8V ON Internal Current Source OFF Figure 6—OVP Sample Unit To avoid the mis-trigger due to the oscillation of the leakage inductance and the parasitic capacitance. when the user unplugs the power supply from the main supply and re-plugs it.MonolithicPower. OLP circuit is designed to be triggered after Vcc is decreased below 8. 10 . © 2011 MPS. The Figure 6 shows the OVP sample unit. the OVP sampling has a TOVPS blanking. All Rights Reserved. The HFC0100 enters a safe low power operation that prevents from any lethal thermal or stress damage. If the output consumes more than the maximum output power. thus increases the FB voltage. Patent Protected. which also reduces the transistor current. to prevent this undesired protection.

MonolithicPower. 1.5V VFB 200mV/div VDrive 5V/div 40us/div Figure 8—Burst Mode Thermal Shutdown (TSD) To prevents from any lethal thermal damage.. This delay will cause an overshoot of the peak current. the path.7V. the current limit is clamped at 1V when VFB is bigger than 3. is blocked. And the current limit is determined by the FB signal. to smoothly establish the output voltage. Leading Edge Blanking In order to avoid the premature termination of the switching pulse due to the parasitic capacitance. the HFC0100 has an internal soft-start circuit that increases the current comparator inverting input voltage. The burst mode operation alternately enables and disables switching cycle of the MOSFET thereby reducing switching loss in the no load or light load conditions. the FB voltage decreases.5V. the delay time is the inherent characteristic of the control circuit. During the blanking time. switching resumes. the HFC0100 stops the switching cycle when the FB voltage drops below the threshold VBURL—0. and capacitors. The FB voltage then falls and rises repeatedly. As soon as the inner temperature drops below 100DegC. the HFC0100 enters the burst mode operation. an internal leading edge blanking (LEB) unit is employed between the CS Pin and the current comparator input. Figure 9 shows the leading edge blanking. VLimit TLEB =250nS VBURL:0.01 www.com 9/23/2011 MPS Proprietary Information. CS Pin to the current comparator input. The pulse width to the power switching device is progressively increased to establish the correct working conditions for transformers. t Figure 9—Leading Edge Blanking Over Power Compensation In the case of current sensing. To limit the maximum output power. shows as figure 10. 11 . VLimit = VFB VFB = I div 3 . Soft-Start To reduce the stress on primary MOSFET and secondary diode during start up.3V. © 2011 MPS. the bigger rising ratio).7V Current Limit Setting The switch current is sensed by the resistor series between the Source of the FET and the ground. VBURH:0. Figure 8 shows the typical FB and Drive waveform during the burst mode. The HFC0100 shuts down switching cycle when the inner temperature exceeds 150DegC. All Rights Reserved. slowly after it starts up. together with the MOSFET current. so Tdelay can be seen fixed. HFC0100 Rev. As the load decreases. Unauthorized Photocopy and Duplication Prohibited. inductors. Patent Protected. the turn off of the FET is delayed due to the propagation delay of the control circuit. This causes the FB voltage to rise again. △I2 is bigger than △I1 due to the bigger rising ratio(the higher input voltage. Once the FB voltage exceeds the threshold VBURH— 0. And the output voltage starts to drop at a rate dependent on the load. the power supply resumes operation.HFC0100—QUASI RESONANT CONTROLLER Burst Operation To minimize the power dissipation in no load or light load.

com 9/23/2011 MPS Proprietary Information.01 www. the bigger offset voltage. Unauthorized Photocopy and Duplication Prohibited. adding one offset voltage at CS pin (the higher input voltage. Patent Protected. ILim it IL im it2 IL im it1 IL im it △I1△I2 t Td elay Td elay T d elayTd elay Figure 10—Propagation delay of the current limit V_bulk T1 HFC0100 Current Comparator 6 Rfeedforward Q1 R1 CS V ref C1 Rsense Figure 11—Over Power Compensation Figure 12 shows the HFC0100 control flow chart. Figure 13 shows the HFC0100 evolution of the signals in presence of faults HFC0100 Rev. 1. All Rights Reserved.HFC0100—QUASI RESONANT CONTROLLER The propagation delay is done by means of the feedforward resistor. 12 .MonolithicPower.). © 2011 MPS. shown as Figure 11. Through this method.

7V VFB>3. Unauthorized Photocopy and Duplication Prohibited. OVP is latch Release from the latch condition . Patent Protected.5V Vcc<3V? N Y OTP= Logic High? Shut Down Internal High Voltage Current Source Y Vcc>11.7V N Toff<7.7V Vcc<8. © 2011 MPS.5V<VFB<3. need to unplug from the main input .com 9/23/2011 MPS Proprietary Information.01 www. 1.5V? and OLP=Logic High Y N Continuous Fault Monitor QR mode Operation OLP=Logic High Burst Mode Operation Y VFB >0.HFC0100—QUASI RESONANT CONTROLLER Start Y Internal High Voltage Current Source ON Shut off the Switching Pulse Vcc Decrease to 5.8uS Figure 12—Control Flow Chart HFC0100 Rev. OTP & OLP are auto restart . Y Constraint Toff_min≥7. 13 . All Rights Reserved.5V 0.MonolithicPower.8V N Y Latch off the Switching Pulse N Y OVP= Logic High? N Vcc<8V Y Soft Start Monitor Vcc N Thermal Monitor Pin VSD Monitor Monitor VFB Y VFB<0.8uS N UVLO.

All Rights Reserved.5V 5.01 www. Patent Protected.8V 8.MonolithicPower.com 9/23/2011 MPS Proprietary Information.HFC0100—QUASI RESONANT CONTROLLER Vcc Start up Regulation Occurs Here Over Voltage Occurs Here Unplug from main input Normal operation Normal operation Normal operation 11. 1. © 2011 MPS.5V Driver Driver Pluses High voltage current source On Off IFault Flag Normal operation OVP Fault Occurs Here Normal operation OLP Fault Occurs Here Normal operation OTP Fault Occurs Here Normal operation Figure 13—Evolution of the Signals in Presence of Faults HFC0100 Rev. Unauthorized Photocopy and Duplication Prohibited. 14 .

069(1.004(0.com 9/23/2011 MPS Proprietary Information.0075(0.004" INCHES MAX. MPS will not assume any legal responsibility for any said applications. All Rights Reserved.00) 0.27) BSC 0.50) GAUGE PLANE 0.27) PIN 1 ID 0.050(1. 0o-8o 0.157(4.75) SEATING PLANE 0. 4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.150(3. 2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH.60) 0.197(5.51) 0. 6) DRAWING IS NOT TO SCALE. VARIATION AA.189(4. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application.61) 0.MonolithicPower.010(0.80) 0.00) 8 5 0.80) 0.050(1.010(0.35) 0.40) 1 4 TOP VIEW RECOMMENDED LAND PATTERN 0. 3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.25) BSC NOTE: 1) CONTROL DIMENSION IS IN INCHES.10) 0.25) x 45o 0.024(0.244(6.0098(0. 15 .25) 0. PROTRUSIONS OR GATE BURRS.063(1.33) 0.010(0.013(0. Patent Protected. © 2011 MPS. Unauthorized Photocopy and Duplication Prohibited.050(1.20) 0.25) SEE DETAIL "A" FRONT VIEW SIDE VIEW 0.HFC0100—QUASI RESONANT CONTROLLER PACKAGE INFORMATION SOIC8 0. 1.80) 0.228(5.016(0. HFC0100 Rev.41) 0.19) 0.01 www.020(0.213(5.020(0. DIMENSION IN BRACKET IS IN MILLIMETERS.27) DETAIL "A" NOTICE: The information in this document is subject to change without notice. 5) DRAWING CONFORMS TO JEDEC MS-012.053(1.