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ICL8038 TM Data Sheet April 2001 File Number 2864.4 OBSOLETE PRODUCT NO RECOMMENDED REPLACEMENT contact
ICL8038
TM
Data Sheet
April 2001
File Number
2864.4
OBSOLETE PRODUCT
NO RECOMMENDED REPLACEMENT
contact our Technical Support
Center at
Precision Waveform Generator/Voltage
Controlled Oscillator
Features
or www.intersil.com/tsc
1-888-INTERSIL
• Low Frequency Drift with Temperature
250ppm/ o C

The ICL8038 waveform generator is a monolithic integrated circuit capable of producing high accuracy sine, square, triangular, sawtooth and pulse waveforms with a minimum of external components. The frequency (or repetition rate) can be selected externally from 0.001Hz to more than 300kHz using either resistors or capacitors, and frequency modulation and sweeping can be accomplished with an external voltage. The ICL8038 is fabricated with advanced monolithic technology, using Schottky barrier diodes and thin film resistors, and the output is stable over a wide range of temperature and supply variations. These devices may be interfaced with phase locked loop circuitry to reduce temperature drift to less than 250ppm/ o C.

[ /Title

• Low Distortion

1% (Sine Wave Output)

• High Linearity

.0.1% (Triangle Wave Output)

• Wide Frequency Range

.0.001Hz to 300kHz

• Variable Duty Cycle

2% to 98%

• High Level

TTL to 28V

• Simultaneous Sine, Square, and Triangle Wave Outputs

• Easy to Use - Just a Handful of External Components Required

(ICL80

38)

/Sub-

ject

(Preci-

sion

Wave-

form

Gener-

ator/Vo

ltage

Con- Ordering Information

trolled

Oscil-

lator)

/Autho

r ()

/Key-

words

(Inter- Pinout

sil

Corpo-

ration,

semi-

con-

ductor,

wave-

form

genera-

tor,

volt-

age

con-

trolled

oscilla-

tor,

preci-

sion,

PART NUMBER

STABILITY

TEMP. RANGE ( o C)

 

PACKAGE

PKG. NO.

ICL8038CCPD

250ppm/ o C (Typ)

0

to 70

14

Ld PDIP

E14.3

ICL8038CCJD

250ppm/ o C (Typ)

0

to 70

14

Ld CERDIP

F14.3

ICL8038BCJD

180ppm/ o C (Typ)

0

to 70

14

Ld CERDIP

F14.3

ICL8038ACJD

120ppm/ o C (Typ)

0

to 70

14

Ld CERDIP

F14.3

ICL8038

(PDIP, CERDIP)

TOP VIEW

 
   
 

SINE WAVE

1

14

ADJUST

   

SINE

2

 

13

WAVE OUT

TRIANGLE

3

12

OUT

 
   
 

DUTY CYCLE

 

4

11

FREQUENCY

FREQUENCY    
   

ADJUST

5

10

V+

6

9

FM BIAS

7

8

NC

NC

SINE WAVE

ADJUST

V- OR GND

TIMING

CAPACITOR

SQUARE

WAVE OUT

FM SWEEP

INPUT

Functional Diagram

V+ 6 CURRENT SOURCE #1 COMPARATOR #1 I 10 2I COMPARATOR C #2 CURRENT FLIP-FLOP
V+
6
CURRENT
SOURCE
#1
COMPARATOR
#1
I
10
2I
COMPARATOR
C
#2
CURRENT
FLIP-FLOP
SOURCE
#2
V- OR GND
11
SINE
BUFFER
BUFFER
CONVERTER
9
3
2

1

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2001, All Rights Reserved

ICL8038

Absolute Maximum Ratings

Supply Voltage (V- to V+) Input Voltage (Any Pin)

. Input Current (Pins 4 and

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

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.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

. V- to V+

25mA

36V

.

.

Output Sink Current (Pins 3 and 9)

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

25mA

Operating Conditions

Temperature Range ICL8038AC, ICL8038BC, ICL8038CC

0 o C to 70 o C

Thermal Information

Thermal Resistance (Typical, Note 1) CERDIP PDIP Package

. Maximum Junction Temperature (Ceramic Package) Maximum Junction Temperature (Plastic Package) Maximum Storage Temperature Range Maximum Lead Temperature (Soldering 10s)

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

θ JA ( o C/W)

75

115

θ JC ( o C/W)

20

N/A

C

C

-65 o C to 150 o C

o C

.175

.150

o

300

o

Die Characteristics

Back Side Potential

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

V-

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θ JA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

V SUPPLY = ±10V or +20V, T A = 25 o C, R L = 10kΩ, Test Circuit Unless Otherwise Specified

   

TEST

ICL8038CC

ICL8038BC

ICL8038AC

 
 

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX

MIN

TYP

MAX

 

UNITS

Supply Voltage Operating Range

V SUPPLY

                     
 

V+

Single Supply

+10

-

+30

+10

-

+30

+10

-

+30

 

V

V+, V-

Dual Supplies

±5

-

±15

±5

-

±15

±5

-

±15

 

V

Supply Current

I SUPPLY

V SUPPLY = ±10V (Note 2)

 

12

20

-

12

20

-

12

20

 

mA

FREQUENCY CHARACTERISTICS (All Waveforms)

 

Max. Frequency of Oscillation

 

f

MAX

 

100

-

-

100

-

-

100

-

-

 

kHz

Sweep Frequency of FM Input

f

SWEEP

 

-

10

-

-

10

-

-

10

-

 

kHz

Sweep FM Range

 

(Note 3)

-

35:1

-

-

35:1

-

-

35:1

-

 

FM Linearity

 

10:1 Ratio

-

0.5

-

-

0.2

-

-

0.2

-

 

%

Frequency Drift with Temperature (Note 5)

 

Δf/ΔT

0 o C to 70 o C

-

250

-

-

180

-

-

120

   

ppm/ o C

Frequency Drift with Supply Voltage

 

Δf/ΔV

Over Supply

-

0.05

-

-

0.05

 

-

0.05

-

 

%/V

 

Voltage Range

 

OUTPUT CHARACTERISTICS

 

Square Wave

                       
 

Leakage Current

 

I

OLK

V 9 = 30V

-

-

1

-

-

1

-

-

1

 

μA

Saturation Voltage

 

V

SAT

I SINK = 2mA

-

0.2

0.5

-

0.2

0.4

-

0.2

0.4

 

V

Rise Time

 

t

R

R L = 4.7kΩ

-

180

-

-

180

-

-

180

-

 

ns

Fall Time

 

t

F

R L = 4.7kΩ

-

40

-

-

40

-

-

40

-

 

ns

Typical Duty Cycle Adjust (Note 6)

 

ΔD

 

2

 

98

2

-

98

2

-

98

 

%

Triangle/Sawtooth/Ramp

                     

-

 

Amplitude

V

TRIAN-

R TRI = 100kΩ

0.30

0.33

-

0.30

0.33

-

0.30

0.33

-

 

xV

SUPPLY

   

GLE

 
 

Linearity

   

-

0.1

-

 

- 0.05

-

 

- 0.05

-

 

%

Output Impedance

 

Z

OUT

I OUT = 5mA

-

200

-

 

- 200

-

 

- 200

-

 

Ω

2

2

ICL8038

Electrical Specifications

V SUPPLY = ±10V or +20V, T A = 25 o C, R L = 10kΩ, Test Circuit Unless Otherwise Specified (Continued)

     

TEST

ICL8038CC

 

ICL8038BC

ICL8038AC

 
 

PARAMETER

SYMBOL

CONDITIONS

 

MIN

TYP

MAX

 

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

Sine Wave

                       
 

Amplitude

V

SINE

R SINE = 100kΩ

 

0.2

0.22

-

 

0.2

0.22

-

0.2

0.22

-

xV

SUPPLY

THD

THD

R S = 1MΩ (Note 4)

 

-

2.0

5

 

-

1.5

3

-

1.0

1.5

 

%

THD Adjusted

THD

Use Figure 4

 

-

1.5

-

 

-

1.0

-

-

0.8

-

 

%

NOTES:

 

2. R A and R B currents not included.

3. V SUPPLY = 20V; R A and R B = 10kΩ, f 10kHz nominal; can be extended 1000 to 1. See Figures 5A and 5B.

 

4. 82kΩ connected between pins 11 and 12, Triangle Duty Cycle set at 50%. (Use R A and R B .)

 

5. Figure 1, pins 7 and 8 connected, V SUPPLY = ±10V. See Typical Curves for T.C. vs V SUPPLY .

 

6. Not tested, typical value for design purposes only.

 

Test Conditions

 
 

PARAMETER

R

A

 

R

B

 

R

L

 

C

SW 1

 

MEASURE

Supply Current

 

10kΩ

 

10kΩ

 

10kΩ

3.3nF

Closed

Current Into Pin 6

 

Sweep FM Range (Note 7)

 

10kΩ

 

10kΩ

 

10kΩ

3.3nF

Open

Frequency at Pin 9

Frequency Drift with Temperature

 

10kΩ

 

10kΩ

 

10kΩ

3.3nF

Closed

Frequency at Pin 3

Frequency Drift with Supply Voltage (Note 8)

 

10kΩ

 

10kΩ

 

10kΩ

3.3nF

Closed

Frequency at Pin 9

Output Amplitude (Note 10)

             
 

Sine

10kΩ

 

10kΩ

 

10kΩ

3.3nF

Closed

Pk-Pk Output at Pin 2

Triangle

10kΩ

 

10kΩ

 

10kΩ

3.3nF

Closed

Pk-Pk Output at Pin 3

Leakage Current (Off) (Note 9)

 

10kΩ

 

10kΩ

 

3.3nF

Closed

Current into Pin 9

 

Saturation Voltage (On) (Note 9)

 

10kΩ

 

10kΩ

 

3.3nF

Closed

Output (Low) at Pin 9

Rise and Fall Times (Note 11)

 

10kΩ

 

10kΩ

4.7kΩ

 

3.3nF

Closed

Waveform at Pin 9

Duty Cycle Adjust (Note 11)

             
 

Max

50kΩ

 

~1.6kΩ

 

10kΩ

3.3nF

Closed

Waveform at Pin 9

Min

~25kΩ

 

50kΩ

 

10kΩ

3.3nF

Closed

Waveform at Pin 9

Triangle Waveform Linearity

 

10kΩ

 

10kΩ

 

10kΩ

3.3nF

Closed

Waveform at Pin 3

Total Harmonic Distortion

 

10kΩ

 

10kΩ

 

10kΩ

3.3nF

Closed

Waveform at Pin 2

NOTES:

 

7.

The hi and lo frequencies can be obtained by connecting pin 8 to pin 7 (f

HI

) and then connecting pin 8 to pin 6 (f

LO

). Otherwise apply Sweep

Voltage at pin 8 ( 2 / 3 V SUPPLY +2V) V SWEEP V SUPPLY where V SUPPLY is the total supply voltage. In Figure 5B, pin 8 should vary between

8.

9.

10.

11.

5.3V and 10V with respect to ground.

10V V+ 30V, or ±5V V SUPPLY ≤ ±15V.

Oscillation can be halted by forcing pin 10 to +5V or -5V.

Output Amplitude is tested under static conditions by forcing pin 10 to 5V then to -5V.

Not tested; for design purposes only.

3

3

ICL8038

Test Circuit

Detailed Schematic

   
             
   
             
   
             
 
             
R A R B R L

R

A

R

B

R

L

10K

10K

10K

 

7 456

 
  7 456  
  7 456  
 

9

SW 1

 

N.C.

   
   
 

8 ICL8038

 

3

  8 ICL8038   3  
 
 

R

TRI

 

10

 

11

 

12

2

 
  10   11   12 2  
 
 
   

C

     
    C         R SINE
 

R

SINE

 

3300pF

  3300pF 82K

82K

  3300pF 82K
      R SINE   3300pF 82K FIGURE 1. TEST CIRCUIT +10V -10V CURRENT SOURCES

FIGURE 1. TEST CIRCUIT

+10V

SINE   3300pF 82K FIGURE 1. TEST CIRCUIT +10V -10V CURRENT SOURCES 6 V+ R 41

-10V

CURRENT SOURCES 6 V+ R 41 R R EXT BR EXT A 32 R 4K
CURRENT SOURCES
6
V+
R 41
R
R EXT BR EXT A
32
R
4K
1
8
Q
5.2K
1
5
Q
11K
4
14
Q
Q
48
1
2
7
R
8
Q
R
3
Q
33
5K
47
R
2
R
Q
19
200
6
39K
Q
Q
4
Q 5
46
800
COMPARATOR
Q
R
45
34
R
Q
20
375
7
Q
8
Q 9
Q
10
44
Q
Q
18
2.7K
R
15
R
46
Q
35
43
R
Q
21
40K
Q
17
330
16
C EXT
R
Q
9
42
5K
10K
R
R
7B
7A
Q
Q 10
41
R
R
R
R
R
27
45
3
25
26
10K
Q
15K
11
30K
33K
33K
33K
33K
R
Q 12
36
Q
30
Q 20 Q 21
1600
Q 13
Q
Q
31
Q
22
19
R
R 4
5
R 6
R
R
R
R
28
29
30
31
Q
100
100
100
32
R 10
33K
33K
33K
33K
5K
Q
49
Q
33
R
22
Q
50
Q
34
10K
R
R 13
37
R 16
R 43
Q
51
620
330
1.8K
27K
R
23
Q
24
Q
52
R
2.7K
R
9
14
Q
Q
38
Q
37
Q
53
35
39
27K
R
375
24
R
11
Q
54
Q
270
Q 36 Q 38
40
R
3
800
39
Q
Q
R 41
R 44
Q
26
55
23
Q 27 Q 28
200
27K
1K
12
R
R
12
Q
15
R 17
56
2.7K
470
4.7K
R 40
R
42
R EXT C
BUFFER AMPLIFIER
2
5.6K
Q
Q
25
29
27K
82K
11
R 18
4.7K
SINE CONVERTER
FLIP-FLOP

Application Information (See Functional Diagram)

An external capacitor C is charged and discharged by two current sources. Current source #2 is switched on and off by a flip-flop, while current source #1 is on continuously. Assuming that the flip-flop is in a state such that current source #2 is off, and the capacitor is charged with a current I, the voltage across the capacitor rises linearly with time. When this voltage reaches the level of comparator #1 (set at 2/3 of the supply voltage), the flip-flop is triggered, changes states, and releases current source #2. This current source normally carries a current 2I, thus the capacitor is discharged with a

net-current I and the voltage across it drops linearly with time. When it has reached the level of comparator #2 (set at 1/3 of the supply voltage), the flip-flop is triggered into its original state and the cycle starts again.

Four waveforms are readily obtainable from this basic generator circuit. With the current sources set at I and 2I respectively, the charge and discharge times are equal. Thus a triangle waveform is created across the capacitor and the flip-flop produces a square wave. Both waveforms are fed to buffer stages and are available at pins 3 and 9.

4

4

ICL8038

The levels of the current sources can, however, be selected over a wide range with two external resistors. Therefore, with the two currents set at values different from I and 2I, an asymmetrical sawtooth appears at Terminal 3 and pulses with a duty cycle from less than 1% to greater than 99% are available at Terminal 9.

The sine wave is created by feeding the triangle wave into a nonlinear network (sine converter). This network provides a decreasing shunt impedance as the potential of the triangle moves toward the two extremes.

Waveform Timing

The symmetry of all waveforms can be adjusted with the external timing resistors. Two possible ways to accomplish this are shown in Figure 3. Best results are obtained by keeping the timing resistors R A and R B separate (A). R A controls the rising portion of the triangle and sine wave and the 1 state of the square wave.

The magnitude of the triangle waveform is set at 1 / 3 V SUPPLY ; therefore the rising portion of the triangle is,

L Y ; therefore the rising portion of the triangle is, FIGURE 2A. SQUARE WAVE DUTY

FIGURE 2A. SQUARE WAVE DUTY CYCLE - 50%

t 1

== C × V

I

--------------

C

-------------------------------------------------------------------

R A

×

1/3

×

V

SUPPLY

×

0.22 ×

V SUPPLY

R A × C = ------------------

0.66

The falling portion of the triangle and sine wave and the 0 state of the square wave is:

t

2

C × V

-------------

==

1

C

×

1/3V SUPPLY

R A R B C

----------------------------------------------------------------------------------- = -------------------------------------

)

V

SUPPLY

------------------------

R

B

V

SUPPLY

------------------------

R

A

(

0.66 2R

A

R

B

2 ( 0.22 )

0.22

Thus a 50% duty cycle is achieved when R A = R B .

If the duty cycle is to be varied over a small range about 50% only, the connection shown in Figure 3B is slightly more convenient. A 1kΩ potentiometer may not allow the duty cycle to be adjusted through 50% on all devices. If a 50% duty cycle is required, a 2kΩ or 5kΩ potentiometer should be used.

With two separate timing resistors, the frequency is given by:

1 1 f = ---------------- = ------------------------------------------------------ + t 2 t 1 R C ⎛
1
1
f
=
----------------
= ------------------------------------------------------
+ t 2
t 1
R
C ⎛
R
A
B ⎞
------------ ⎜ 1
+ -------------------------
0.66
2R
A – R
B ⎠
or, if R A = R B = R
0.33
f
= ----------- (for Figure 3A)
RC

FIGURE 2B. SQUARE WAVE DUTY CYCLE - 80%

FIGURE 2. PHASE RELATIONSHIP OF WAVEFORMS

V+ R R R L A B 7 456 9 8 ICL8038 3 2 10
V+
R
R
R
L
A
B
7 456
9
8 ICL8038
3
2
10
11
12
C
82K
V- OR GND

FIGURE 3A.

V+ 1kΩ R L R R A B 456 7 9 8 ICL8038 3 10
V+
1kΩ
R
L
R
R
A
B
456
7
9
8
ICL8038
3
10
11
12
2
C
100K
V- OR GND

FIGURE 3B.

FIGURE 3. POSSIBLE CONNECTIONS FOR THE EXTERNAL TIMING RESISTORS

5

5

ICL8038

Neither time nor frequency are dependent on supply voltage, even though none of the voltages are regulated inside the integrated circuit. This is due to the fact that both currents and thresholds are direct, linear functions of the supply voltage and thus their effects cancel.

Reducing Distortion

To minimize sine wave distortion the 82kΩ resistor between pins 11 and 12 is best made variable. With this arrangement distortion of less than 1% is achievable. To reduce this even further, two potentiometers can be connected as shown in Figure 4; this configuration allows a typical reduction of sine wave distortion close to 0.5%.

   
         
 
         
 
         
 
         
       

V+

R

A

1kΩ
1kΩ
R A 1kΩ R B R L  

R

B

R A 1kΩ R B R L  

R

L

 
 

456

  456
  456

7

   

9

 
7     9  
7     9  

8

 

ICL8038

3

 
8   ICL8038 3  

10

11

12

1

2

 
10 11 12 1 2   100kΩ  
100kΩ
100kΩ
10 11 12 1 2   100kΩ  
10 11 12 1 2   100kΩ  
 
           

10kΩ

C

 

10kΩ

100kΩ

 
 
 
   
 

V- OR GND

FIGURE 4. CONNECTION TO ACHIEVE MINIMUM SINE WAVE DISTORTION

Selecting R A , R B and C

For any given output frequency, there is a wide range of RC combinations that will work, however certain constraints are placed upon the magnitude of the charging current for optimum performance. At the low end, currents of less than 1μA are undesirable because circuit leakages will contribute significant errors at high temperatures. At higher currents (I > 5mA), transistor betas and saturation voltages will contribute increasingly larger errors. Optimum performance will, therefore, be obtained with charging currents of 10μA to 1mA. If pins 7 and 8 are shorted together, the magnitude of the charging current due to R A can be calculated from:

I

=

R 1 × (V+

---------------------------------------- × --------

(

R

1

V-)

+

R

2

)

1

R

A

= 0.22(V+ ------------------------------------ – V-)

R A

R 1 and R 2 are shown in the Detailed Schematic.

A similar calculation holds for R B .

The capacitor value should be chosen at the upper end of its possible range.

Waveform Out Level Control and Power Supplies

The waveform generator can be operated either from a single power supply (10V to 30V) or a dual power supply (±5V to ±15V). With a single power supply the average levels of the triangle and sine wave are at exactly one-half of the supply voltage, while the square wave alternates between V+ and ground. A split power supply has the advantage that all waveforms move symmetrically about ground.

The square wave output is not committed. A load resistor can be connected to a different power supply, as long as the applied voltage remains within the breakdown capability of the waveform generator (30V). In this way, the square wave

output can be made TTL compatible (load resistor connected to +5V) while the waveform generator itself is

powered from a much higher voltage.

Frequency Modulation and Sweeping

The frequency of the waveform generator is a direct function of the DC voltage at Terminal 8 (measured from V+). By

altering this voltage, frequency modulation is performed. For small deviations (e.g. ±10%) the modulating signal can be

applied directly to pin 8, merely providing DC decoupling with a capacitor as shown in Figure 5A. An external resistor between pins 7 and 8 is not necessary, but it can be used to increase input impedance from about 8kΩ (pins 7 and 8 connected together), to about (R + 8kΩ).

For larger FM deviations or for frequency sweeping, the modulating signal is applied between the positive supply

voltage and pin 8 (Figure 5B). In this way the entire bias for the current sources is created by the modulating signal, and

a very large (e.g. 1000:1) sweep range is created

(f = Minimum at V SWEEP = 0, i.e., Pin 8 = V+). Care must be taken, however, to regulate the supply voltage; in this configuration the charge current is no longer a function of the supply voltage (yet the trigger thresholds still are) and thus the frequency becomes dependent on the supply voltage. The potential on Pin 8 may be swept down from V+ by ( 1 / 3

V SUPPLY - 2V).

V+ R R R L A B 7 456 9 R 8 ICL8038 3 FM
V+
R
R
R
L
A
B
7 456
9
R
8 ICL8038
3
FM
2
10
11
12
C
81K
V- OR GND

FIGURE 5A. CONNECTIONS FOR FREQUENCY MODULATION

6

6

ICL8038

V+ V+ R R 15K SWEEP R R R A B L A B VOLTAGE
V+
V+
R
R
15K
SWEEP
R
R
R
A
B
L
A
B
VOLTAGE
5
7 4
9
456
9
8 ICL8038
8
ICL8038
3
1N914
2
2
11
10
10
11
12
1N914
C
81K
C
2N4392
STROBE
100K
V- OR GND
-15V
OFF
+15V (+10V)
FIGURE 5B. CONNECTIONS FOR FREQUENCY SWEEP
FIGURE 5.
-15V (-10V)
ON

FIGURE 7. STROBE TONE BURST GENERATOR

Typical Applications

The sine wave output has a relatively high output impedance (1kΩ Typ). The circuit of Figure 6 provides buffering, gain and amplitude adjustment. A simple op amp follower could also be used.

R A R B AMPLITUDE 7 456 2 + 100K 741 8 ICL8038 - 10
R A
R B
AMPLITUDE
7 456
2
+
100K
741
8 ICL8038
-
10
11
4.7K
C

V+7 456 2 + 100K 741 8 ICL8038 - 10 11 4.7K C To obtain a

To obtain a 1000:1 Sweep Range on the ICL8038 the voltage across external resistors R A and R B must decrease to nearly zero. This requires that the highest voltage on control Pin 8 exceed the voltage at the top of R A and R B by a few hundred mV. The Circuit of Figure 8 achieves this by

using a diode to lower the effective supply voltage on the ICL8038. The large resistor on pin 5 helps reduce duty cycle variations with sweep.

The linearity of input sweep voltage versus output frequency can be significantly improved by using an op amp as shown

in Figure 10.can be significantly improved by using an op amp as shown 20K +10V 1N457 DUTY CYCLE

20K

+10V 1N457 DUTY CYCLE 15K 0.1μF 1K 4.7K 4.7K 546 9 10K 8 ICL8038 3
+10V
1N457
DUTY CYCLE
15K
0.1μF
1K
4.7K
4.7K
546
9
10K
8
ICL8038
3
FREQ.
2
10
11
12
DISTORTION
20K
≈15M
0.0047μF
100K
-10V
FIGURE 8. VARIABLE AUDIO OSCILLATOR, 20Hz TO 20kHzY

V--10V FIGURE 8. VARIABLE AUDIO OSCILLATOR, 20Hz TO 20kHzY FIGURE 6. SINE WAVE OUTPUT BUFFER AMPLIFIERS

FIGURE 6. SINE WAVE OUTPUT BUFFER AMPLIFIERS

With a dual supply voltage the external capacitor on Pin 10 can be shorted to ground to halt the ICL8038 oscillation. Figure 7 shows a FET switch, diode ANDed with an input strobe signal to allow the output to always start on the same slope.

7

7

ICL8038

V 1 +

INPUT

DUTY CYCLE R 1 FREQUENCY ADJUST FM BIAS 4 5 6 7 3 SQUARE WAVE
DUTY
CYCLE
R
1
FREQUENCY
ADJUST
FM BIAS
4
5
6
7
3
SQUARE
WAVE
OUT
9
ICL8038
2
VCO
DEMODULATED
IN
AMPLIFIER
FM
PHASE
1
8
10
11
12
DETECTOR
R
2
TIMING
CAP.
ADJ.
LOW PASS
FILTER

V 2 +

TRIANGLE

OUT

TIMING CAP. ADJ. LOW PASS FILTER V 2 + TRIANGLE OUT SINE WAVE OUT SINE WAVE

SINE WAVE

OUT

ADJ. LOW PASS FILTER V 2 + TRIANGLE OUT SINE WAVE OUT SINE WAVE ADJ. SINE

SINE WAVE

ADJ.

SINE WAVE

V-/GND

FIGURE 9. WAVEFORM GENERATOR USED AS STABLE VCO IN A PHASE-LOCKED LOOP HIGH FREQUENCY SYMMETRY
FIGURE 9. WAVEFORM GENERATOR USED AS STABLE VCO IN A PHASE-LOCKED LOOP
HIGH FREQUENCY
SYMMETRY
10kΩ
100kΩ
500Ω
1N753A
4.7kΩ
4.7kΩ
(6.2V)
1MΩ
1kΩ
100kΩ
1,000pF
LOW FREQUENCY
456
9
SYMMETRY
+15V
-
SINE WAVE
1kΩ
ICL8038
+15V
OUTPUT
741
3
8 FUNCTION GENERATOR
+
-
741
-V IN
P 4
+
+
2
10
11
12
10kΩ
50μF
OFFSET
15V
100kΩ
3,900pF
SINE WAVE
DISTORTION
-15V

FIGURE 10. LINEAR VOLTAGE CONTROLLED OSCILLATOR

Use in Phase Locked Loops

Its high frequency stability makes the ICL8038 an ideal building block for a phase locked loop as shown in Figure 9. In this application the remaining functional blocks, the phase detector and the amplifier, can be formed by a number of available ICs (e.g., MC4344, NE562).

In order to match these building blocks to each other, two steps must be taken. First, two different supply voltages are used and the square wave output is returned to the supply of the phase detector. This assures that the VCO input voltage will not exceed the capabilities of the phase detector. If a smaller VCO signal is required, a simple resistive voltage divider is connected between pin 9 of the waveform generator and the VCO input of the phase detector.

Second, the DC output level of the amplifier must be made compatible to the DC level required at the FM input of the waveform generator (pin 8, 0.8V+). The simplest solution here is to provide a voltage divider to V+ (R 1 , R 2 as shown) if the amplifier has a lower output level, or to ground if its level is higher. The divider can be made part of the low-pass filter.

This application not only provides for a free-running frequency with very low temperature drift, but is also has the unique feature of producing a large reconstituted sinewave signal with a frequency identical to that at the input.

For further information, see Intersil Application Note AN013, “Everything You Always Wanted to Know About the ICL8038”.

8

8

ICL8038

Definition of Terms

Supply Voltage (V SUPPLY ). The total supply voltage from V+ to V-.

Supply Current. The supply current required from the power supply to operate the device, excluding load currents and the currents through R A and R B .

Frequency Range. The frequency range at the square wave output through which circuit operation is guaranteed.

Sweep FM Range. The ratio of maximum frequency to minimum frequency which can be obtained by applying a sweep voltage to pin 8. For correct operation, the sweep voltage should be within the range:

( 2 / 3 V SUPPLY + 2V) < V SWEEP < V SUPPLY

Typical Performance Curves

20 -55 o C 15 125 o C o 10 25 C 5 5 10
20
-55 o C
15
125
o C
o
10
25
C
5
5
10
15
20
25
30
SUPPLY CURRENT (mA)

SUPPLY VOLTAGE (V)

FIGURE 11. SUPPLY CURRENT vs SUPPLY VOLTAGE

1.03 1.02 10V 1.01 20V 30V 1.00 20V 10V 30V 0.99 0.98 -50 -25 0
1.03
1.02
10V
1.01
20V
30V
1.00
20V
10V
30V
0.99
0.98
-50
-25
0
25
75
125
NORMALIZED FREQUENCY

TEMPERATURE ( o C)

FIGURE 13. FREQUENCY vs TEMPERATURE

FM Linearity. The percentage deviation from the best fit straight line on the control voltage versus output frequency curve.

Output Amplitude. The peak-to-peak signal amplitude appearing at the outputs.

Saturation Voltage. The output voltage at the collector of Q 23 when this transistor is turned on. It is measured for a sink current of 2mA.

Rise and Fall Times. The time required for the square wave output to change from 10% to 90%, or 90% to 10%, of its final value.

Triangle Waveform Linearity. The percentage deviation from the best fit straight line on the rising and falling triangle waveform.

Total Harmonic Distortion. The total harmonic distortion at the sine wave output.

1.03 1.02 1.01 1.00 0.99 0.98 5 10 15 20 25 30 NORMALIZED FREQUENCY
1.03
1.02
1.01
1.00
0.99
0.98
5
10
15
20
25
30
NORMALIZED FREQUENCY

SUPPLY VOLTAGE (V)

FIGURE 12. FREQUENCY vs SUPPLY VOLTAGE

200 RISE TIME 150 o 125 C 25 o C -55 o C 100 125
200
RISE TIME
150
o
125
C
25
o C
-55 o C
100
125
o C
25
o C
FALL TIME
-55 o
C
50
0
0
2
4
6
8
10
TIME (ns)

LOAD RESISTANCE (kΩ)

FIGURE 14. SQUARE WAVE OUTPUT RISE/FALL TIME vs LOAD RESISTANCE

9

9

ICL8038

Typical Performance Curves (Continued)

2 1.5 125 o C 1.0 25 o C -55 o C 0.5 0 0
2
1.5
125
o C
1.0
25
o C
-55 o C
0.5
0
0
2
4
6
8
10
SATURATION VOLTAGE

LOAD CURRENT (mA)

FIGURE 15. SQUARE WAVE SATURATION VOLTAGE vs LOAD CURRENT

1.2 1.1 1.0 0.9 0.8 0.7 0.6 10 100 1K 10K 100K 1M NORMALIZED OUTPUT
1.2
1.1
1.0
0.9
0.8
0.7
0.6
10 100
1K
10K
100K
1M
NORMALIZED OUTPUT VOLTAGE

FREQUENCY (Hz)

FIGURE 17. TRIANGLE WAVE OUTPUT VOLTAGE vs FREQUENCY

1.1 1.0 0.9 10 100 1K 10K 100K 1M NORMALIZED OUTPUT VOLTAGE
1.1
1.0
0.9
10 100
1K
10K
100K
1M
NORMALIZED OUTPUT VOLTAGE

FREQUENCY (Hz)

FIGURE 19. SINE WAVE OUTPUT VOLTAGE vs FREQUENCY

1.0 LOAD CURRENT 125 o C TO V - 25 o C 0.9 -55 o
1.0
LOAD CURRENT
125
o C
TO V -
25
o C
0.9
-55 o C
0.8
LOAD CURRENT TO V+
0
2
4
6
8
10
12
14
16
18
20
NORMALIZED PEAK OUTPUT VOLTAGE

LOAD CURRENT (mA)

FIGURE 16. TRIANGLE WAVE OUTPUT VOLTAGE vs LOAD CURRENT

10.0 1.0 0.1 0.01 10 100 1K 10K 100K 1M LINEARITY (%)
10.0
1.0
0.1
0.01
10
100
1K
10K
100K
1M
LINEARITY (%)

FREQUENCY (Hz)

FIGURE 18. TRIANGLE WAVE LINEARITY vs FREQUENCY

12 10 8 6 4 ADJUSTED UNADJUSTED 2 0 10 100 1K 10K 100K 1M
12
10
8
6
4
ADJUSTED
UNADJUSTED
2
0
10
100
1K
10K
100K
1M
DISTORTION (%)

FREQUENCY (Hz)

FIGURE 20. SINE WAVE DISTORTION vs FREQUENCY

10

10

ICL8038

Dual-In-Line Plastic Packages (PDIP)

N E1 INDEX 1 2 3 N/2 AREA -B- -A- D E BASE PLANE A2
N
E1
INDEX
1
2
3
N/2
AREA
-B-
-A-
D
E
BASE
PLANE
A2
A
-C-
SEATING
PLANE
L
C L
D1
A1 A
e
D1
e
B1
e
C
C
B
e
B
0.010 (0.25)
M
C
A B
S

NOTES:

1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95.

4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3.

5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).

are measured with the leads constrained to be perpen-

6. E and

e A
e
A

dicular to datum

-C- .
-C-
.

7. e B and e C are measured at the lead tips with the leads uncon- strained. e C must be zero or greater.

8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm).

9. N is the maximum number of terminal positions.

10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,

E42.6 will have

a B1 dimension

of 0.030

-

0.045

inch (0.76 -

1.14mm).

E14.3 (JEDEC MS-001-AA ISSUE D) 14 LEAD DUAL-IN-LINE PLASTIC PACKAGE

 

INCHES

MILLIMETERS

 

SYMBOL

MIN

MAX

MIN

MAX

NOTES

 

A

-

0.210

-

5.33

4

A1

0.015

-

0.39

-

4

A2

0.115

0.195

2.93

4.95

-

 

B

0.014

0.022

0.356

0.558

-

B1

0.045

0.070

1.15

1.77

8

 

C

0.008

0.014

0.204

0.355

-

 

D

0.735

0.775

18.66

19.68

5

D1

0.005

-

0.13

-

5

 

E

0.300

0.325

7.62

8.25

6

E1

0.240

0.280

6.10

7.11

5

 

e

0.100

BSC

2.54

BSC

-

e

A

0.300

BSC

7.62

BSC

6

e

B

-

0.430

-

10.92

7

 

L

0.115

0.150

2.93

3.81

4

 

N

 

14

 

14

9

Rev. 0 12/93

11

11

ICL8038

Ceramic Dual-In-Line Frit Seal Packages (CERDIP)

-A- -D- E -B- bbb S C A - B S D S
-A-
-D-
E
-B-
bbb
S
C
A - B
S
D
S
c1 LEAD FINISH BASE (c) METAL b1 M M (b)
c1
LEAD FINISH
BASE
(c)
METAL
b1
M
M
(b)

SECTION A-A

D BASE Q PLANE A -C- SEATING PLANE L α S1 eA A A b2
D
BASE
Q
PLANE
A
-C-
SEATING
PLANE
L
α
S1
eA
A
A
b2
b
e
eA/2
c
ccc
M
C
A - B
S
D
S
aaa
M
C
A - B
S
D
S

NOTES:

1.

Index area: A notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used

as

a pin one identification mark.

2.

The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied.

3.

Dimensions b1 and c1 apply to lead base metal only. Dimension

M

applies to lead plating and finish thickness.

4.

Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2.

5.

This dimension allows for off-center lid, meniscus, and glass overrun.

6.

Dimension Q shall be measured from the seating plane to the base plane.

7.

Measure dimension S1 at all four corners.

8.

N

is the maximum number of terminal positions.

9.

Dimensioning and tolerancing per ANSI Y14.5M - 1982.

10. Controlling dimension: INCH.

F14.3 MIL-STD-1835 GDIP1-T14 (D-1, CONFIGURATION A)

14 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE

   

INCHES

 

MILLIMETERS

   

SYMBOL

MIN

MAX

MIN

MAX

NOTES

A

-

0.200

-

5.08

-

b

0.014

0.026

0.36

0.66

2

b1

0.014

0.023

0.36

0.58

3

b2

0.045

0.065

1.14

1.65

-

b3

0.023

0.045

0.58

1.14

4

c

0.008

0.018

0.20

0.46

2

c1

0.008

0.015

0.20

0.38

3

D

-

0.785

-

19.94

5

E

0.220

0.310

5.59

7.87

5

e

 

0.100

BSC

 

2.54

BSC

-

eA

 

0.300

BSC

 

7.62

BSC

-

eA/2

 

0.150

BSC

 

3.81

BSC

-

L

0.125

0.200

3.18

5.08

-

Q

0.015

0.060

0.38

1.52

6

S1

0.005

-

0.13

-

7

α

90

o

105

o

90

o

105

o

-

aaa

-

0.015

-

0.38

-

bbb

-

0.030

-

0.76

-

ccc

-

0.010

-

0.25

-

M

-

0.0015

-

0.038

2, 3

N

 

14

   

14

 

8

Rev. 0 4/94

All Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at website www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. How- ever, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site www.intersil.com

Sales Office Headquarters

NORTH AMERICA Intersil Corporation 2401 Palm Bay Rd., Mail Stop 53-204 Palm Bay, FL 32905 TEL: (321) 724-7000 FAX: (321) 724-7240

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