VIPer53 - E

OFF-line primary switch
General features
Type DIP-8 PowerSO-10TM European (195 - 265Vac) 50W 65W US / Wide range (85 - 265 Vac) 30W 40W PowerSO-10 DIP-8

Features
■ ■ ■ ■ ■ ■ ■ ■ ■

Switching frequency up to 300kHz Current limitation Current mode control with adjustable limitation Soft start and shut-down control Automatic burst mode in standby condition (“Blue Angel“ compliant ) Undervoltage lockout with Hysteresis HIgh voltage star-tup current source Overtemperature protection Overload and short-circuit control

Description
The VIPer53-E combines an enhanced current mode PWM controller with a high voltage MDMesh Power Mosfet in the same package. Typical applications cover offline power supplies with a secondary power capability ranging up to 30W in wide range input voltage, or 50W in single European voltage range and DIP-8 package, with the following benefits:
■ ■ ■

Overload and short circuit controlled by feedback monitoring and delayed device reset. Efficient standby mode by enhanced pulse skipping. Primary regulation or secondary loop failure protection through high gain error amplifier.
DRAIN

Block diagram
OSC ON/OFF OSCILLAT OR

PW M LATCH OVERT EMP. DET ECT OR R1 S FF Q R2 R3 R4 R5 BLANKING TIME SELECTION 1V

UVLO COMPARATOR VDD 8.4/ 11.5V 0.5V STANDBY COMPARATOR 4V 150/400ns BLANKING PW M COMPARATOR 8V

0.5V

HCOM P

CURRENT AMPLIFIER

15V ERROR AMPLIFIER

125k

4.35V

OVERLOAD COMPARATOR OVERVOLTAGE COMPARATOR

18V

4.5V

T OVL

COMP

SOURCE

November 2006

Rev 1

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Contents

VIPer53 - E

Contents
1 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 1.2 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin connections and function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Operation pictures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Primary regulation configuration example . . . . . . . . . . . . . . . . . . . . . . 15 Secondary feedback configuration example . . . . . . . . . . . . . . . . . . . . 17 Current mode topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 High voltage Start-up current source . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Short-circuit and overload protection . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Transconductance error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Special recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Software implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

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VIPer53 - E

Electrical data

1
1.1

Electrical data
Maximum rating
Stressing the device above the rating listed in the “Absolute Maximum Ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 1.
Symbol VDS ID VDD VOSC ICOMP ITOVL VESD TJ TC TSTG

Absolute maximum rating
Parameter Continuous drain source voltage (TJ= 25 ... 125°C) (1) Continuous drain current Supply voltage OSC input voltage range COMP and TOVL input current range (1) Electrostatic discharge: Machine model (R = 0Ω; C = 200pF) Charged device model Junction operating temperature Case operating temperature Storage temperature Value -0.3 ... 620 Internally limited 0 ... 19 0 ... VDD -2 ... 2 Unit V A V V mA

200 1.5 Internally limited -40 to 150 -55 to 150

V kV °C °C °C

1. In order to improve the ruggedness of the device versus eventual drain overvoltages, a resistance of 1kΩ should be inserted in series with the TOVL pin.\

1.2

Thermal data
Table 2.
Symbol RthJC RthJA

Thermal data
Parameter Thermal Resistance Junction-case Thermal Resistance Ambient-case Max Max PowerSO-10 (1) 2 60 DIP-8 (2) 20 80 Unit ° C/W ° C/W

1. When mounted on a standard single-sided FR4 board with 50mm² of Cu (at least 35 mm thick) connected to the DRAIN pin. 2. When mounted on a standard single-sided FR4 board with 50mm² of Cu (at least 35 mm thick) connected to the device tab.

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Symbol BVDSS IDSS Power section Parameter Test conditions Min.⋅ C Eon ⋅ 300 2 ⋅ ⎛ ---------------E ton = -⎝ 2 300 ⎠ Table 4.. This parameter can be used to compute the energy dissipated at turn on Eton according to the initial drain to source voltage VDSon and the following formula: V DSon⎞ 1.E 2 Electrical characteristics TJ = 25°C. VCOMP = 0V Off state drain current Static drain-source On state resistance Fall time Rise time Drain capacitance Effective output capacitance VDS = 500V. On clamped inductive load 2.2nF Min. 105 Unit kHz FOSC2 Oscillator frequency total variation Figure 16 on page 14 VDD = VDDon . VTOVL = 0V TJ = 25°C TJ = 100°C ID = 0. VDDovp.. 620 150 Typ..9 1 1. unless otherwise specified Table 3.2A. Unit V µA Drain-source voltage ID = 1mA. VCOMP = 0V. VCOMP = 4. 100 Max. 100°C 93 100 107 kHz VOSChi VOSClo Oscillator peak voltage Oscillator valley voltage 9 4 V V 4/36 . TJ = 125°C ID = 1A.5V. TJ = 0 . VIN = 300V (1) ID = 1A. 95 Typ.2nF Figure 12 on page 12 RT = 8kΩ.Electrical characteristics VIPer53 . VIN = 300V (1) VDS = 25V 200V < VDSon < 400V (2) RDS(on) 0.7 Ω Ω ns ns pF pF tfv trv Coss CEon 100 50 170 60 1. CT = 2. Max.5 1 . VDD = 13V. Symbol FOSC1 Oscillator section Parameter Oscillator frequency initial accuracy Test conditions RT = 8kΩ. CT = 2..

5 3. Symbol VDSstart IDDch1 IDDch2 IDDchoff IDD0 IDD1 VDDoff VDDon VDDhyst VDDovp Supply section Parameter Drain voltage starting threshold Startup charging current Startup charging current Startup charging current in thermal shutdown Operating supply current not switching Operating supply current switching VDD undervoltage shutdown threshold VDD startup threshold VDD threshold hysteresis VDD Overvoltage shutdown threshold Test conditions VDD = 5V.1 18 11 mA mA 9. VDD = 16V Figure 11.THYST Fsw = 0kHz.. Figure 5. IDD = 0mA VDD = 0 . VCOMP = 0V Fsw = 100kHz Figure 5 on page 10 Figure 5.4 11.5V.4 0.5 10. 40 1 Min.. Symbol VDDreg ∆VDDreg Error amplifier section Parameter VDD regulation point VDD regulation point total variation Unity gain bandwidth Voltage gain DC transconductance Test conditions ICOMP = 0mA Figure 11. 34 -12 -2 Max. In order to insure a correct stability of the error amplifier. on page 11 VCOMP = 2. VDD= 14V Figure 11. VDD = 5V. on page 11 ICOMP = 0mA. 14..4mA.VIPer53 . VDD = 16V ICOMP = 0.E Electrical characteristics Table 5. 100°C From Input = VDD to Output = VCOMP ICOMP = 0mA Figure 14 and 15 ICOMP = 0mA Figure 14 and 15 VCOMP = 2.5 -0.5 V % GBW AVOL Gm 700 45 1. 7. VDD=14V(1) VCOMP = 2. a capacitor of 10nF (minimum value: 8nF) should always be present on the COMP pin.8 kHz dB mS V V mA mA VCOMPlo Output low level VCOMPhi Output high level ICOMPlo ICOMPhi Output sinking current Output sourcing current 1. VDS = 100V Figure 5 on page 10 VDD = 10V. ICOMP = -0.. TJ > TSD . Unit 50 V mA mA mA 8 9 8.2 2. 15 2 Max. Unit 15. Figure 5.8 V V V 19 V Table 6.5 Typ.6 17 0 Min. Typ. 5V.5V Figure 11.5V. 5/36 . TJ = 0 .3 12. VDS = 100VFigure 7.6 1. VDS = 100VFigure 5.2 4.6 0.4mA.

3 A IDmax td VCOMPbl tb1 tb2 tONmin1 tONmin2 VCOMPoff 1.. Unit °C °C 6/36 .. dID/dt = 0 VCOMP = VCOMPovl. on page 11 ICOMP = 0mA.Electrical characteristics VIPer53 .3 A ns V Current sense delay to ID = 1A Turn-Off VCOMP blanking time change threshold Blanking time Blanking time Minimum On time Minimum On time VCOMP Shutdown Threshold Figure 6 on page 10 VCOMP < VCOMPBLFigure 6.7 2 2.35 Max. VTOVL = 0V dID/dt = 0 Min.. Symbol HCOMP PWM comparator section Parameter ∆VCOMP / ∆IDPEAK Test conditions VCOMP = 1 . 4. dID/dt = 0 dID/dt = 0 Figure 10. 4 8 V ms 1. VTOVL = 0V Figure 10. Max. Unit 1. 140 Typ. 160 40 Max.5 500 200 750 450 ns ns ns ns V Table 8. VDDreg. Symbol VCOMPovl Overload protection section Parameter VCOMP overload threshold VCOMPhi to VCOMPovl voltage difference VTOVL overload threshold Overload delay Test conditions ITOVL = 0mA (1) Figure 4 on page 9 VDD = VDDoff . VCOMP > VCOMPBLFigure 6. (1) Min. Typ. Symbol TSD THYST Over temperature Protection Section Parameter Thermal shutdown temperature Thermal shutdown hysteresis Test Conditions Figure 7 on page 10 Figure 7 on page 10 Min.7 2 0.E Table 7. COVL = 100nF Figure 4. VCOMP < VCOMPBL VCOMP > VCOMPBL Figure 9 on page 11 300 100 450 250 400 150 600 350 0. Typ. 4 V Figure 10.3 V/A V VCOMPos VCOMP Offset IDlim Peak drain current limitation Drain current capability 1. Unit V VDIFFovl 50 150 250 mV VOVLth tOVL Figure 4.9 250 1 2. ITOVL= 0mA Figure 4.6 1. VCOMPovl is always lower than VCOMPhi Table 9..5 2.

E Pin connections and function 3 Pin connections and function Figure 1. Pin connection (top view) COMP 1 8 TOVL OSC 2 7 VDD SOURCE 3 6 NC SOURCE 4 5 DRAIN DIP-8 PowerSO-10 Figure 2. Current and voltage conventions IDD ID VDD IOSC OSC 15V DRAIN VDD ITOVL VOSC TOVL COMP SOURCE VDS ICOMP VTOVL V COMP 7/36 .VIPer53 .

Allows the connection of an external capacitor for delaying the overload protection. and output of the internal error amplifier.35V.4 V). Power MOSFET source and circuit ground reference. and the overload protection is triggered if the voltage exceeds 4.5V. The useful voltage range extends from 0. . Pin Name Pin function Pin function Power supply of the control circuits.VDDon: Voltage value at which the device starts switching (Typically 11. Allows the setting of thedynamic characteristic of the converter through an external passive network. This action is delayed by the timing capacitor connected tothe TOVL pin.5V to 4.5V. Also provides the charging current of the external capacitor during start-up.VDDoff: Voltage value at which the device stops switching (Typically 8.E Table 10. Allows the setting of the switching frequency through an external Rt-Ct network.35V. The Power MOSFET is always off below 0. Input of the current mode structure. Also used by the internal high voltage current source during the start-up phase to charge the external VDD capacitor.VDDreg: Regulation voltage point when working in primary feedback (Trimmed to 15 V). VDD SOURCE DRAIN COMP TOVL OSC 8/36 . . Power MOSFET drain. The functions of this pin are managed by four threshold voltages: .VDDovp: Triggering voltage of the overvoltage protection (Trimmed to 18 V).Pin connections and function VIPer53 .5 V). which is triggered by a voltage on the COMP pin higher than 4. .

ID C<<C OSS C L D Rise and fall time t VDS 90% tfv trv TOVL COMP SOURCE OSC 15V VDD DRAIN 300V 10% t Figure 4. Overloaded event VDD Normal operation Abnormal operation VDDon VDDoff VCOMP VDIFFovl VTOVL VOVLth tOVL VDS Not switching Switching 9/36 .E Operation pictures 4 Operation pictures Figure 3.VIPer53 .

tb tb1 Blanking time VDDhyst VDDoff IDDch2 VDDon VDD VDS = 100 V FSW = 0 kHz IDDch1 tb2 VCOMPbl VCOMPhi Figure 7.E Figure 5. VDD VDDovp Overvoltage event VDD VDDon VCOMP Abnormal operation Automatic startup VCOMP VDS Not switching Switching 10/36 . IDD IDD0 Start-up VDD current Figure 6. Tj TSD TSD-THYST Thermal shutdown Figure 8.Operation pictures VIPer53 .

VOSC VOSChi Operation pictures Shutdown action Figure 10. Output characteristics ICOMP ICOMPhi Slope = Gm 0 VDDreg VDD ICOMPlo 11/36 . Comp pin gain and offset VOSClo IDpeak t VCOMP IDlim IDmax Slope = 1 / HCOMP VCOMPoff t ID VCOMP VCOMPos VCOMPovl VCOMPhi t Figure 11.VIPer53 .E Figure 9.

2nF 4.Operation pictures Figure 12.E VDD Rt OSC PWM section 320 Ω Ct SOURCE The switching frequency settings shown on the graphic here below is valid within the following boundaries: Rt > 2kΩ FSW = 300kHz Figure 13.7nF 1nF 100 10nF 22nF 10 1 10 100 RT (KΩ) 12/36 . Oscillator schematic Vcc VIPer53 . Oscillator settings Frequency (kHz) 300 2.

See figures Figure 18. 19 and 22.5 V This configuration is for test purpose only. Error amplifier transfer function Gain (dB) 60 Open 40 R = 10 kΩ 20 R = 2. Figure 15.VIPer53 . Error amplifier test cpfiguration Vin VDD DRAIN Operation pictures OSC 15V TOVL COMP SOURCE Vout R 2.2 kΩ R = 470 Ω 0 -20 -40 -60 1 10 100 1k 10k 100k 1M 10M Frequency (Hz) 13/36 . In order to insure a correct stability of the error amplifier.E Figure 14. a capacitor of 10nF (minimum value: 8nF) should be always connected between COMP pin and ground.

04 1.96 -20 0 20 40 60 80 100 120 Temperature (°C) 14/36 . Typical current limitation vs.02 1 0.96 -20 0 20 40 60 80 100 120 Temperature (°C) Figure 17. junction temperature Normalised IDlim 1. junction temperature VIPer53 .98 0.Operation pictures Figure 16.E Normalised Frequency 1.98 0.04 1.02 1 0. Typical frequency variation vs.

this current has to be integrated by a capacitor (C7 in Figure 18). Therefore. and is automatically regulated at 15V. Off line power supply with auxiliary supply feedback F1 AC IN C1 D1 T1 R1 C2 R2 C3 T2 D2 L1 D4 R4 D3 C8 C9 DC OUT U1 VIPer73 R3 VDD DRAIN C10 OSC 15V C4 TOVL COMP SOURCE R6 1k C5 C11 10nF C6 R5 C7 The schematic on Figure 18 delivers a fixed output voltage by using the internal error amplifier of the device in a primary feedback configuration. The error amplifier of the VIPer53 is a transconductance type: its output is a current proportional to the difference of voltage between the VDD pin and the internally trimmed 15V reference (i. As the transconductance value is set at a relatively low value to control the overall loop gain and ensure stability. When the steady state operation is reached. The secondary voltage has to be adjusted through the turn ratio of the transformer between auxiliary and secondary. the VDD voltage is accurately regulated to 15V.e. thus providing at the same time an excellent line regulation. which depends only on transformer coupling and output diodes impedance. due to the internal error amplifier connected to this pin. the error voltage). 15/36 . This results in a good load regulation. The current mode structure takes care of all incoming voltage changes. The primary auxiliary winding provides a voltage to the VDD pin..VIPer53 .E Primary regulation configuration example 5 Primary regulation configuration example Figure 18. this capacitor blocks any DC current from the COMP pin and imposes a “nil” error voltage.

For an output power of a few watts. For higher power. It can be adjusted to provide the best compromise between stability and recovery time with fast load changes.Primary regulation configuration example VIPer53 .E The switching frequency can be set to any value through the choice of R3 and C5. EMI (Lower with low switching frequencies) and transformer size (Smaller with high switching frequencies). This allows to optimize the efficiency of the converter by adopting the best compromise between switching losses. 70kHz to 130kHz are generally chosen. 16/36 . typical switching frequencies between 20kHz and 40kHz because of the small size of the transformer. The R5 compensation resistor value sets the dynamic behavior of the converter.

will deliver a constant biasing current of 0. no additional components are required to ensure a minimum current biasing of U3. and drive the PWM controller through an optocoupler as shown on Figure 17. typical load regulation of 1% can be achieved from zero to full output current with this simple configuration. 17/36 . Also.VIPer53 . and so it does not depend on the output load either. Consequently. As the current flowing in this branch remains constant for the same reason as above. The internal error amplifier will therefore be saturated in the high state. the way is to monitor it directly secondary side. the low biasing current value avoid any ageing of the optocoupler. The optocoupler is connected in parallel with the compensation network on the COMP pin. The design of the auxiliary winding that the VDD voltage is always lower than the internal 15V reference. a simple zener and resistance network in series with the optocoupler diode can insure a good secondary regulation. Off line power supply with optocoupler feedback F1 AC IN C1 D1 T1 R1 C2 R2 C3 T2 D2 L1 D4 R4 U1 VIPer73 R3 VDD DRAIN C10 D3 C8 C9 DC OUT OSC 15V R8 TOVL COMP SOURCE U2 C4 C5 R9 1k C11 10nF R5 C6 C7 C12 R7 U3 R6 When a more accurate output voltage is needed. the gain of the optocoupler ensures consequently a constant biasing of the TL431 device (U3) which is in charge of secondary regulation.E Secondary feedback configuration example 6 Secondary feedback configuration example Figure 19. This current does not depend on the compensation voltage. The constant current biasing can be used to simplify the secondary circuit: Instead of a TL431. If the optocoupler gain is sufficiently low. and because of its transconductance nature.6mA to the optotransistor.

the compensation network has only a role of gain stabilization for the optocoupler. offering the possibility of using C7 as a soft start capacitor: When starting up the converter. The rising speed of the output voltage can be set through the value of C7.6V in R5 and a rising slope across C7. and its value can be freely chosen.E Since the dynamic characteristics of the converter are set on the secondary side through components associated to U3.6 mA on the COMP pin.Secondary feedback configuration example VIPer53 . 18/36 .5V to 4. together with the operating range of 0.5V provides a soft start-up of the converter. R5 can be set to a fixed value of 1kΩ . This voltage shape. The C4 and C6 values must be adjusted accordingly in order to ensure a correct start-up. creating a constant voltage of 0. the VIPer53 device delivers a constant current of 0.

This kind of feedback includes two nested regulation loops: The inner loop controls the peak primary current cycle by cycle. For this purpose. When the Power MOSFET output transistor is on.E Current mode topology 7 Current mode topology The VIPer53-E implements the conventional current mode control method for regulating the output voltage. see Figure 19 on page 17) and is sets accordingly the peak drain current for each switching cycle. The simpler voltage mode structure which only controls the duty cycle. with the current amplifier. the blanking time function and the PWM latch. the power switch is turned off. all input voltage changes are compensated for before impacting the output voltage. and better stability for the voltage regulation loop. This function prevents anomalous or premature termination of the switching pulse in the case of current spikes caused by primary side transformer capacitance or secondary side rectifier reverse recovery time when working in continuous mode. 19/36 . the inductor current (primary side of the transformer) is monitored with a SenseFET technique and converted into a voltage.VIPer53 . leads generally to high current at start-up with the risk of transformer saturation. This structure is completely integrated as shown on the Block Diagram on page 1. The following formula gives the peak current in the Power MOSFET according to the compensation voltage: Equation 1 V COMP – V COMPos I Dpeak = ------------------------------------------------H COMP The outer loop defines the level at which the inner loop regulates peak current in the power switch. instantaneous correction to line changes. the PWM comparator. The compensation voltage can be controlled to increase slowly during the start-up phase. As the inner loop regulates the peak primary current in the primary side of the transformer. Current mode topology also provides a good converter start-up control. When VS reaches VCOMP. without any overshoot. An integrated blanking filter inhibits the PWM comparator output for a short time after the integrated Power MOSFET is switched on. so the peak primary current will follow this soft voltage slope to provide a smooth output voltage rise. VCOMP is driven by the feedback network (TL431 through an optocoupler in secondary feedback configuration. This results in an improved line regulation.

and maintains the PWM latch and the Power MOSFET in the Off state as long as VCOMP remains below 0. Note: This frequency is actually an equivalent number of switching pulses per second. The output voltage is regulated in burst mode.5V. whereas for higher voltages. Therefore the regulation loop will quickly drive VCOMP to VCOMPoff (Point 3) in order to pass into burst mode and to control the output voltage.5V (See Block Diagram on page 1). when taking into account internal propagation time. In addition. The power points value PRST and PSTBY are defined by the following formulas: Equation 2 2 11 . a comparator monitores the COMP pin voltage. and associated minimum turn on. The corresponding hysteresis can be seen on the switching frequency which passes from FSWnom which is the normal switching frequency set by the components connected to the OSC pin and to FSWstby. As long as the power remains below PRST the output of the regulation loop remains stuck at VCOMPsd and the converter works in burst mode. the minimum turn on time which defines the frontier between normal operation and burst mode changes according to VCOMP value. rather than a fixed switching frequency since the device is working in burst mode.0V (VCOMPbl). – It allows the regulation of the output voltage. the VCOMP net decreases its voltage until it reaches this 0. with the following benefits: – It reduces the switching losses. For this purpose. thus providing low consumption on the mains lines. When the output power decreases. exceeding the effective turn-on time that should be needed at this output power level. the system reaches point 2 where VCOMP equals VCOMPbl.5 W of input power when in standby. and resumes normal operation as soon as VCOMP is higher than 0. The minimum turn-on time passes immediately from 350ns to 600ns. The corresponding ripple is not higher than the nominal one at full load.e. requiring less than 0. The corresponding function described hereafter consists of reducing the switching frequency by going into burst mode. The device is compliant with “Blue Angel” and other similar standards. The hysteresis cannot be seen on the switching frequency. it is 150ns Figure 6 on page 10 The minimum turn on times resulting from these values are respectively 600 ns and 350 ns.5V threshold (VCOMPoff). If the output load requires a duty cycle below the one defined by the minimum turn on of the device.E 8 Standby mode The device offers a special feature to address the low load condition. the blanking time increases to 400ns. This brutal change induces an hysteresis between normal operation and burst mode as shown on Figure 20 on page 21.• F SWnom • ( tb 1 + td ) • V 2 IN • -----P RST = -Lp 2 20/36 . but it can be seen in the sudden surge of the COMP pin voltage from point 3 to point 1 at that power level.Standby mode VIPer53 . Its “density” increases (i. Below 1. the number of missing cycles decreases) as the power approaches PRST and finally resumes normal operation at point 1. The Power MOSFET can be completely Off for some cycles. even if the load corresponds to a duty cycle that the device is not able to generate because of the internal blanking time.

The standby frequency FSWstby is given by: Equation 4 P STBY . Standby mode implementation ton 3 600ns Minimum turn on 350ns 1 2 VCOMP VCOMPsd VCOMPoff VCOMPbl PIN PRST 3 PSTBY 2 1 FSW FSWstby FSWnom 21/36 .VIPer53 .• F SWnom • Ip 2 ( V COMPbl ) • Lp P STBY = -2 Standby mode Where Ip(VCOMPbl2) is the peak Power MOSFET current corresponding to a compensation voltage of VCOMPbl (1V). Note: The power point PSTBY where the converter is going into burst mode does not depend on the input voltage. depending on the Lp value and input voltage.E Equation 3 1 . Figure 20.• F SWnom P SWstby = ---------------P RST The ratio between the nominal and standby switching frequencies can be as high as 4.

VDD starts from 0V with a charging current IDDch1 at about 9 mA.6mA. As soon as the voltage on this pin reaches the high voltage threshold VDDon of the UVLO logic. The charging current change at VDDoff allows a fast complete start-up time tSDU. when the device starts switching. This is especially useful for short circuits and overloads conditions. 22/36 . and also supplies the external capacitor connected to the VDD pin. the device turns into active mode and starts switching. and the converter should normally provide the needed current on the VDD pin through the auxiliary winding of the transformer. This lower current leads to a slope change on the VDD rise.High voltage Start-up current source VIPer53 . When about VDDoff is reached. as described in the following section. This time tss depends on many parameters. soft start feature. and the auxiliary winding delivers some energy to VDD capacitor after the start-up time tss. and compensation network implemented on the COMP pin and possible secondary feedback circuit. The start-up current generator is switched off. and maintains a low restart duty cycle. The following formula can be used for defining the minimum capacitor needed: Equation 5 I DD1 ⋅ tss C VDD > -------------------------V DDhyst Figure 21 on page 23 shows a typical start-up event. output capacitors. including transformer design. the charging current is reduced down to IDDch2 which is about 0. This current is partially absorbed by internal control circuits in standby mode with reduced consumption.E 9 High voltage Start-up current source An integrated high voltage current source provides a bias current from the DRAIN pin during the start-up phase. as shown on Figure 19 on page 17. Device starts switching for VDD equal to VDDon. The external capacitor CVDD on the VDD pin must be sized according to the time needed by the converter to start-up.

VIPer53 .E Figure 21. Start-up waveforms High voltage Start-up current source IDD IDD1 t IDDch2 IDDch1 VDD VDDreg VDDst VDDsd tSU tSS t 23/36 .

without compromising the real start-up of the converter. Note: If VCOMP drops below the VCOMPovl threshold for any reason during the VDD drop. The maximum value of the two calculus will be adopted. In order to keep the whole converter in a safe state during this event. DRST must be kept as low as possible. 24/36 . This state is latched because of to the regulation loop which maintains the COMP pin voltage above the VCOMPovl threshold. For this purpose. recharging the VDD capacitor for a new restart cycle. the internal MOSFET driver is disabled and the device stops switching.35V has been implemented on the COMP pin. All this behavior can be observed on Figure 8 on page 10. A typical value of about 10% is generally sufficient. thus delivering its full power capability to the output. it defines the power capability of the power supply.Short-circuit and overload protection VIPer53 . the capacitor connected on the TOVL pin begins to charge. The restart duty cycle DRST is defined as the time ratio for which the device tries to restart. In Figure 10 on page 11 the value of the drain current Id for VCOMP = VCOMPovl is shown. its voltage drops down until it reaches VDDoff and the device is reset. Since the VDD pin does not receive any more energy from the auxiliary winding.E 10 Short-circuit and overload protection A VCOMPovl threshold of about 4. the device resumes switching immediately. Since IDmax represents the maximum value for which the overload protection is not triggered. The corresponding parameter IDmax is the drain current to take into account for design purposes.5 ⋅ 10 –6 ⋅ tss Equation 7 4 OVL ⋅ I DDch2 1 . both VDD and TOVL capacitors can be used to satisfy the following conditions: Equation 6 C OVL > 12. The device enters an endless restart sequence if the overload or short circuit condition is maintained.– 1⎞ ⋅ C -------------------------------------C VDD > 8 ⋅ 10 ⋅ ⎛ ------------⎝D ⎠ V DDhyst RST Refer to the previous start-up section for the definition of tss. When VCOMP goes above this level. and CVDD must also be checked against the limit given in this section. When reaching typically VOVLth (4V).

minimum value) should always be connected to the COMP pin to ensure a correct stability of the internal error amplifier.0 for different values of a simple resistance connected on the COMP pin.4mA/V. for the schematic and Figure 23 on page 28 for the error amplifier transfer function for a typical set of values of CCOMP and RCOMP. The unloaded transconductance error amplifier shows an internal ZCOMP of about 140KΩ . very similar to the one above: Equation 11 F ( s ) = Gm ⋅ Z ( s ) The error amplifier frequency response is shown in . and a resistance in series leads to a flat gain at higher frequency. A theoretical example can be seen in Figure 24 for a discontinuous mode flyback loaded by a simple resistor. This configuration illustrated in Figure 22. Note that a 10nF capacitor (8nF.--------------------.VIPer53 . are subject to large tolerances. More complex impedances can be connected on the COMP pin to achieve different compensation methods. The complete converter open loop transfer function can be built from both power cell and error amplifier transfer functions. Gm is well defined by specification. and therefore AVOL. A capacitor provides an integrator function. An impedance Z must be connected between the COMP pin and ground in order to accurately define the transfer function F of the error amplifier.= --------Z COMP = --------------------⋅ ∂I COMP Gm ∂V DD This last equation shows that the open loop gain AVOL can be related to Gm and ZCOMP: Equation 10 A VOL = Gm ⋅ Z COMP where Gm value for VIPer53 is typically 1. introducing a zero level and ensuring a correct phase margin. Transconductance Gm is the change in output current ICOMP versus change in input voltage VDD.E Transconductance error amplifier 11 Transconductance error amplifier The VIPer53-E includes a transconductance error amplifier. regulated from primary side (no 25/36 . thus eliminating the DC static error. but ZCOMP. the following equation. Thus: Equation 8 ∂I COMP Gm = ------------------∂V DD The output impedance ZCOMP at the output of this amplifier (COMP pin) can be defined as: Equation 9 ∂V COMP ∂V COMP 1 .

the unity gain is reached in a first order slope. A typical schematic corresponding to this situation can be seen on Figure 18.Transconductance error amplifier VIPer53 . As the highest bandwidth is obtained with the highest output power (Plain line with RL2 load in Figure 24). but some limitations have to be respected: As the transfer function above the zero due the capacitor ESR is not reliable (The ESR itself is not well specified. A zero at higher frequency values then appears. The dynamic load regulation is improved by increasing the regulation bandwidth. For maximum load (plain line). and other parasitic effects may take place). The point where the complete transfer function has a unity gain is known as the regulation bandwidth and has: – – The higher it is. similar to the one shown in Figure 23. In Figure 24. RL1 and RL2. the load pole is exactly compensated by the zero of the error amplifier. the above criteria will be checked for this condition and allows to define the value of RCOMP. the internal error amplifier is fully used for regulation). Note: The overall transfer function does not depend on the input voltage because of the current mode control. The transfer function of the power cell is represented as G(s) in Figure 24 Iexhibits a pole which depends on the output load and on the output capacitor value. The error amplifier cut-off then definitely any further spurious noise or resonance from disturbing the regulation loop. the faster the reaction will be to an eventual load change. The total transfer function is shown as F(s). As the load of a converter may change.E optocoupler. Generally. The following formula can be derived: Equation 12 R COMP = 2 P OUT2 F BW2 ⋅ R L2 ⋅ C OUT ---------------. The phase shift in the complete system at this point has to be less than 135° to ensure good stability. as the error amplifier gain depends only on this value for this frequency range. A zero due to the RCOMP-CCOMP network is set at the same value as the maximum load RL2 pole. so the stability is ensured. due to the output capacitor ESR. the bandwidth should always be lower than the minimum of FC and ESR zero. and the smaller the output voltage change will be. The error amplifier has a fixed behavior.⋅ ----------------------------------------------------Gm P MAX 1 . Its bandwidth is to avoid injection of high frequency noise in the current mode section.⋅ LP ⋅ I2 and: PMAX = -LIM ⋅ F SW 2 OUT With: POUT2 = -------------- V R L2 26/36 . and a second-order gives 180°. two curves are shown for two different values of output resistance value. a first-order slope gives 90° of phase shift. G(s) at the bottom of Figure 24. and the result is a perfect first order decreasing until it reaches the zero of the output capacitor ESR.

VIPer53 . This condition can be met by adjusting the CCOMP value: Equation 13 R L1 ⋅ C OUT -⋅ C COMP > ----------------------------------------------------2 6. Figure 22. It can be then increased to provide a natural soft start function as this capacitor is charged by the error amplifier current capacity ICOMPhi at start-up. Typical compensation network VDD DRAIN OSC 15V TOVL COMP SOURCE Rcomp 10nF Ccomp 27/36 .E Transconductance error amplifier The lowest load gives another condition for stability: The frequency FBW1 must not encounter the second order slope generated by the load pole and the integrator part of the error amplifier.3 ⋅ Gm ⋅ R COMP P OUT1 -----------------P MAX With: 2 V OUT P OUT1 = --------------R L1 The above formula gives a minimum value for CCOMP.

E 50 40 30 20 10 0 -10 1 10 100 1k 10k 100k 1M Phase (°) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 1 10 Frequency (Hz) Rcomp=4. Typical transfer functions Gain (dB) 60 Rcomp=4.Transconductance error amplifier Figure 23.7k Ccomp=470nF 100 1k 10k 100k 1M Frequency (Hz) 28/36 .7k Ccomp=470nF VIPer53 .

G(S) 1 FBW1 FBW2 F 29/36 .E Figure 24. Complete converter transfer function Transconductance error amplifier G(S) 1 ---------------------------------------------π⋅ R ⋅ C L1 OUT 1 ---------------------------------------------π⋅ R ⋅ C L2 OUT F 1 1 ----------------------------------------------------------2 ⋅ π ⋅ ESR ⋅ C OUT F(S) 1 --------------------------------------------------------------------------2⋅ π⋅ R ⋅ C COMP COMP FC F 1 F(S).VIPer53 .

19 and 22. 13 Software implementation All the above considerations and some others are included included in ST design software which provides all of the needed components around the VIPer device for specified output configurations.Special recommendations VIPer53 . and is available on www. a resistance of 1kΩ should be inserted in series with the TOVL pin. as its value is negligible prior to the internal pull-up resistance (about 125kΩ).com. Note that. this resistance does not impact the overload delay.E 12 Special recommendations As steted in the error amplifier section.st. as shown on Figure 18. 30/36 . a capacitor of 10nF capacitor (minimum value: 8nF) should always be connected to the COMP pin to ensure correct stability of the internal error amplifier Figure 18. Figure 19 on page 17. In order to improve the ruggedness of the device versus eventual drain overvoltages.

The maximum ratings related to soldering conditions are also marked on the inner box label. These packages have a Lead-free second level interconnect. ECOPACK specifications are available at: www. 31/36 .VIPer53 . in compliance with JEDEC Standard JESD97.E Package mechanical data 14 Package mechanical data In order to meet environmental requirements. ECOPACK is an ST trademark.st. The category of second Level Interconnect is marked on the package and on the inner box label.com. ST offers these devices in ECOPACK® packages.

25 9.46 1.26 7.11 Min Max 5.16 8.02 7.78 0.20 9.92 0.52 0. Nom.92 3.81 4.Package mechanical data VIPer53 .56 1.36 10. Package dimensions 32/36 .35 2.54 7.36 1.E Table 11.10 3.62 10.87 6. 470 0. A A1 A2 b b2 c D E E1 e eA eB L 2. DIP8 mechanical data Dimensions Databook (mm) Ref.30 Gr.14 0.27 7.30 0.62 6.95 0.38 2.92 3.33 Package Weight Figure 25.

VIPer53 .10 5.90 1.35 0.20 7.65 0.80 3.70 8° 1.27 1.50 7.40 Min Max 3.60 9.40 7.20 6.00 0. Package dimensions 33/36 .50 1.60 0.10 Figure 26.55 9.20 1. Nom.40 9.40 0.60 6.10 0.E Table 12.25 13.60 7. A A1 B c D D1 E E1 E2 E3 E4 e F H h L q α 0° 1.30 7. PowerSO-10 mechanical data Dimensions Package mechanical data Databook (mm) Ref.35 14.40 7.80 0.35 6.35 9.

E 15 Order codes Table 13. Order codes Package DIP-8 PowerSO-10 PowerSO-10 Shipment Tube Tube Tape and reel Part Number VIPer53DIP-E VIPer53SP-E VIPer53SPTR .Order codes VIPer53 .E 34/36 .

Date 13-Nov-2006 Revision history Revision 1 Initial release. Changes 35/36 .VIPer53 .E Revision history 16 Revision history Table 14.

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