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The Intel 8085A microprocessor(µP)
Intel 8085 CPU
• Introduced on March 1976 • 8-bit microprocessor • 3 MHz • 6500 Transistors • 64K Byte addressable memory
• The 8085A is an 8-bit general purpose microprocessor that can address 64K Bytes of memory. • It has 40 pins and uses +5V for power. It can run at a maximum frequency of 3 MHz. – The pins on the chip can be grouped into 6 groups: Address Bus Data Bus Control and Status Signals Power supply and frequency Externally Initiated Signals v Serial I/O ports
8085A Pin Diagram Clock 8085 A Address ( Low order) and data Bus Address Bus ( High order) 8085 A Pin Diagram 4 .
8085A Pin Diagram 5 .
5 RST 6.5 RST 5.5 INTR 6 7 8 9 10 A8 High – Order Address Bus 21 AD7 19 Interrupts & Externally Initiated Signals READY HOLD RESETIN Multiplexed Address/ Data Bus 35 39 36 AD0 12 30 29 33 34 32 31 11 38 INTA HLDA ALE S0 S1 IO/M RD WR Control and Status Signals 3 RESET OUT 37 CLK OUT 6 .8085A : Groups GRD 20 1 2 X2 40 Vcc A15 26 SID SOD 5 4 X1 Serial I/O Ports TRAP RST 7.
The 8085 Bus Structure The 8-bit 8085 CPU (or Micro Processing Unit) communicates with the other units using a 16-bit address bus. an 8-bit data bus and a control bus 7 .
2. then during the late parts of the execution. So. The other 8 address bits are multiplexed (time shared) with the 8 data bits. 8 signal lines A8 – A15 are unidirectional. the bits AD0 – AD7 are bi-directional and serve as A0 – A7 and D0 – D7 at the same time. these lines carry the address bits during the early part. Bus: A shared group of wires used for communicating signals among devices Mallika Verma 8 . During the execution of the instruction. they carry the 8 data bits.The Address and Data Bus: Interconnections between units The address bus consists of 16 address lines of which 1.
16 address lines are capable of addressing a total of 216 = 65. Address locations: 0000 (Hex) – FFFF (Hex) Data range: 00 (Hex) – FF (Hex) Bus: A shared group of wires used for communicating signals among devices 9 . a latch can be used to save the value before the function of the bits changes.536 (64k) memory locations.The Address and Data Bus: Interconnections between units Important Facts In order to separate the address from the data.
This signal can be used to enable a latch to save the address bits from the AD lines. Bus: A shared group of wires used for communicating signals among devices Mallika Verma 10 .The Control and Status Signals There are 4 main control and status signals. Active low. This signal is a pulse that become 1 when the AD0 – AD7 lines have an address on them. • RD: Read. Active low. It becomes 0 after that. • IO/M: This signal specifies whether the operation is a memory operation (IO/M=0) or an I/O operation (IO/M=1). • WR: Write. These are: • ALE: Address Latch Enable. • S1 and S0 : Status signals to specify the kind of operation being performed .
Frequency Control Signals There are 3 important pins in the frequency control group. • The frequency is internally divided by 2. a clock running at 6 MHz should be connected to the X0 and X1 pins. – CLK (OUT): An output clock pin to drive the clock of the rest of the system. to run the microprocessor at 3 MHz. – So. – X0 and X1 are the inputs from the crystal or clock generating circuit. Mallika Verma 11 .
the low order bits remain for only one clock period and they would be lost if they are not saved externally. Mallika Verma 12 . – The high order bits of the address remain on the bus for ~three clock periods. – To make sure an external latch to save the value of AD7– AD0 when it is carrying the address bits is used.Demultiplexing AD7-AD0 – it is obvious that the AD7– AD0 lines are serving a dual purpose and that they need to be demultiplexed to be used in both situations. The ALE signal enables this latch. However.
A0 D7. the address is saved and the AD7– AD0 lines can be used for their purpose as the bi-directional data lines. Then when ALE goes low. the address is latched.D0 Given that ALE operates as a pulse during first clock pulse T1.Demultiplexing AD7-AD0 8085 A15-A8 ALE AD7-AD0 Latch A7. Mallika Verma 13 .
Each Memory Location stores one byte (8 bits) There is a a lot of interaction between the microprocessor and the memory for • exchange of information during program execution •. The interfacing operation is simply the matching of these requirements Mallika Verma 14 . control signals and their timing • Memory has its requirements and the microprocessor has its requirements as well .Memory Memory: Where instructions (programs) and data are stored Organized in arrays of locations (addresses). .
Memory structure & its requirements RAM Data Lines ROM Input Buffer WR Address Lines CS Address Lines CS Output Buffer RD Output Buffer RD Data Lines Date Lines • • The process of interfacing the above two chips is the same. The ROM does not have a WR signal 15 Mallika Verma .
The MEMR signal can be used to enable the RD line on the memory chip. – Translating this to microprocessor domain: – The microprocessor places a 16-bit address on the address bus. – Identify the memory register. Mallika Verma 16 . – Part of the address bus will select the chip and the other part will go through the address decoder to select the register. – Enable the appropriate buffer. – The signals IO/M and RD combined indicate that a memory read operation is in progress.Interfacing Memory – Accessing memory can be summarized into the following three steps: – Select the chip.
However. – Reads may not return last value written – Writes may have side effects Mallika Verma 17 . I/O registers are connected to external wires.I/O • I/O devices: Enable system to interact with the world – Device interface hardware connects actual device to bus – The CPU views the I/O device registers just like memory that can be accessed over the bus. etc. device control logic.
Mallika Verma 18 .Address decoding • The result of address decoding is the identification of a register for a given address. – This portion is decoded internally within the chip. – A large part of the address bus is usually connected directly to the address inputs of the memory chip. – This can be done either using logic gates or a decoder. – What concerns us is the other part that must be decoded externally to select the chip.
The Overall Picture Putting all of the concepts together.A10 Chip Selection Circuit 8085 A15-A8 ALE AD7-AD0 Latch CS A9.D0 1K Byte Memory Chip WR RD IO/M RD WR Mallika Verma 19 .A0 D7.A0 A7. we get: A15.
The Latch in Detail ALE is High the latch is transparent Output changes according to input data Output follows the input as long as G is high ALE Low Output of latch represents low order address bus The output does not change and retains the D input level which is the low order address 8 such latches de-multiplex the AD bus ALE Enable G AD7 D Q A7 74LS373 OC D7 Mallika Verma 20 .
The 8085: Pin outs and details ADDRESS LINES A8 .AD7: These tri-state lines may by either inbound or outbound. They provide a multiplexing between the lower 8 bits of the 16-bit-wide address early in a machine cycle and 8 data bits later in the cycle. When containing addresses. • • • • • Mallika Verma 21 . ADDRESS-DATA LINES AD0 .536 locations. They provide the upper 8 bits of the 16-bit-wide address which identifies one unique 8-bit byte within the µP’s address space. they may be either inbound or outbound. They also will contain the 8 bits of an I/O device address during an I/O operation. these lines are outbound only.A15: These tri-state lines are outbound only. Sixteen address lines provide an address space of 65. when containing data. depending upon the nature of the machine cycle.
so that the full address will be available to the system for the rest of the machine cycle.AD7 lines contain the lower 8 bits of a memory address.The 8085: Pin outs and details • ADDRESS LATCH ENABLE (ALE): This signal appears outbound early in a machine cycle to advise the external circuitry that the AD0 . S1. • • • Mallika Verma 22 . The falling edge of ALE is the point at which the signals on the AD lines. It should be used to clock a catch-and-hold circuit such as a 74LS245 or 74LS373. as well as the S0. and IO/M lines will be stable and may be taken by the external circuitry.
Mallika Verma 23 . as well as identify its direction. & IO/M: These three status lines serve to indicate the general status of the processor with respect to what function the µP will perform during the machine cycle. or toward I/O (line is high). The IO/M line approximates in one line what the S0 and S1 lines do in two. such as very slow RAM or other specialized devices. S1.The 8085: Pin outs and details STATUS LINES S0. Write indicates that the µP is going to send data away from itself. The S0 and S1 lines are made available for circuits which need advanced warning of the ensuing operation. READ & WRITE (RD & /WR): These lines indicate which direction the MP expects to pass data between itself and the external data bus. It indicates whether the operation will be directed toward memory (line is low). These lines also serve to time the event. Read indicates that the µP is expecting data to be fed to it.
Upon receipt of HOLD. • • • • • • Mallika Verma 24 . will cause the 8085 to enter wait states.The 8085: Pin outs and details • • • READY: This is an input line which may be used as a signal from external RAM that a wait state is needed. and certain control lines. then generate HLDA. The negation of Ready. by being pulled low. HOLD & HOLD ACKNOWLEDGE (HOLD & HLDA): These lines provide the 8085 with a DMA capability by allowing another processor on the same system buses to request control of the buses. The µP will remain off the buses until HOLD is negated. See the timing diagrams for critical timing. data. since the RAM is not able to provide the data or accept it in the time allowed by the µP . This signals the other processor that it may proceed. the µP will tristate its address.
5. The interrupting device will jam a Restart (RST) instruction onto the data bus.. Mallika Verma 25 . These lines have priority over the INTR line.The 8085: Pin outs and details INTERRUPT & INTERRUPT ACKNOWLEDGE (INTR & INTA): These lines provide a vectored interrupt capability to the 8085.5: These three lines are additional interrupt lines which generate an automatic Restart. which the µP uses to locate an interrupt vector in low RAM. TRAP: This is an unmaskable interrupt with a fixed vector in RAM. and may be masked off or on by software.5. 7. 6. then generate INTA as it enters the next machine cycle. Upon receipt of INTR. RST 5. the µP will complete the instruction in process. They also have certain electrical characteristics for assertion. and each other.
Upon receipt of this signal. • • • • X1 & X2: These two pins provide connection for an external frequency determining circuit to feed the 8085’s clock. the µP will internally synchronize the Reset with the clock of the processor.The 8085: Pin outs and details • RESET IN & RESET OUT: These lines provide for both µP and system reset. The internal oscillator of the ‘85 will divide the frequency by two for the system clock. such as an RC network or Reset switch. then generate RESET OUT for other devices in the system. although other resonant circuits may be used. The RESET IN line is generated asynchronously by some sort of external circuit. This is normally a crystal. • • • Mallika Verma 26 .
6. SERIAL INPUT DATA & SERIAL OUTPUT DATA (SID & SOD): These two lines provide for a single serial input or output line to/from the 8085. These lines are brought into the device as D7.5. and 7. and TRAP.The 8085: Pin outs and details CLOCK (CLK): This line provides a system clock signal to external circuits which need to be in synchronization with the µP . These two instructions also have control over the mask which controls the RST 5. Vcc & Vss: These are the power connections for +5 volts and ground Mallika Verma 27 . The SID and SOD lines are simple single bit I/O lines.5.5. and may be tested or set by the Read Interrupt Mask (RIM) or Set Interrupt Mask (SIM) instructions. any timing required to provide external communication via them must be provided by the software. interrupts.
Accumulator) – Perform arithmetic and logic operations (ALU) – Test for conditions (IF / THEN) – Sequence the execution of instructions – Store temporary data in RAM during execution Mallika Verma 28 .The 8085: CPU Internal Structure The internal architecture of the 8085 CPU is capable of performing the following operations: – Store 8-bit data (Registers.
8085 Functional Block Diagram Mallika Verma 29 .
The 8085: CPU Internal Structure Simplified block diagram Mallika Verma 30 .
the ALU includes the accumulator. This temporary register is not accessible by the programmer. • Also. Mallika Verma 31 .The 8085: CPU Internal Structure The ALU • In addition to the arithmetic & logic circuits. the ALU includes a temporary register used for holding data temporarily during the execution of the operation. which is part of every arithmetic & logic operation.
The 8085: Registers Mallika Verma 32 .
The 8085: CPU Internal Structure Registers – Six general purpose 8-bit registers: B. Mallika Verma 33 . E. C. H. move. etc). Accumulator – – Single 8-bit register that is part of the ALU ! Used for arithmetic / logic operations – the result is always stored in the accumulator. D. L – They can also be combined as register pairs to perform 16-bit operations: BC. HL – The H&L register pair may be used to store indirect addresses – Registers are programmable (data load. DE.
Zero. etc. Stack Pointer (SP) Contains the address information(16 bit) of the location of the stack. – Carry. This register is always incremented/decremented by 2. – Conditional operations (IF / THEN) are executed based on the condition of these flag bits.The 8085: CPU Internal Structure Program Counter (PC) Contains the memory address (16 bits) of the instruction that will be executed in the next step. Parity. Sign. Flag Bits – Indicate the result of condition tests. Mallika Verma 34 .
(DCR B). This flag is used only internally for BCD operations. Otherwise it is cleared. So.5 describes BCD addition including the DAA instruction). • P-Parity flag – After an ALU operation if the result has an even # of 1’s the p-flag is set. • AC-Auxiliary Carry – This flag is set when a carry is generated from bit D3 and passed to D4 . Otherwise it is cleared. Otherwise is reset. the flag can be used to indicate borrow for subtraction. • Z-zero flag – Set if the result of the ALU operation is 0. So.The Flags Register There is also the flags register(5 bits) whose bits are affected by the arithmetic & logic operations. (Section 10. the flag can be used to indicate even parity. • CY-carry flag – After an ALU operation if the operation results in a carry the carry flag is set. This flag is affected by operations on the accumulator as well as other registers. Mallika Verma 35 . • S-sign flag – The sign flag is set if bit D7 of the accumulator is set after an arithmetic or logic operation.
The Flag register D7 D6 D5 D4 D3 D2 D1 D0 S Z X AC X P X CY Mallika Verma 36 .
8085:SYSTEM TIMING The time required by the 8085 to fetch and execute one machine language instruction is defined as an Instruction Cycle. however. The 8085’s method of instruction execution inside the µP is more organized. The instructions may be of different complexities. and so the time required to execute any instruction is more predictable and more regular. with the result that the more complicated instructions take longer to execute. Mallika Verma 37 .
– Machine Cycle: The time required to complete one operation of accessing memory. A T-state lasts for one clock period. • In the 8085.Cycles and States – T. or acknowledging an external request. I/O. • An instruction’s execution length is usually measured in a number of T-states.State: One subdivision of an operation. Mallika Verma 38 . (clock cycles). an instruction cycle may consist of 1 to 6 machine cycles. • This cycle may consist of 3 to 6 T-states. – Instruction Cycle: The time required to complete the execution of an instruction.
• The three main types are: • Memory Read and Write. the operations can be grouped into a small set. • Request Acknowledge.More on the 8085 machine cycles • The 8085 executes several types of instructions with each requiring a different number of operations of different types. • These can be further divided into various operations (machine cycles). However. Mallika Verma 39 . • I/O Read and Write.
8085:THE PROCESS0R CYCLE Each instruction is divided into one to five Machine Cycles. These six lines can define seven different machine cycle types Mallika Verma 40 . Each machine cycle is essentially the result of the need. by the instruction being executed. cycles numbers 2 & 3 may be needed to fetch two more bytes of an address. WR. S0. the first to obtain the instruction byte itself. to access the RAM. while numbers 4 & 5 may be needed to save a 2-byte address somewhere else in RAM. and the remaining four to be divided into fetching and saving other bytes. and the control lines RD. and INTA. The longest. in which the instruction itself is obtained from RAM. The shortest instruction would require just one machine cycle. For example. and S1. The type of machine cycle being executed is specified by the status lines IO/M. of five machine cycles. would consist of five RAM accesses.
5. 4. 3. 6. OP CODE FETCH MEMORY READ MEMORY WRITE I/O READ I/O WRITE INTERRUPT ACKNOWLEDGE BUS IDLE Mallika Verma 41 .Machine Cycles :Types 1. 7. 2.
Control and Status signals
ALE, RD, WR, IO/M, S0 and S1
Machine cycle IO/M Op-code Fetch Memory Read Memory Write IO Read IO Write Interrupt Acknowledge Halt Hold Reset 0 0 0 1 1 1 Z Z Z Status S1 1 1 0 1 0 1 0 X X S0 1 0 1 0 1 1 0 X X
Control Signals RD = 0 RD = 0 WR = 0 RD = 0 WR = 0 INTA = 0 RD, WR = Z and INTA = 1
Generating Control Signals
The 8085 generates a single RD signal. However, the signal needs to be used with both memory and I/O. So, it must be combined with the IO/M signal to generate different control signals for the memory and I/O. – Keeping in mind the operation of the IO/M signal we can use the following circuitry to generate the right set of signals:
Example: Instruction Fetch Operation
– All instructions (program steps) are stored in memory. – To run a program, the individual instructions must be read from the memory in sequence, and executed. • Program counter puts the 16-bit memory address of the instruction on the address bus
• Control unit sends the Memory Read Enable signal to access the memory • The 8-bit instruction stored in memory is placed on the data bus and transferred to the instruction decoder Instruction is decoded and executed
Example: Instruction Fetch Operation Mallika Verma 45 .
S0 and S1 are both 1.Op-code Fetch Machine Cycle • The first step of executing any instruction is the Op-code/Instruction fetch cycle. • T4 is used to decode and execute it. Mallika Verma 46 . – In this cycle. • To differentiate this machine cycle from the very similar “memory read” cycle. the microprocessor brings in the instruction’s Op-code from memory. • The 8085 uses the first 3 T-states to fetch the op-code. the control & status signals are set as follows: – IO/M=0. – It is also possible for an instruction to have 6 T-states in an op-code fetch machine cycle. – This machine cycle has four T-states.
Op-code Fetch: Timing Diagram T1 CLK T2 T3 Timing transfer of byte From memory to µP A15 –A8 Higher order address 05H Low order address M 20H AD7 – AD0 4FH Memory content ALE IO/M RD 47 .
Memory Read Machine Cycle • The memory read machine cycle is exactly the same as the opcode fetch except: – It only has 3 T-states – The S0 signal is set to 0 instead Mallika Verma 48 .
The Memory Read Machine Cycle – To understand the memory read machine cycle. 49 Mallika Verma . it will need at least two machine cycles. 32 – In memory. – The second machine cycle is the Memory Read Cycle.10 page 83. Therefore. – The first machine cycle is the opcode fetch discussed earlier. – Figure 3. – The 8085 needs to read these two bytes from memory before it can execute the instruction. let’s study the execution of the following instruction: • MVI A. this instruction looks like: • The first byte 3EH represents the opcode for loading a byte into the accumulator (MVI A). the second byte is the data to be loaded.
Example: Memory Read Operation Mallika Verma 50 .
Mallika Verma 51 .
2000H 2001H 3E 32 Mallika Verma 52 .
8085 Functional Block Diagram Mallika Verma 53 .
Arithmetic . increment and decrement.setting/clearing flag bits. return from subroutine and restarts. • Other Machine Instructions .AND. • Input/Output instructions. subtract. stack operations.add.conditional. Logic . unconditional. XOR and rotate. Mallika Verma 54 . OR.8085:Instruction Set 8085 instruction set consists of the following instructions: • • • • Data movement instructions. call subroutine. etc. enabling/disabling interrupts. Control transfer .
where the data is stored Instructions are 3 byte in length Immediate Addressing contains the data (8 or 16-bit data) itself 2 or 3 byte instructions Stack Addressing Contents of stack pointer is data itself 55 .Addressing modes Direct addressing: Simple instructions. address of the memory location is contained in the instruction itself Instructions are 3 byte in length Register Direct addressing: Address is that of data in register or register pair not memory location Instructions are executed faster. they need not be fetched from memory Single byte instructions Register indirect addressing Instruction specifies register pair containing address.
specifies MEMORY contents with H&L as the register to contain the address.DATA TRANSFER GROUP This group of instructions provides the 8085 with the ability to move data around inside the RAM. No other register pair can be used as such. between the RAM and the registers of the µP .r) are the general means of moving data between memory and registers • They are one byte instructions • Copies data from the source register r2 to the destination register r1 • Illustrate the use of the Register Indirect mode of addressing • The letter "M".r2. They are important because a good deal of moving must be done in programming MOV GROUP: Three instructions (MOV r1. and between registers within the µP .M. MOV r. and MOV M. Mallika Verma 56 .
r2 Cycle 1 T state 4 Address register Flags None Hex. Code B B C D Destination Location E H L M A 40 48 50 58 60 68 70 78 C 41 49 51 59 61 69 71 79 Source Location D 42 4A 52 5A 62 6A 72 7A E 43 4B 53 5B 63 6B 73 7B H 44 4C 54 5C 64 6C 74 7C L 45 4D 55 5D 65 6D 75 7D 7E M 46 4E 56 5E 66 6E A 47 4F 57 5F 67 6F 77 7F 57 MOV M. MOV r.M Cycle 2 T state 7 Address register indirect Flags None .r .MOV Instruction: Data Transfer Group MOV r1.
3 T state 7. d8 Cycle 2. • Note that the Register Indirect mode again is evident. MVI M. • The immediate data is stored as a byte directly below the instruction byte.MOVE IMMEDIATE : Data Transfer Group MVI GROUP: • These two instructions (MVI r. and MVI M.data) provide a means of loading a byte immediately into a register or a memory address.data. MVI r.d8 Move immediate 8 bit data. 10 B C D E H Address immediate 06 0E 16 1E 26 Flags None L 2E M 36 A 3E 58 .
but only indirectly. again with the inverse addressing • This is a 3 byte instruction LDA addr16 Cycle 4 T state 13 Address direct Flags None Hex code 3A Mallika Verma STA addr16 Cycle 4 Tstate 13 Address direct Flags None Hex Code 32 59 . with the help of the H&L registers. • The address of the byte to be loaded or stored follows the instruction.LOAD ACUMULATOR:DATA TRANSFER GROUP LDA & STA: • The Load Accumulator Direct (LDA) and the Store Accumulator Direct (STA) instructions provide a means of moving a byte between the accumulator and a RAM address. that is. • This may also be done with the MOV OP code.
register of the pair.LOAD Resister Pair: Data Transfer Group LXI INSTRUCTION: Load register pair immediate This single instruction (LXI rp. register of the pair LXI rp. or low-order.data 16/addr 16) provides a means of loading any register pair with a two-byte value. or high order. while the third byte is loaded into the rightmost. addr 16 Cycle 3 T state 10 Address immediate Flags None Mallika Verma B 01 D 11 H 21 SP 31 60 . The second byte of the instruction is loaded into the leftmost.
Since the H&L register pair is heavily used in the Register Indirect mode. The two bytes following the instruction contain an address in memory location again low-order in byte 2. these instructions provide a quick means of loading the two bytes of an address into the pair in only one instruction. and high-order in byte 3.DATA TRANSFER GROUP LHLD & SHLD: The Load H&L Direct (LHLD) and Store H&L Direct (SHLD) instructions provide a means of moving two bytes between the HL register pair and a Memory address pointed out by 16 bit address. LHLD addr16 Cycle 5 T state 16 Address direct Flags None Hex code 2A Mallika Verma SHLD addr16 Cycle 5 T state 16 Address direct Flags None Hex code 22 61 .
This instruction permits the accumulator to access groups of data bytes. the BC or DE pair must be previously loaded with the address desired. This is not the same as the MOV.DATA TRANSFER GROUP LDAX & STAX: • The Load Accumulator Indirect (LDAX) and Store Accumulator Indirect (STAX) instructions provide a means of moving data between the accumulator and a memory location indirectly. as may be necessary with long precision arithmetic. which uses only the HL register pair. They are 1 byte instructions LDAX Cycle 2 T state 7 Address indirect Flags None Hex code LDAX B 0A LDAX D 1A Mallika Verma • • • • STAX Cycle 2 T state 7 Address indirect Flags None Hex code STAX B 02 STAX D 12 62 . with the memory address contained in either the BC or DE register pair. Obviously.
when ready. This would be advantageous in complex data handling Moves the contents of four registers at a time One byte instruction XCHG Cycle 1 T state 4 Address register Flags None Hex code EB Mallika Verma 63 . then. Exchange H and L with D and E This allows an address to be built in the DE pair.DATA TRANSFER GROUP XCHG INSTRUCTION: • • • • • • The Exchange (XCHG) instruction permits the HL register pair’s contents to be exchanged with the DE register pair’s contents. to be transferred at once to the HL pair.
subtractions.ARITHMETIC GROUP This group provides the 8085 with mathematical ability • • • • • to manipulate 8-bit data to manipulate larger data (by judicious use of the codes) The Accumulator can perform additions. and compares. The other register contents can only increment or decrement by 1. All the condition flags are affected (Unless otherwise indicated) Mallika Verma 64 .
2 80 81 82 T state 4. into the accumulator. They assume that the accumulator already has in it the other value to participate in the add. 7 Address register Flags All modified to reflect the result of addition Mallika Verma E 83 H 84 L 85 M 86 A 87 65 . If the answer resulted in a ninth bit. either in a register or in the address contained by the H&L registers.ARITHMETIC GROUP ADD INSTRUCTIONS: • The Add Register (ADD r) and Add Memory (ADD M) instructions add the byte specified. it is stored in the Carry flag It is a one byte instruction • • • • ADD r. The sum will remain in the accumulator. ADD M B C D Cycle 1.
ARITHMETIC GROUP ADD WITH CARRY (ADC): • The Add Register with Carry (ADC r) and Add Memory with Carry (ADC M) instructions will add the specified byte. mathematical operations on values longer than 8 bits are possible. AND the value of the Carry bit. into the accumulator. It is a one byte instruction • • • • • Mallika Verma 66 . either in a register or in the address contained by the H&L registers. If the answer resulted in a ninth bit. By including the carry bit in the operation. the first value must already be loaded in the A register prior to execution of these instructions. it is stored in the Carry flag. The sum remains in the accumulator.
ADC M Cycle 1.ARITHMETIC GROUP • • • • • ADC r. 7 Address register Flags All modified to reflect the result of addition B 88 C D E H L 8D M 8E A 8F 89 8A 8B 8C Mallika Verma 67 . 2 T state 4.
it is stored in the Carry flag. ACI d8 ADI d 8 Cycle 2 Cycle 2 T state 7 T state 7 Address immediate Address immediate Flags All modified to reflect the Flags All modified to reflect result of addition the result of addition 68 Mallika Verma . • The sum remains in the accumulator. • The ACI instruction adds the immediate value and the value of the Carry flag.ARITHMETIC GROUP ADD IMMEDIATES: • The Add Immediate (ADI) and Add Immediate with Carry (ACI) instructions provide a means of adding a fixed value into the accumulator. • If the answer resulted in a ninth bit. • These instructions assume that an initial value has already been loaded into the accumulator. while the ADI does not take the Carry flag into account. • The immediate data is provided by the second byte of the instruction.
prior to the execution of the instructions. in a register or in the address contained by the H&L registers. The Carry flag will be set to a 1 if a borrow was required during the subtraction. The accumulator must have the first value already loaded . in which the two’s complement of the specified value is computed first.ARITHMETIC GROUP SUBTRACT INSTRUCTIONS: SUB r and SUB M subtract the specified byte. and then added to the contents of the A register. Mallika Verma 69 . The subtract is accomplished by the complement-and-add technique. from the contents of the accumulator.
SUB M Cycle 1. 2 T state 4. 7 Address register Flags All modified to reflect the result of Subtraction B 90 C D E 93 H 94 L 95 M 96 A 97 91 92 Mallika Verma 70 .ARITHMETIC GROUP • • • • • SUB r.
7 Address register Flags All modified to reflect the result of Subtraction B 98 C D E H 9C L 9D M 9E A 9F 99 9A 9B 71 Mallika Verma . • • • • • SBB r. • The Carry flag will be set to a 1 if a borrow was required during the subtraction. • The subtract is accomplished by the complement-and-add technique. • The first value must be loaded into the A register prior to the execution of the instructions. and the value of the Carry flag. 2 T state 4.ARITHMETIC GROUP SUBTRACT WITH BORROW: • The Subtract Register with Borrow (SBB r) and the Subtract Memory with Borrow (SBB M) instructions will subtract the specified byte. either in a register or in the address contained in the H&L registers. SBB M Cycle 1. from the contents of the A register.
The immediate value is provided by the second byte of the instruction. while the SUI does not take the Carry flag into account. The subtract is accomplished by the complement-and-add technique. The Carry flag will be set at the end of the instruction if .ARITHMETIC GROUP SUBTRACT IMMEDIATES: The Subtract Immediate (SUI d8) and Subtract Immediate with Borrow (SBI d8) instructions provide a means of subtracting a fixed value from the contents of the accumulator. The SBI instruction will subtract both the immediate value and the contents of the Carry flag from the A register. a borrow was required during execution. Mallika Verma 72 . The first value must be loaded into the accumulator prior to the execution of the instructions.
ARITHMETIC GROUP SUBTRACT IMMEDIATES • • • • • • SUI d 8 Cycle 2 T state 7 Address immediate Flags All modified to reflect the result of subtraction Hex Code D6 SBI d 8 Cycle 2 T state 7 Address immediate Flags All modified to reflect the result of subtraction Hex Code DE Mallika Verma 73 .
B INR r. 3 04 T state 4. • These instructions allow the programmer to create counting routines and reiterations. • Note that the Carry flag is not affected by these instructions. 10 Address register Flags All modified except Cy to reflect the result of operation C D E H 24 L 2C M 34 A 3C 0C 14 1C Mallika Verma 74 .ARITHMETIC GROUP INCREMENT INSTRUCTIONS: • The Increment Register (INR r) and Increment Memory (INR M) instructions provide a quick means of adding one to the contents of a register or memory location. INR M Cycle 1.
• One byte instruction DCR r. DCR M B Cycle 1. • These instructions allow the programmer to create counting routines and reiterations. 10 05 Address register Flags All modified except Cy to reflect the result of operation Mallika Verma C D E H 25 L 2D M 35 A 3D 0D 15 1D 75 .ARITHMETIC GROUP DECREMENT INSTRUCTIONS: • The Decrement Register (DCR r) and Decrement Memory (DCR M) instructions provide a quick means of subtracting one from the contents of a register or a memory location. • Note that the Carry flag is not affected by these instructions. 3 T state 4.
ARITHMETIC GROUP REGISTER PAIR INSTRUCTIONS: The Increment Register Pair (INX rp) and Decrement Register Pair (DCX rp) instructions provide a means of adding to. will be allowed into the low-order byte. It is also used for incrementing/ decrementing memory location INX rp. or subtracting from. this means that a borrow from the high-order byte. Note that none of the flags are affected. this means that the carry from the sum of the low order byte of the pair and the one will be added into the upper byte automatically. In the DCX instruction. if the subtraction of one from the low-order byte demands it. if required. a 16-bit value contained in a register pair. DCX rp Cycle 1 T state 6 Address register Flags none Mallika Verma INX B 03 D H SP 33 B 0B 13 23 DCX D 1B H 2B SP 3B 76 . In the INX instruction.
no other flag Mallika Verma B 09 D 19 H 29 SP 39 77 . The Carry flag will be set if a carry occurred out of the high order byte.ARITHMETIC GROUP D0UBLE ADD: • The Add Register Pair to H&L (DAD rp) instruction adds a 16 bit value already existing in the BC or DE register pair into the 16-bit value contained in the H&L registers.to high-order bytes within the add is taken into account automatically. A carry from low. The sum remains in the H&L registers. This instruction is one byte Only instruction where the accumulator is not involved in addition • • • • • DAD rp Cycle 3 T state 10 Address register Flags only CY flag affected.
into two 4-bit BCD values. again. or if the AC flag is set. i.e. is too large to fit in one byte. adding 3810 and 3816 are exactly the same. Then the high-order four bits of the A register are examined. The Carry flag. and then convert the result back into BCD. This may be done by virtue of the fact that the ten numbers of BCD (0 to 9) are coded in binary exactly as are the first ten of the sixteen numbers of binary coded hexadecimal. of course. One byte instruction 78 • • • Mallika Verma . process it in the accumulator using essentially hexadecimal arithmetic. which normally is assumed to be two 4bit hexadecimal values. a 6 is added to them. indicates that the hexadecimal value of the byte before the instruction. The conversion be may accomplished by the use of the Auxiliary Carry flag. if they contain a value >9. a value of 6 is added to these bits.. This allows the programmer to accept input data as BCD. If the contents of the low-order four bits of the A register is >9.ARITHMETIC GROUP DECIMAL ADJUST: • • • The Decimal Adjust Accumulator (DAA) instruction converts the 8-bit value in the A register. when translated to BCD. or if the Carry flag is on.
ARITHMETIC GROUP DAA Cycle 1 T state 4 Address register Flags all altered to reflect the result of operation Hex Code 27 Mallika Verma 79 .
Unless otherwise noted. all the condition flags are affected. Mallika Verma 80 .LOGICAL GROUP This group of instructions provides the decisionmaking ability of the 8085. the condition flags may be set so that they can be tested by Jumpon-condition instructions. By using these instructions. and includes some logically oriented utility instructions as well.
is a bit pattern which indicates.LOGICAL GROUP AND INSTRUCTIONS: • ANA r and ANA M instructions perform a logical And function between the specified byte. • The And function occurs on a bit-by-bit basis. in which positions of the bytes both the A register and the outside byte contained 1’s. • The result. • One byte instruction 81 Mallika Verma . and the contents of the accumulator. that bit position in the A register is reset to 0. or both. with 1’s left on. but the Carry flag is always cleared by an And. If either the bit position of the outside byte or the bit position in the A register. • This is valuable for testing the conditions of specific bits within a byte. Identical actions occur on the other seven bit positions at the same time. the bit in the A register is left as a 1. The low order bit of the specified byte is Anded with the low order bit of the A register. contained 0’s. if both the bit from the outside byte AND the bit from the A register are a 1. • The accumulator must first be loaded with an initial value. either in a register or in the address contained in the H&L registers. and reacting accordingly. left in the accumulator. • All condition flags are involved.
Z . Cy is reset and AC is set Hex Code B C D E H L A5 M A6 A A7 A0 A1 A2 A3 A4 Mallika Verma 82 .LOGICAL GROUP ANA r. 7 Address register Flags S. ANA M Cycle 1. M T state 4. P are modified to reflect the result of operation.
P are modified to reflect the result of operation. but the Carry flag is cleared. The A register must first be loaded with the byte to be tested.LOGICAL GROUP AND IMMEDIATE : The ANI d8 instruction allows the programmer to match the byte in the accumulator with a fixed mask byte. All condition flags are involved. ANI. Z . Cy is reset and AC is set Hex Code E6 83 Mallika Verma . The Anding function occurs exactly as Explained for the ANA instruction. d8 Cycle 2 T state 7 Address register Flags S. contained in the second byte of the instruction.
a 0 is loaded into that bit position of the A register. left in the accumulator. •The Or function occurs on a bit-by-bit basis. but the Carry and Auxiliary Carry flags are always cleared. •The result. value prior to the execution of these instructions.LOGICAL GROUP OR INSTRUCTIONS: •The ORA r and ORA M instructions perform inclusive Or’s between the specified byte. if either the bit from the outside byte OR the bit from the A register is a 1. •Identical operations occur on the other seven bit positions of the bytes. is a bit pattern in which a 1 exists in any bit position in which either of the bytes also had a bit set. either in a register or in the address contained in the H&L registers. If neither bit position from the outside bit or the A register is a 1. and the contents of the accumulator. or both. •All condition flags are affected. •The A register must be loaded with the first . The low order bit of the outside byte is Ored with the low order bit of the A register. Mallika Verma 84 . that bit position is set to a 1 in the A register.
P are modified to reflect the result of operation. 2 T state 4. ORA M Cycle 1.LOGICAL GROUP ORA r. 7 Address register Flags S. Z . Cy and AC are reset Hex Code B C D E H B4 L B5 M B6 A B7 B0 B1 B2 B3 Mallika Verma 85 .
All condition flags are affected. Z . The first byte must be loaded into the A register prior to execution of the instruction. d8 Cycle 2 T state 7 Address register Flags S. ORI. but the Carry and Auxiliary Carry flags are always cleared • • . Cy and AC are reset Hex Code F6 Mallika Verma 86 . P are modified to reflect the result of operation.LOGICAL GROUP OR IMMEDIATE: • The ORI d8 instruction allows the programmer to OR the contents of the accumulator with data contained in the second byte of the instruction.
either in a register or in a byte contained in the address in the H&L register. The A register must be loaded with the first byte prior to the execution of the instruction. 87 • • • • • Mallika Verma . and 0’s set where there was either 0’s in both bytes or 1’s in both bytes. in the same bit position. All condition flags are affected. but the Carry and Auxiliary Carry flags are always cleared. and the contents of the accumulator. which contains a bit pattern with 1’s set where there was a 1 in either the A register or the outside byte. T he results are left in the accumulator. Identical operations occur on the other bit positions of the bytes at the same time. The Exclusive Or occurs on a bit-by-bit basis.LOGICAL GROUP EXCLUSIVE OR INSTRUCTIONS: • XRA r and XRA M instructions perform exclusive Or functions between a specified byte.
P are modified to reflect the result of operation. XRA M Cycle 1. Cy and AC are reset Hex Code B A8 C A9 D E H L M A AF AA AB AC AD AE Mallika Verma 88 . 7 Address register Flags S. Z . 2 T state 4.LOGICAL GROUP XRA r.
All the condition flags are affected. P are modified to reflect the result of operation. Cy and AC are reset Hex Code EE 89 • • • Mallika Verma . XRI. Z . but the Carry and Auxiliary Carry flags are cleared. d8 Cycle 2 T state 7 Address register Flags S. The Exclusive Or function occurs on a bit-by-bit basis exactly as outlined above.LOGICAL GROUP EXCLUSIVE OR IMMEDIATE: • The XRI d8 instruction allows the programmer to perform an Exclusive Or between a mask byte stored as the second byte of the instruction and the contents of the accumulator. The first byte must be loaded into the A register prior to the execution of the instruction.
COMPARE INSTRUCTIONS COMPARE INSTRUCTIONS: • • • • The CMP r and CMP M instructions compare the contents of the specified byte. and are set to indicate the conditions of the lost answer. to the contents of the accumulator. and the actual answer of subtraction is lost. either in a register or in the address contained in the H&L registers. This is accomplished by subtracting the byte in the register/ memory from the contents of the accumulator. If A < reg/mem Cy flag is set If A = reg/mem Zero flag is set If A > reg/mem CY and Zero flags are reset 90 . The contents of the accumulator remain unchanged. The condition flags are all affected.
2 T state 4. AC .Compare Instructions CMP r. CMP M Cycle 1. P are also modified in addition to CY and Zero Hex Code B B8 C B9 D E H L M A BF BA BB BC BD BE 91 . 7 Address register Flags S.
The contents of the A register are left unchanged. P are modified in addition to CY and Z Hex Code FE 92 . d8 Cycle 2 T state 7 Address register Flags S. as described above.COMPARE INSTRUCTIONS: COMPARE IMMEDIATE: The CPI d8 instruction compares the contents of the accumulator to a fixed value provided by the second byte of the instruction. Z . The function occurs by a subtraction with lost answer. CPI. The first value must be loaded into the A register prior to the execution of the instruction.
respectively. • In the RLC. It is also moved to the Carry flag. 93 . Only the Carry flag is affected by these instructions. It is also moved to the Carry flag. • Thus. • In the RRC. all the bits move one position to the right. the bit shifted out of the low order position of the A register is moved around to the high order position. all the bits move one position to the left. the high order bit which is shifted out of the A register is moved around to the low order bit position. the Carry flag in either case indicates whether a bit was shifted out of the accumulator.ROTATE INSTRUCTIONS: • The Rotate Left (RLC) and Rotate Right (RRC) instructions rotate the accumulator’s contents one bit position left or right.
In the RAR. the low order bit is moved to the Carry flag. however. the bits in the A register are shifted right one position.ROTATE INSTRUCTIONS ROTATE THROUGH CARRYS: The RAL and the RAR instructions rotate the accumulator’s contents one bit position left or right. these instructions use the Carry flag as a ninth bit in the circle. In the RAL. Unlike the rotates above. the bits in the A register are shifted left one position. the high order bit moved to the Carry flag. the Carry flag is moved to the high order position of the A register. the Carry flag contents is moved to the low order position of the A register. respectively. Only the Carry flag is affected. 94 .
RAL. RRC. RAR Cycle 1 T state 4 Flags CY HEX Codes RLC 07 RRC 0F RAL 17 RRC 1F 95 .ROTATE INSTRUCTIONS RLC.
ROTATE INSTRUCTIONS RAL instruction CY RAR Instruction CY D7 D0 D7 D0 RLC Instruction CY RRC Instruction CY D7 D0 D7 D0 96 .
depending upon its initial condition. • The CMC will change the flag from 1 to 0. or 0 to 1.TEST INSTRUCTIONS COMPLEMENT ACCUMULATOR: • • The Complement Accumulator (CMA) instruction provides a 1’s complement of the 8 bits in the A register No condition flags are affected. • No other flags are affected. regardless of its previous state. • The STC forces the flag to a 1. CARRY INSTRUCTIONS: • The Complement Carry (CMC) and Set Carry (STC) instructions allow direct control of the Carry flag by the programmer. CMA 07 CMC 0F STC 17 97 .
which provides linking. • The first type is the Jump. to save the address of the next instruction following the Call. proceed to a subordinate routine. • There are two major types of these instructions in the 8085.Branch Instructions • This group of instructions permits the programmer to alter the flow of program execution from a normal straight line. in which the flow is altered with no intention of returning to the place where the Jump occurred. and return to the saved address when that routine is completed. via the system stack. • The second type is the Call. Mallika Verma 98 .
Branch Instructions Jumps and Calls may be conditional or unconditional • An unconditional Jump or Call causes the function to be executed absolutely. three bits labeled XXX will contain a code which specifies the conditions to be tested. These may be specified by the programmer in assembly language by putting together a mnemonic composed of a J. followed by one or two more characters which specify the conditions to be tested. or a C. The breakdown follows: 99 . In the first byte of these instructions. for Jump. • The conditional Jump or Call causes the function to be executed if the conditions specified are met. for Call.
The next instruction to be fetched. program flow remains in a straight line. • The JXX instruction will alter program flow if the conditions specified by the “XX" bits are true. • No condition codes are affected. therefore. will the first of the new routine. • The JMP instruction is unconditional. 100 . otherwise. the Jump occurs absolutely.Jump Instructions JUMP INSTRUCTIONS: • The Jump (JMP addr16) and Jump Conditional (JXX addr16) instructions allow program flow to be altered by loading the contents of the two bytes following the instruction to be loaded into the Program Counter.
a16 JC. a16 Opcode C2 a16 CA a16 D2 a16 DAa16 E2 a16 EA a16 F2 a16 FA a16 Flag Z=0 Z=1 CY = 0 CY =1 P=0 P=1 S=0 S=1 101 . a16 JM. a16 JNC. a16 JPO.No. a16 JZ.JUMP INSTRUCTIONS Conditions attached with Jump Unconditional Jump JMP addr 16 Cycle 3 T state 10 Address Immediate Flags none Hex Code C3 Conditional Jump JXX addr 16 Cycle 3 T state 10 Address Immediate Flags none S. 1 2 3 4 5 6 7 8 Condition JNZ. a16 JPE. a16 JP.
and the address of the first instruction of the subroutine is fetched next. 2. Thus. 102 . The SP is then decremented by two. and the low byte of the PC into the address below that. providing that the conditions specified by the XX bits are true. The Call Conditional executes exactly the same way. TWO STEPS 1.The Call will move the high byte of the PC into the address pointed to by the Stack Pointer minus 1. with the address of the next sequential instruction saved for later ref. None of the flags are affected. the address of the instruction following the Call is saved on the system stack. and the third byte of the instruction containing the high order byte of the address. to update it to the new stack position. with the second byte of the instruction containing the low order byte of the address.Subroutine Instructions CALL INSTRUCTIONS: The CALL addr16 and the conditional CXX addr16 instructions allow a subroutine to be invoked.The two bytes following the Call instruction will then be moved to the PC.
Unconditional Call CALL addr 16 Cycle 5 T state 18 Address Imm/reg indirect Flags none Hex Code CD Conditional Call CXX addr 16 Cycle 5 T state 18 Address Imm/reg indirect Flags none Conditions attached with Call S.No. 1 2 3 4 5 6 7 8 Condition CNZ, a16 CZ, a16 CNC, a16 CC, a16 CPO, a16 CPE, a16 CP, a16 CM, a16 Opcode C4 a16 CC a16 D4 a16 DCa16 E4 a16 EC a16 F4 a16 FC a16 Flag Z=0 Z=1 CY = 0 CY =1 P=0 P=1 S=0 S=1
RETURN INSTRUCTIONS: The RET and Return Conditional (RXX) instructions provide a means, at the end of a subroutine, of resuming program execution at the instruction following the Call instruction which invoked the subroutine. These instructions are placed at the end of the subroutine, not in the body of the main program. When encountered, the Return will move the byte pointed to by the Stack Pointer into the lower byte of the PC, the next byte higher in RAM to the higher byte of PC, and add 2 to the contents of SP. Thus, the address of the instruction following the Call, previously saved on the stack, is now in PC, and will be fetched next. The Return Conditional executes exactly the same way, providing that the conditions specified by the XX bits are true. The stack pointer is updated accordingly. None of the flags are affected.
Unconditional RET RET Cycle 3 T state 10 Address reg indirect Flags none 1 Byte Hex Code C9 Conditional Return RXX Cycle 3 T state 12 Address reg indirect Flags none 1 Byte Conditions attached with Return S.No. 1 2 3 4 5 6 7 8 Condition RNZ, a16 RZ, a16 RNC, a16 RC, a16 RPO, a16 RPE, a16 RP, a16 RM, a16 Opcode C0 a16 C8 a16 D0 a16 D8a16 E0 a16 E8 a16 F0 a16 F8 a16 Flag Z=0 Z=1 CY = 0 CY =1 P=0 P=1 S=0 S=1
PCHL Cycle 1 T state 6 Address register Flags none 1 Byte Hex Code E9 106 . and may be assembled by other parts of the program to the advantage of the programmer. The original contents of the PC are destroyed.JUMP INDIRECT INSTRUCTIONS The Jump H&L Indirect instruction • • • PCHL moves the contents of the H&L registers into the Program Counter The contents of H&L must be previously built. so this is a one-way jump.
¾ as many as eight different external events i. and then jump to any one of eight different locations in low core. may ask for service. 107 .. depending upon the contents of the bits marked n in the instruction. I/O devices.RESTART INSTRUCTIONS The RST n instruction • Are special unconditional call instructions • One byte instructions • Are software interrupts • provides part of the vectored interrupt system by which any one of eight different levels of interrupt may stop the execution of the program currently in progress by ¾ saving the address of the next instruction onto the stack. etc.e.
Software Interrupts S.No. 1 RST n Cycle 3 T state 12 Address reg indirect Flags none One byte 1 Byte 2 3 4 5 6 7 8 Instruction RST 0 RST 1 RST 2 RST 3 RST 4 RST 5 RST 6 RST 7 Opcode C7 CF D7 DF E7 EF F7 FF The default interrupt for the µP in the Lab is RST 5 (EF) 108 .
and update the SP. • The Pop instruction will return the last two items on the stack to the specified register pair. • The condition flags are not affected. PUSH AND POP: • Push Register Pair (PUSH rp) and Pop Register Pair (POP rp) allow programmers to manipulate the system stack. • The SP register pair may not be specified. and update the SP accordingly. DE. or provide utilities. • The Push will place the contents of the BC. or HL register pairs onto the stack. 109 .MACHINE CONTROL GROUP This group is a collection of miscellaneous instructions which control bodily functions of the µP.
STACK Instructions PUSH rp SP-1 ↔ rh SP -2 ↔ rl SP ↔ SP-2 Cycle 3 T state 12 Address reg indirect Flags none One byte LXI SP a16 is always before PUSH Data transfer instruction PUSH B C5 PUSH D D5 PUSH H E5 POP rp rl ↔ SP rh ↔ SP +1 SP ↔ SP+2 Cycle 3 T state 10 Address reg indirect Flags none One byte Data transfer instruction POP B C1 POP D D1 POP H E1 110 .
followed by the Flag byte. •When the POP is executed. •The SP is then updated. •When the PUSH PSW is encountered.Processor Word Instructions PSW INSTRUCTIONS: PUSH PSW and the POP PSW instructions will allow the programmer to save the contents of the A register and of the condition flags on the stack. 111 . •The A register is then loaded with the next byte retrieved. This allows programmers to save conditions at the beginning of subroutines so that the execution of the instructions within the routines will not alter the conditions under which the original program was operating. and the bits are loaded into their proper flip-flops. The Processor Status Word (PSW) of the 8085 is defined as a "Flag Byte" which contains the condition flag bits in a specific sequence: S Z X AC X P X CY The contents of the A register is also saved as part of the PSW. the Flag byte is retrieved first. or to retrieve them from the stack. the contents of the A register is pushed onto the stack first.
S. AC One byte Data transfer instruction Opcode E1 POP PSW 112 . P.PUSH and POP PSW PUSH PSW SP-1 ↔ A SP -2 ↔ Flag Content SP ↔ SP-2 Cycle 3 T state 12 Address reg indirect Flags none One byte LXI SP a16 is always before PUSH Data transfer instruction Opcode F5 Flag content ↔ SP A ↔ SP +1 SP ↔ SP+2 Cycle 3 T state 10 Address reg indirect Flags Z. CY.
the stack receives the original contents of H&L. XTHL L ↔ SP H ↔ SP +1 Cycles 5 T state 16 Address reg indirect Flags none Opcode E3 113 . while H&L receives the two bytes from the stack. • The contents of SP remain unchanged.Stack Exchange Instructions EXCHANGE STACK TOP with H&L (XTHL) instruction • causes the contents of the H&L registers to be exchanged with the two bytes which are currently on the top of the system stack. • It is a two-way instruction. • These will be the last two bytes pushed. • No flags are affected.
Stack Exchange Instructions MOVE H&L TO SP: SPHL instruction • Will directly move the contents of the H&L registers into the Stack Pointer • the original contents of SP are destroyed. SPHL SP ↔HL Cycle 1 T state 6 Address register Flags none One byte Opcode E1 114 . • This may be used to permit multiple stacks to exist at one time in the system. • No flags are affected.
I/O INSTRUCTIONS • The IN port and OUT port instructions allow the µP to communicate with the outside world. • No flags are affected. • In both cases. • These are two byte instructions 115 . • In the case of IN. the address byte of the device to be used is contained in the byte following the instruction. the byte to be sent on the data lines is placed in the A register prior to execution of the instruction. the byte accepted on the D0-D7 data lines by the µP is placed in the A register. • For the OUT. • This byte is presented at once to both the upper and lower bytes of the A0-A15 address lines.
I/O INSTRUCTIONS IN Port (8bit address) Cycle 3 T state 10 Address Direct Flags none Two byte Op code DB port OUT Port (8 bit address0 Cycle 3 T state 10 Address Direct Flags none Two byte Op code D3 Port 116 .
Enable or Disable all interrupts except TRAP 117 . • No flags are affected. •For the DI. the interrupts will be enabled following the completion of the next instruction following the EI. perhaps a RET or JMP. to be executed before the µP allows itself to again be interrupted. •This allows at least one more instruction. the interrupts are disabled immediately.INTERRUPT CONTROL INSTRUCTIONS Enable Interrupts (EI) and Disable Interrupts (DI) instructions allow the µP to permit or deny interrupts under program control •For the EI.
INTERRUPT CONTROL INSTRUCTIONS HALT and NO-OP: The Halt (HLT) and No-Operation (NOP) instructions serve general utility purposes The Halt will stop the processor from further execution. It is used primarily as a programmer’s aid in saving space within language programs for later use. from a Halt. as the result of another device wanting the bus. it can be restarted again only by an interrupt. 118 . but will return to the Halt state when the Hold is canceled. The NOP is simply a one-byte long place holder. The µP may enter a Hold state. A reset signal applied to the µP will abort the Halt. which is passed through automatically without any data motion or action of any kind.
Halt and NOP EI and DI Cycle 1 T state 4 Flags none One byte Op code FB. F3 HLT Cycle 1 T state 5 Flags none One byte Op code 76 NOP Cycle 1 T state 4 Flags none One byte Op code 00 Machine Control Group 119 .
they are not electrically or logically related.RIM and SIM Instructions The Read Interrupt Mask (RIM) and Set Interrupt Mask (SIM) instructions are used to service both the extended interrupt system of the ‘85 and the Serial Input Data (SID) and Serial Output Data (SOD) pins on the device. While these items are both serviced by the same instructions. and should not be confused 120 .
5 M6.RIM Instructions READ INTERRUPT MASK (RIM) • This instruction permits the system to examine the interrupt mask by loading into the A register a byte which defines the condition of the mask bits • For the mask able interrupts. the condition of the interrupts pending for the mask able interrupts.5 D4 I5.5 D5 I6. and the condition of the Serial Input Data (SID) pin on the µP The format of the Accumulator is D7 SID D6 I7. the condition of the Interrupt Enable flag. 121 . SIM instructions via the accumulator.5 D3 IE D2 D1 D0 M7.5 The Interrupt Mask is a group of bits which can be accessed by RIM.5 M5.
5 are masked on or off.5.5 D5 I6.Read Interrupt Mask D7 SID D6 I7. INTERRUPT ENABLE BIT D3: This bit corresponds to the Interrupts Enabled. It is set or reset by the Enable Interrupts or Disable Interrupts OP codes • 122 . D2: These bits indicate whether the interrupts for 5. the purpose of these bits are as follows: • INTERRUPT MASK BITS D0.5 D3 IE D2 M7.5.5 M5. and 0 for enabled. D1. and 7. 6.5 D1 D0 M6. It is a valuable tool. since one program section may not necessarily know what a second section is doing or expecting.5 From the D0 end of the byte. The bits are set to a 1 for disabled.5 D4 I5.
123 .5 D3 IE D2 M7. If interrupts 5. which corresponds to the 7.5 or 6. D6: These bits indicate what interrupts have occurred since the last time that specific interrupt was serviced. Bit D6. and 0 if it is low. The software examining this bit must have total ability to deal with whatever it finds there. D5.5 D4 I5.5 interrupt. •SERIAL INPUT DATA BIT D7: This bit provides the condition of the SID pin.5 D5 I6.5 are masked off by bits D0 or D1.5 •INTERRUPTS PENDING BITS D4.5 D0 M5.5 D1 M6. will be set on to indicate that an interrupt was requested. It will be 1 if the pin is high.Read Interrupt Mask D7 SID D6 I7. even if it was masked off. bits D4 and D5 will not be set.
Read Interrupt Mask
When the RIM instruction is executed, the status of all the lines indicated are sampled, and the resulting bit pattern is placed in the A register. The instruction simply provides these conditions for display; it has no affect on the bits themselves. The bits in the A register may then be examined directly by logical instructions, or moved to a register or memory location for safekeeping. RIM Cycle 1 T state 4 Flags none One byte Op code 20H
SET INTERRUPT MASK (SIM) • This instruction is the reverse of the RIM • While the RIM simply reads the status of various lines, the SIM sets various bits to form masks or generate output data via the SOD line. • The conditions that the programmer wishes to set up must be set into the A register exactly as desired first, then the SIM Instruction is executed. • The SIM will take the bit pattern it finds in the A register and loads it into the masks in the following format: D7 D6 D5 X D4 7.5 D3 D2 D1 D0
MSE M7.5 M6.5 M5.5
Set Interrupt Mask
D7 SOD D6 SOE D5 X D4 7.5 D3 MSE D2 D1 D0
M7.5 M6.5 M5.5
RST MASKS BITS D0, D1, D2: These bits are the interrupt masks for the 5.5, 6.5, and 7.5 interrupts brought into the ‘85 on their own pins. The bits are 0 to enable and 1 to disable the interrupts. If bits D0 or D1 are disabled (set to 1), a signal applied to their respective pins cause no action. If D0 or D1 are set to 0 (enabled), their respective bits will be visible via the RIM instruction, and the call to the interrupt vector will occur. In the case of bit D2 for masking the 7.5 interrupt, the RIM instruction will indicate that a 7.5 interrupt is pending, but an automatic call will not occur.
This permits accessing of the mask byte to deal with the interrupts without affecting SOD. If a SIM is executed with this bit set high. 127 .5 M5.5 D3 MSE D2 D1 D0 M7. the mask bits will take on the same arrangement as those given in the lower bits of the A register. If a SIM is executed with this bit low.5 M6.Set Interrupt Mask D7 SOD D6 SOE D5 X D4 7. and D2 to be changed.5 MASK SET ENABLE BIT D3: This bit permits bits D0. D1. the condition of the mask bits will not change.
5 and 6.5 RESET BIT D4: This bit permits the SIM instruction to reset the interrupt pending flag indicated by bit D6 in the RIM instruction byte.Set Interrupt Mask D7 SOD D6 SOE D5 X D4 7. 128 • .5 • RST 7. This bit allows that pending request to be reset individually under program control.5.5 D3 MSE D2 M7.5 D0 M5.5 D1 M6. Since the 7. it can indicate that it is pending via the RIM instruction even though it is masked off.5 interrupt is handled somewhat more importantly than the 5. UNDEFINED BIT D5: This bit is unused.
5 D0 M5. SERIAL OUTPUT DATA BIT D7: This bit contains the voltage level (+5 volts = 1. and in turn appears on the SOD pin of the ‘85. which will in turn cause it to appear on the SOD pin. If the SIM instruction is executed and bit D6 is set to 1 (enabled).Set Interrupt Mask D7 SOD • D6 SOE D5 X D4 7.5 • SOD ENABLE BIT D6: This bit works in conjunction with bit D7. the condition of bit D7. 0 volts = 0) which should appear at the SOD pin of the ‘85. If bit D6 is low. the SIM instruction will have no affect on bit D7. This. If bit D6 is low. If it is set to 1 when the SIM is executed. high or low. like bit D3. the SIM’s execution has no affect on the bit D7. allows executing SIMs to service either interrupts or the serial I/O without affecting the other. is electrically loaded into the SOD latch. 129 .5 D3 MSE D2 M7. the level contained by D7 is forwarded to the SOD latch.5 D1 M6.
Next.5 latch which catches the rising edge of the 7. which will disable all interrupts. These will effectively allow the new instructions following the Reset to take full control of the µP .5 flip-flop and holds it till RIM instruction is reset. the RST 7. Lastly. without interrupts causing immediate problems. all three mask bits are set to a 1. First. 130 .Set Interrupt Mask SIM Cycle 1 T state 4 Flags none One byte Op code 30 The RESET IN line affects the flags of the interrupt masks. the SOD latch is reset to a 0.
or the arrangement of the condition flags. The PC was reset to all zeroes during the Reset cycle. therefore. 131 . a Reset switch of some kind accessible to the operator. At the beginning of the state following the latch of /RESET IN. • When the /RESET IN line goes high.ADDITIONAL INFORMATION RESET SYSTEM • The 8085 generates its own Reset function upon receipt of an asynchronous /RESET IN signal from an external source. the µP will place the contents of the PC onto the address bus. and a Power-on Reset circuit which causes a reset when power is applied to system. • The Reset cycle does not affect the contents of any register except PC. • The results of a Reset are undetermined. and enter T1 of the M1 cycle for the next instruction. • The Intel documentation indicates that the occurrence of Reset is essentially asynchronous with respect to the execution of the program in process. • This signal is probably generated from two sources. • Receipt of /RESET IN is latched by an internal flip-flop at the rising edge of the next clock pulse (low asserted). and not guaranteed. RESET OUT is generated to the outside world. and the µP enters T-reset cycles. the address appearing on the A0-A15 lines will be 0000H.
5 FF • Trap FF • SOD FF The following items are turned on. by the Reset cycle: • RST 5.5 Mask • RST 6.5 Mask 132 . or set. or turn off. the following items: • Program Counter • Instruction Register • Interrupt Enable FF • RST 7.Reset Cycle The Reset cycle will reset.5 Mask • RST 7.
INTERRUPT FACILITIES The functional items required are an Interrupt Request (INTR) pin. an Interrupt Acknowledge (INTA) pin. eight interrupt vectors. and the Restart instruction 133 . an Interrupt Enable (INTE) pin.
and these bytes can tailor its operation to a variety of conditions. and the ports may be used for input. one 6-bit wide parallel port and an interval timer. The device accepts standard 8085 electrical interface lines and operates on a single 5 volt supply. or both. many Intel and non-Intel RAMs and ROMs have been developed to provide data storage to meet every conceivable need. and two 8-bit-wide bi-directional parallel I/O ports. The timer is programmable. It requires initialization bytes to be sent to it before it can perform. It requires a single 5 volt supply In addition to these devices above. and is cascadable to a total of 64 interrupts by adding additional 8259’s to each of the first one’s input lines. output. and a 5 volt supply. two 8-bit wide parallel ports. includes 256 bytes of RAM. 134 . It uses the 8085 electrical interface.SUPPORT DEVICES FOR THE 8085 8155 : This device provides several items of general use for a small ‘85-based control environment. 8255: 8755 EPROM WITH I/O: This device provides 2Ks worth of 8-bit bytes of UV-erasable EPROM. 8259 Programmable interrupt controller: It handles 8 vectored interrupts by itself.
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