Microcontrollers

Serial Communication

Objectives
• To study the serial communication protocol RS-232 • To enable serial communication using the USART of PIC16F877

Contents
• • • • • Serial port Protocol RS-232 Speed generator Asynchronous transmitter Asynchronous receiver

Contents • • • • • Serial port Protocol RS-232 Speed generator Asynchronous transmitter Asynchronous receiver .

a PC provides serial ports (COM1. COM2.) and a DB-9 connector . etc.Serial Port • Serial communication is one of the traditional protocols that enables the communication between a PC and a microcontroller • To that purpose.

Serial Port • On the PIC side. the serial communication is handled by an USART (Universal Synchronous Asynchronous Transmitter Receiver) • Two pins of the PIC are used by the USART .

Contents • • • • • Serial port Protocol RS-232 Speed generator Asynchronous transmitter Asynchronous receiver .

RS-232 Protocol • The communication is organized in negative-logic packets • A start bit (START) • Eight or nine data bits (8-bit data plus 1 parity bit) • One or two bits for end of communication (STOP) • When a line of communication is not being driven. it is on a high state (idle state) • A negative transition from the idle state represents the START command .

the so-called bauds (bits per second) • Typical communication speed rates are 1200. etc.RS-232 Protocol • The duration of each bit is related to the communication speed. given in seconds: for a 9600 bauds communication speed rate the duration of each bit is approximately 104μs . 9600 bauds. 2400. • The reciprocal of the communication speed rate is the duration of each bit.

Voltage-Level Matching • The matching of the voltage levels between the protocol and TTL is made by the MAX232 integrated circuit .

Voltage-Level Matching • The operation of the MAX232 is shown below .

only one of the two modes is available during the communication • The rest of the presentation is devoted to asynchronous communication only . the USART and the PC can operate both as a transmitter and as a receiver • When synchronous.USART • This is the peripheral that implements a serial communication with a PC by using the RS232 protocol • The USART supports both synchronous and asynchronous communications • When asynchronous.

USART • The pins of PIC16F that are used for communication by the USART are RC6/TX for transmission and RC7/RX for reception • Both pins are to be defined as input pins using TRISC • The USART is switched on by setting bit 7 of register RCSTA .

Contents • • • • • Serial port Protocol RS-232 Speed generator Asynchronous transmitter Asynchronous receiver .

Baud Rate Generator • The communication speed rate is determined by the Baud Rate Generator (BRG) • The BRG can operate in two operating modes: high and low speed • The selection of the operating mode is made via register TXSTA (bank 1) .

Baud Rate Generator The SPBRG register establishes the communication rate by adjusting the period of an 8-bit count in accordance with the equation below The high-speed mode reduces the error when defining the speed rate in the SPBRG register .

Asynchronous Mode • In this operating mode the protocol has the following features • • • • One START bit that indicates the start of the communication 8-bit data One parity bit (optional) One STOP bit that indicates the end of the communication • Transmission and reception of the 8-bit data start with the LSB • Transmitter and receiver rates are under control of BRG .

Contents • • • • • Serial port Protocol RS-232 Speed generator Asynchronous transmitter Asynchronous receiver .

Asynchronous Transmitter • The structure of TX along with the corresponding configuration bits are shown below • TXREG stores the data to be transmitted • TSR is a shift register • BRG generates the clock pulses for the shift operation .

Asynchronous Transmitter • The operation of TX is configured by register TXSTA .

Asynchronous Transmitter: Initialization • Contents of SPBRG is updated according to the selected communication rated • Asynchronous mode is selected (bit 4 of TXSTA) and the serial module is switched on (bit 7 of RCSTA is set to one) • TX interrupt is enabled (optional) • 9-bit data communication is set (optional) • Transmission data is loaded in TXREG • Transmitter is switched on by setting bit TXEN of TXSTA to one .

Asynchronous Transmitter: Interrupt • Bits GIE and PEIE of INTCON are set to one • TX interrupt is enabled by setting bit 4 of PIE1 to one • TX interrupt flag bit is bit 4 of PIR1 .

their operation is shown below .Asynchronous Transmitter: Operation • TXIF interrupt flag is set (generating an interrupt) one instruction cycle after a parallel load from TXREG to TSR • TXIF can only be cleared by loading a new data in TXREG • TMRT bit (bit 1 of TXSTA) is set (no interrupt involved) once TSR has been emptied and is cleared when a new data is loaded in TSR • TXIF and TMRT are read-only bits.

Contents • • • • • Serial port Protocol RS-232 Speed generator Asynchronous transmitter Asynchronous receiver .

Asynchronous Receiver • The internal structure of RX is shown along with the configuration bits • RSR is a shift register and a two-level FIFO is used to stored up to two received data .

Asynchronous Receiver • The operation of RX is configured by register RCSTA .

Asynchronous Receiver: Initialization • Contents of SPBRG is updated according to the selected communication speed rate • Asynchronous mode is selected (bit 4 of TXSTA) and the serial module is switched on (bit 7 of RCSTA) • RX interrupt is enabled (optional) • 9-bit data communication is set (optional) • Receiver is switched on by setting bit CREN of RCSTA to one .

Asynchronous Receiver: Interrupt • Bits GIE and PEIE of INTCON are set to one • RX interrupt is enabled by setting bit 5 of PIE1 to one • RX interrupt flag bit is bit 5 of PIR1 .

Asynchronous Receiver: Operation • The received data is stored in RSR (shift register) • Upon reception of the STOP bit a parallel loading from RSR to RCREG takes place and an interrupt is generated (if enabled) • RCIF flag bit is cleared once RCREG contents has been read • Because RCREG is part of a two-level FIFO. up to two 8-bit data can be read simultaneously .

FERR. is set when the STOP bit is received as a zero instead of one. this third received data is discarded and RX is disabled • OERR must be cleared for RX to continue operating. FERR must be read before reading the contents of RCREG. to detect this error.Asynchronous Receiver: Errors • Overrun Error bit. is set when the FIFO is full and a third received data is loaded. OERR is cleared by clearing bit CREN and then setting it (resetting RX) • Framing Error bit. at the end of communication . OERR.

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