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Objective: To get familiar with development simulator EdSim 51 Theory:Program Status Word: The Program Status Word (PSW)

contains several status bits that reflect the current state of the CPU. The PSW resides in SFR space. It contains the Carry bit, the Auxiliary Carry (for BCD operations), the two register bank select bits, the Overflow flag, a parity bit, and two user-definable status flags. Stack Pointer: The Stack Pointer register is 8 bits wide. It is incremented before data is stored during PUSH and CALL executions. While the stack may reside anywhere in on-chip RAM, the Stack Pointer is initialized to 07H after a reset. This causes the stack to begin at location 08H. Data Pointer: The Data Pointer (DPTR) consists of a high byte (DPH) and a low byte (DPL). Its intended function is to hold a 16-bit address. It may be manipulated as a 16-bit register or as two independent 8-bit registers. Ports 0 to 3: P0, P1, P2 and P3 are the SFR latches of Ports 0, 1, 2 and 3, respectively. Serial Data Buffer: The Serial Data Buffer is actually two separate registers, a transmit buffer and a receive buffer register. When data is moved to SBUF, it goes to the transmit buffer where it is held for serial transmission. (Moving a byte to SBUF is what initiates the transmission.) When data is moved from SBUF, it comes from the receive buffer.

Table 1.3

Timer Registers: Register pairs (TH0, TL0), (TH1, TL1), and (TH2, TL2) are the 16-bit counting registers for Timer/Counters 0, 1, and 2, respectively. Capture Registers: The register pair (RCAP2H, RCAP2L) is the capture register for the Timer 2 capture mode. In this mode, in response to a transition at the 80C52s T2EX pin, TH2 and TL2 are copied into RCAP2H and RCAP2L. Timer 2 also has a 16-bit auto-reload mode, and RCAP2H and RCAP2L hold the reload value for this mode. Control Registers: Special Function Registers IP, IE, TMOD, TCON, T2CON, SCON, and PCON contain control and status bits for the interrupt system, the timer/counters, and the serial port. Addressing Modes: 1. Direct Addressing: In direct addressing the operand is specified by an 8-bit address field in the instruction. Only 128 Lowest bytes of internal Data RAM and SFRs can be directly addressed. 2. Indirect Addressing: In indirect addressing the instruction specifies a register which contains the address of the operand. Both internal and external RAM can be indirectly addressed. The address register for 8-bit addresses can be R0 or R1 of the selected register bank, or the Stack Pointer. The address register for 16-bit addresses can only be the 16-bit data pointer register, DPTR. 3. Register Instructions: The register banks, containing registers R0 through R7, can be accessed by certain instructions which carry a 3-bit register specification within the opcode of the instruction. Instructions that access the registers this way are code efficient, since this mode eliminates an address byte. When the instruction is executed, one of the eight registers in the selected bank is accessed. One of four banks is selected at execution time by the two bank select bits in the PSW. 4. Register-specific Instructions: Some instructions are specific to a certain register. For example, some instructions always operate on the Accumulator, or Data Pointer, etc., so no address byte is needed to point to it. The opcode does this itself. Instructions that refer to the Accumulator as A assemble as accumulator-specific opcodes.

5. Immediate Constants: The value of a constant can follow the opcode in Program Memory. For example; MOV A, # 100 Loads the Accumulator with the decimal number 100. The same number could be specified in hex digits as 64H. 6. Indexed Addressing: Only Program Memory can be accessed with indexed addressing, and it can only be read. This addressing mode is intended for reading look-up tables in Program Memory. A 16-bit base register (either DPTR or the Program Counter) points to the base of the table, and the Accumulator is set up with the table entry number. The address of the table entry in Program Memory is formed by adding the Accumulator data to the base pointer. Another type of indexed addressing is used in the case jump instruction. In this case the destination address of a jump instruction is computed as the sum of the base pointer and the Accumulator data.

Table 1.4 Timer/Counters: The Atmel 80C51 Microcontrollers implement two general purpose, 16-bit timers/ counters. They are identified as Timer 0 and Timer 1, and can be independently configured to operate in a variety of modes as a timer or as an event counter. Timer/Counter Operations: A basic operation consists of timer registers THx and TLx (x= 0, 1) connected in cascade to form a 16-bit timer. Setting the run control bit (TRx) in TCON register (see Figure 2-3) turns the timer on by allowing the selected input to increment TLx. When TLx overflows it increments THx; when THx overflows it sets the timer overflow flag

(TFx) in TCON register. Setting the TRx does not clear the THx and TLx timer registers. Timer registers can be accessed to obtain the current count or to enter preset values. They can be read at any time but TRx bit must be cleared to preset their values, otherwise the behavior of the timer/counter is unpredictable. For timer operation (C/Tx# = 0), the timer register counts the divided-down peripheral clock. The timer register is incremented once every peripheral cycle (6 peripheral clock periods). The timer clock rate is FPER / 6, i.e. FOSC / 12 in standard mode or FOSC / 6 in X2 mode. For counter operation (C/Tx# = 1), the timer register counts the negative transitions on the Tx external input pin.

Table 1.5 In addition to the timer or counter selection, Timer 0 and Timer 1 have four operating modes from which to select which are selected by bit-pairs (M1, M0) in TMOD. Modes 0, 1, and 2 are the same for both timer/counters. Mode 3 is different. The four operating modes are described below. Timer 2 has three modes of operation: capture, auto-reload and baud rate generator.

Mode 0 (13-bit Timer): Mode 0 configures timer 0 as a 13-bit timer which is set up as an 8-bit timer (TH0 register) with a modulo 32 prescaler implemented with the lower five bits of the TL0 register

Fig. 1.3 The upper three bits of TL0 register are indeterminate and should be ignored. Prescaler overflow increments the TH0 register. Mode 1 (16-bit Timer): Mode 1 is the same as Mode 0, except that the Timer register is being run with all 16 bits. Mode 1 configures timer 0 as a 16-bit timer with the TH0 and TL0 registers connected in cascade

Fig. 1.4

Table 1.6

Fig 1.5 Mode 2 (8-bit Timer with Auto-Reload): Mode 2 configures timer 0 as an 8-bit timer (TL0 register) that automatically reloads from the TH0 register

Mode 3 (Two 8-bit Timers): Mode 3 configures timer 0 so that registers TL0 and TH0 operate as separate 8-bit timers