(5)
( ) F s is the transfer function of the loop filter, as for 3order
LL, F(s) is a 2order low pass filter; the tra
s follow:
P nsfer function is
a
2
( )
n n
2 2
n n
2
s +2
w s w
F s
w s w
c
c
+
=
+
(6)
Take ( ) F s ( ) C s : to
( )
3 2 2 2
n
s Kw +
n n n
2
n n
s +2 2
( )
(2 )
w s w K w
C s
K w s w
c c
c
+ +
=
+
(7)
e data assed rough the shaping filter getting the
ideal phase modulation signal
Th p th
( ) s u
istortio
, then handled by
ompensation filter being pred n which ou
com
c tput the
pensated phase ( )
comp
s u :
( ) ( )
comp
s s ( ) C s u = u (8)
It can be noticed that the compensation filter can be
completed by FIR d
filter an IIR filter cascading, the FIR
d IIR filter separately set as followed: filter an
( ) ( )
3 2 2
n n n n
( ) s +2 2
fir
T s w s w K w s Kw c c = + + +
2
(9)
2
n n
( ) 1 (2 )
iir
T s K w s w c = + (10)
According to the inverse Laplace transformation, the
phase si of
t omain
gnal can be expressed as the linear added
he derivativ eal phase signal , the time d
utput phase of FIR part can be expressed as
ord
ation
( )
fir
t
e to id ( ) t
o followed:
( )
2
( ) '''( ) 2 ''( ) 2 '( )
( )
fir n n n
t t w t w K w t
t
c c
= + + +
+
(11)
Then ( )
fir
t go through the 1 er low pass filter
( ) T s and finally get the compensated modul
2
n
Kw
iir
hase p ( )
comp
s u . The diagram of compensation filter is
depicted as Fig. 4:
( ) t
( )
comp
t
( )
fir
t
( ) g t
'''
( ) A t
''
( ) B t
'
( ) C t
( ) D t
2
1
n n
(2 ) K w s w c +
Fig. 4 the diagram of compensation filter
The waveform of compensated phase is shown as Fig. 5.
The compensated phase amount to adding high frequency
signals to the ideal phase signal. The higher the data rate
transmitted, the high frequency signals amplitude rose
much more,
compensate higher for
rem
up
which means the changing rate of the
d phase range should be much more
edying more attenuation of PLL. Phase shifting also
exists to compensate the phase response of PLL.
0 200 400 600 800 1000
10
8
6
4
2
0
2
4
6
8
10
sample point
p
h
a
s
e
s
i
g
n
a
l
modulation phase signal
ideal phase signal
compensated phase signal
Fig. 5 the compensated phase waveform compared with ideal
phase
B. The applicable condition
However there is applicable condition to apply the
compensated filter. Through the filter the changing rate of
the e
dividing ratio which is
sho
modulation fractional frequency
wn as Fig. 6.
According to (10), the amplitude response of ( )
iir
T s can
be expressed as:
( ) ( )
2
4
iir
T 1 2 jx K w x w c = + (12)
n n
phase is raised, leading to the enlargement of th
0 100 200 300 400 500
1
0.8
0.6
0.4
0.2
0
0.2
0.4
0.6
0.8
1
n
f
r
a
c
t
i
o
n
a
l
f
r
e
q
u
e
n
c
y
d
i
v
i
d
i
n
g
r
a
t
i
o
n fractional frequency dividing ratio of sigmadelta modulator modulatia
with compensated
without compensated
Fig. 6 the modulation fractional frequency division ratio
Equation (12) must be less than
2
max
1
n
T Kw =
( )
comp
t
, so the
maximum compensated phase must m t the
relat
ee
ionship as (14):
( ) ( ) ( ) ( )
( )
'
'''
2
''
2
1
n
t
t
Kw
+
Assuming the data rate raised
1 2
comp
n n
t t t
K w w
c c
 
s + +

\ .
+
(13)
M times, and then each
erivate part in (14) will be en because the
time is reduced to
d sample larged
1 M times of th inal: e orig
( ) ( ) ( )
( )
''
max max max
3 '''
max
M
comp
D C B
t M t M t
T T T
' 2
max
A
M t
T
= + +
(14)
+
is the maximum compensated phase of t
a g
max
M
comp
ta rate raisin
he
d M times. According to (1) the average
modulation frequency is enlarged either, and then the
maximum modulation fractional ratio can be obtained:
gnal.
However sigmadelta modulator has a requirement of the
range when it applied to PLL as a fractional
divider. The fundamental component of sigmadelta
mo
2
mod mod
3 4
mod mod
max '
'' '''
M
frac Mfrac M frac
M frac M frac
= +
+ +
(15)
It will be sent to sigmadelta modulator as input si
mod
input frequency
dulator is N bit accumulator, the input fraction has to
convert to N bit binary according to 2
N
F frac ( =
(
, and
then F is accumulated at each sample time, when the
accumulated value is more than 2
N
overflow is happened
and the carry is set to 1. If the input fraction
mod
frac is bigger
than 1, it has to be indicated by N + which
exceeded the N bit accumulators range, the truncation error
would produce wrong frequency dividing ratio causing that
modulation phase can not transmitted correctly S in order
to ensure that the frequency dividing ratio can indicate the
modulation phase correctly, the maximum compensated
modulation fractional ratio
mod
max
M
1 , bit binary
. o
frac shown as (16) must
be less than 1.
IV. SIMULATION
Fig. 7 shows the power m of ideal phase,
compensated phase before an , which
proves being th
spectru
d after PLL separately
ro
ncy
ugh the co of
high freque signal nce the whole
transfer charact
mpensation filter the power
ala is strengthen to b
eristic and enlarge the phase modulation band
effectively.
1.5 1 0.5 0 0.5 1 1.5
x 10
7
100
80
60
40
20
0
s
i
g
n
a
l
p
o
w
e
r
(
d
B
)
ideal phase
1.5 1 0.5 0 0.5 1 1.5
x 10
7
100
80
60
40
20
0
compensated phase
1.5 1 0.5 0 0.5 1 1.5
x 10
7
100
80
60
40
20
0
Frequency(rad/sec)
s
i
g
n
a
l
p
o
w
e
r
(
d
B
)
output of PLL without compensated
1.5 1 0.5 0 0.5 1 1.5
x 10
7
100
80
60
40
20
0
Frequency(rad/sec)
output of PLL with compensated
Fig. 7 power spectrum of the compensated phase compared with
ideal phase before and after PLL
0 500 1000 1500 2000 2500 3000 3500 4000
100
80
60
40
20
0
20
40
60
80
100
with compensated
sample point
p
h
a
s
e
e
r
r
o
r
the phase error between ideal phase and modulated phase by pll
Fig. 8 phase error between ideal phase and PLL output phase
Fig. 7 (a) shows the ideal phase power spectrum, Fig. 7
(c) shows the modulated signal after the ideal phase passing
through PLL, there is obviously power suppression on the
frequency outside the loop band. Besides there is amplitude
overshooting inside the band. Both of them would lead to
phase distortion. Fig. 7 (b) shows the compensated phase
power spectrum, high frequency signal outside the band is
enhanced and part of the signals inside the loop is depressed
to balance the suppression outside the band and the
overshoot inside the band. Fig. 7 (d) is the modulated phase
power spectrum of the PLL output by compensated phase
passing through PLL, there is less distortion compared with
ideal phase signal and is more similar with Fig. 7 (a).
Through the predistortion filter the modulated phase
error is improved greatly. Fig. 8 depicts the phase error
between ideal phase and PLL output phase signal with
co r
rea
mpensated and uncompensated. The maximum phase erro
ched 80ewithout compensated while it is improved to
less than 10eby compensated.
V. CONCLUSION
In this paper a predistortion filter is proposed for the
high data rate phase modulation. By this structure the data
rate limitation is relieved in the PLLbased phase modulator.
Besides the phase modulation error is reduced effectively.
One issue with predistortion filter is that there is a condition
to improve data rate. The data rate can be raised M times
only by the maximum fractional dividing ratio less than 1
after compensated. Using the predistortion filter to improve
the wideband phase modulation, the maximum data rate can
be
This work is supported by the National Natural Science
Foundation of Ch F010501 and by
the
:
ohong Liu, TsungHsien Lin, A Wideband PLLBased G/FSK
Transmitt State Circuits,
vol.44, no.
[5]
(a) (b)
(c) (d)
improved to 2.85Mbit/s with 1MHz PLL cutoff frequency
by the standard of the phase error less than 10e while the
maximum data rate is only 400Kbit/s without predistortion
filter.
VI. ACKNOWLEDGEMENT
ina under Grant 61001032/
Fundamental Research Funds for the Central Universities.
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