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CHAPTER 3
SIGNALS & SYSTEMS
GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia
Published by: NODIA and COMPANY ISBN: 9788192276243
Visit us at: www.nodia.co.in
YEAR 2012 ONE MARK
MCQ 3.1 If x[n] = (1/3) n − (1/2)nu[n], then the region of convergence (ROC) of its
z -transform in the z -plane will be
(A) 3 z
1 < < 3 (B) z 3
1
2
< < 1
(C) 2 z
1 < < 3 (D) z 3
1 <
MCQ 3.2 The unilateral Laplace transform

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ANALOG & DIGITAL ELECTRONICS

YEAR 2012 MCQ 8.1

ONE MARK

In the sum of products function f (X, Y, Z) = (2, 3, 4, 5), the prime implicants are (B) XY, X Y Z , XY Z (A) XY, XY (C) XY Z , XYZ, XY (D) XY Z , XYZ, XY Z , XY Z

/

MCQ 8.2

The i -v characteristics of the diode in the circuit given below are v − 0.7 A, v $ 0.7 V i = * 500 0A v < 0. 7 V

**The current in the circuit is (A) 10 mA (C) 6.67 mA
**

MCQ 8.3

(B) 9.3 mA (D) 6.2 mA

The output Y of a 2-bit comparator is logic 1 whenever the 2-bit input A is greater than the 2-bit input B . The number of combinations for which the output is logic 1, is (A) 4 (B) 6 (C) 8 (D) 10

MCQ 8.4

Consider the given circuit

**GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia
**

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PAGE 420

ANALOG & DIGITAL ELECTRONICS

CHAP 8

In this circuit, the race around (A) does not occur (B) occur when CLK = 0 (C) occur when CLK = 1 and A = B = 1 (D) occur when CLK = 1 and A = B = 0

YEAR 2012 MCQ 8.5 TWO MARKS

The voltage gain Av of the circuit shown below is

(A) Av . 200 (C) Av . 20

MCQ 8.6

(B) Av . 100 (D) Av . 10

The state transition diagram for the logic circuit shown is

**GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia
**

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CHAP 8

ANALOG & DIGITAL ELECTRONICS

PAGE 421

MCQ 8.7

The circuit shown is a

1 rad/s (R1 + R2) C (B) high pass filter with f3dB = 1 rad/s R1 C (C) low pass filter with f3dB = 1 rad/s R1 C 1 (D) high pass filter with f3dB = rad/s (R1 + R2) C (A) low pass filter with f3dB =

YEAR 2011 MCQ 8.8

ONE MARK

A low-pass filter with a cut-off frequency of 30 Hz is cascaded with a high pass filter with a cut-off frequency of 20 Hz. The resultant system of filters will function as (A) an all – pass filter (B) an all – stop filter (C) an band stop (band-reject) filter (D) a band – pass filter

MCQ 8.9

The CORRECT transfer characteristic is

**GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia
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10 The output Y of the logic circuit given below is (A) 1 (C) X (B) 0 (D) X YEAR 2011 MCQ 8.www.nodia. The set of instructions that precede the RET instruction in the subroutine are GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www. h LXI D.com PAGE 422 ANALOG & DIGITAL ELECTRONICS CHAP 8 MCQ 8.in .gatehelp.co.11 TWO MARKS A portion of the main program to call a subroutine SUB in an 8085 environment is given below. DISP LP : CALL SUB LP+3 h It is desired that control be returned to LP+DISP+3 when the RET instruction is executed in the subroutine.

54 mA MCQ 8. then the current through collector will be (A) 168 mA (B) 108 mA (C) 20.7 V.co.13 (D) 5.nodia.12 XTHL INX D (D) INX D INX D XTHL The transistor used in the circuit shown below has a β of 30 and ICBO is negligible If the forward voltage drop of diode is 0.com CHAP 8 ANALOG & DIGITAL ELECTRONICS PAGE 423 POP D (A) DAD H PUSH D POP DAD INX (B) INX INX PUSH H D H H H H POP H (C) DAD D PUSH H MCQ 8.gatehelp.36 mA A two bit counter circuit is shown below It the state QA QB of the counter at the clock time tn is ‘10’ then the state QA QB of the counter at tn + 3 (after three clock cycles) will be (A) 00 (B) 01 (C) 10 Published by: NODIA and COMPANY (D) 11 ISBN: 9788192276243 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Visit us at: www.in .www.

com PAGE 424 ANALOG & DIGITAL ELECTRONICS CHAP 8 MCQ 8.co.in .14 A clipper circuit is shown below.www.7 V. the output voltage vo is GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www.gatehelp.15 ONE MARK Given that the op-amp is ideal. Assuming forward voltage drops of the diodes to be 0. the input-output transfer characteristics of the circuit is YEAR 2010 MCQ 8.nodia.

IC .12 V Assuming that the diodes in the given circuit are ideal. All gates have equal propagation delay of 10 ns. The value of V0 is (A) 4.com CHAP 8 ANALOG & DIGITAL ELECTRONICS PAGE 425 (A) 4 V (C) 7.17 TWO MARKS The transistor circuit shown uses a silicon transistor with VBE = 0.12 V YEAR 2010 MCQ 8.www. the voltage V0 is (A) 4 V (C) 7.23 V The TTL circuit shown in the figure is fed with the waveform X (also shown).65 V (C) 6.in .5 V MCQ 8.5 V (B) 5 V (D) 12.3 V MCQ 8.co.gatehelp. The output Y of the circuit is GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www.18 (B) 5 V (D) 7.nodia. IE and a dc current gain of 100.7.16 (B) 6 V (D) 12.

gatehelp.in .co. PC means Program Counter SP means Stack Pointer (A) (SP) incremented (B) (PC)!Addr (PC)!Addr ((SP))!(PC) (C) (PC)!Addr (SP) incremented ((SP))!(PC) (D) ((SP))!(PC) (SP) incremented ((SP))!(PC) (SP) incremented (PC)!Addr Statement For Linked Answer Questions: 6 & 7 The following Karnaugh map represents a function F . the CPU carries out the following sequential operations internally : Note: (R) means content of register R ((R)) means content of memory location pointed to by R.20 A minimized form of the function F is (A) F = X Y + YZ (C) F = X Y + Y Z (B) F = X Y + YZ (D) F = X Y + Y Z GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www. MCQ 8.www.19 When a “CALL Addr” instruction is executed.nodia.com PAGE 426 ANALOG & DIGITAL ELECTRONICS CHAP 8 MCQ 8.

GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www.21 Which of the following circuits is a realization of the above function F ? YEAR 2009 MCQ 8.gatehelp.nodia.www. The current through the circuit is also shown.in .co.com CHAP 8 ANALOG & DIGITAL ELECTRONICS PAGE 427 MCQ 8.22 ONE MARK The following circuit has a source voltage VS as shown in the graph.

(IV) MCQ 8. NOR and NAND Gates (C) NOR and NAND Gates (D) XOR.in .www. (III).23 The increasing order of speed of data access for the following device is (I) Cache Memory (II) CD-ROM (III) Dynamic RAM (IV) Processor Registers (V) Magnetic Tape (A) (V). (II). (II). (III). (I).nodia. (IV).com PAGE 428 ANALOG & DIGITAL ELECTRONICS CHAP 8 The element connected between a and b could be MCQ 8. (IV) (D) (V). C = 10 μF . (I) (C) (II).24 The nature of feedback in the op-amp circuit shown is (A) Current-Current feedback (C) Current-Voltage feedback MCQ 8. NOR and NAND Gates YEAR 2009 MCQ 8. (I). OR and AND Gates (B) XNOR. (IV).26 TWO MARKS The following circuit has R = 10 kΩ. (III).25 (B) Voltage-Voltage feedback (D) Voltage-Current feedback The complete set of only those Logic Gates designated as Universal Gates is (A) NOT. Under ideal conditions. (V) (B) (V).co. (III). (II).gatehelp. The input voltage is a sinusoidal at 50 Hz with an rms value of 10 V. (I). the current Is from the source is GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www.

in .28 In an 8085 microprocessor. the contents of the Accumulator.nodia.27 (B) 20π mA leading by 90% (D) 10π mA lagging by 90% Transformer and emitter follower can both be used for impedance matching at the output of an audio amplifier.www. The output waveform of this circuit will be GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www.com CHAP 8 ANALOG & DIGITAL ELECTRONICS PAGE 429 (A) 10π mA leading by 90% (C) 10π mA leading by 90% MCQ 8. F0 H SUB B (A) 01 H (B) 0F H (C) F0 H (D) 10 H MCQ 8. The basic relationship between the input power Pin and output power Pout in both the cases is (A) Pin = Pout for both transformer and emitter follower (B) Pin > Pout for both transformer and emitter follower (C) Pin < Pout for transformer and Pin = Pout for emitter follower (D) Pin = Pout for transformer and Pin < Pout for emitter follower MCQ 8.co. after the following instructions are executed will become XRA A MVI B.29 An ideal op-amp circuit and its input wave form as shown in the figures.gatehelp.

the output voltage V0 of the circuit will be GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www. during forward biased and reverse biased conditions. are shown in the figure.nodia.in . (I) (II) If such a diode is used in clipper circuit of figure given above.www.com PAGE 430 ANALOG & DIGITAL ELECTRONICS CHAP 8 YEAR 2008 MCQ 8.30 ONE MARK The equivalent circuits of a diode.co.gatehelp.

32 (B) 3.co. Assuming diodes D1 and D2 to be ideal.in .33 (B) Vc1 = 10 V.Vc2 = 10 V MCQ 8.gatehelp.7 V. the value of current I is (A) 0 mA (C) 4. load resistance to be infinite and initial capacitor voltages to be zero.com CHAP 8 ANALOG & DIGITAL ELECTRONICS PAGE 431 YEAR 2008 MCQ 8.31 TWO MARKS Two perfectly matched silicon transistor are connected as shown in the figure assuming the β of the transistors to be very high and the forward voltage drop in diodes to be 0. the switch ‘S ’ is closed at t = 0 .7 mA In the voltage doubler circuit shown in the figure.6 mA (D) 5.Vc2 =− 5 V (D) Vc1 = 5 V. The steady state voltage across capacitor C1 and C2 will be (A) Vc1 = 10 V. GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www.nodia.Vc2 =− 10 V The block diagrams of two of half wave rectifiers are shown in the figure.Vc2 = 5 V (C) Vc1 = 5 V. The transfer characteristics of the rectifiers are also shown within the block.www.3 mA MCQ 8.

com PAGE 432 ANALOG & DIGITAL ELECTRONICS CHAP 8 It is desired to make full wave rectifier using above two half-wave rectifiers.co.in .gatehelp.34 A waveform generator circuit using OPAMPs is shown in the figure. The resultants circuit will be MCQ 8. It produces a triangular wave at point ‘P’ with a peak to peak voltage of 5 V for Vi = 0 V .www. GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www.nodia.

nodia.co.36 The output of the filter in Q.gatehelp. the circuit acts as a (A) all pass filter (B) band pass filter (C) high pass filter (D) low pass filter MCQ 8.5 V.in . A general filter circuit is shown in the figure : MCQ 8.35 If R1 = R2 = RA and R3 = R4 = RB .www. the voltage waveform at point ‘P’ will become Statement for Linked Answer Questions 21 and 22.com CHAP 8 ANALOG & DIGITAL ELECTRONICS PAGE 433 If the voltage Vi is made + 2.21 is given to the circuit in figure : The gain v/s frequency characteristic of the output (vo) will be GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www.

is used to implement a 3-variable Boolean function as shown in the figure The simplified form of Boolean function F (A. B. with active low outputs. 2100 H and 0000 H respectively.37 A 3-line to 8-line decoder. C) implemented in ‘Product of Sum’ form will be (A) (X + Z) (X + Y + Z ) (Y + Z) (B) (X + Z ) (X + Y + Z) (Y + Z ) (C) (X + Y + Z) (X + Y + Z) (X + Y + Z) (X + Y + Z ) (D) (X + Y + Z) (X + Y + Z ) (X + Y + Z) (X + Y + Z ) MCQ 8. program counter (PC) and (H.38 The content of some of the memory location in an 8085 accumulator based system are given below Address g 26FE 26FF 2700 2701 2702 Content g 00 01 02 03 04 g g The content of stack (SP).com PAGE 434 ANALOG & DIGITAL ELECTRONICS CHAP 8 MCQ 8. 2100 H: DAD SP 2101 H: PCHL the content of (SP) and (PC) at the end of execution will be GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www.co.nodia. When the following sequence of instruction are executed.in .www.L) are 2700 H.gatehelp.

co.www. SP = 2700 H (D) PC = 2A02 H.4 W The circuit shown in the figure is GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www. what is the power dissipated in the transistor ? (A) 0.4 W (D) 5.com CHAP 8 ANALOG & DIGITAL ELECTRONICS PAGE 435 (A) PC = 2102 H. SP = 2702 H ONE MARK The common emitter forward current gain of the transistor shown is βF = 100 The transistor is operating in (A) Saturation region (C) Reverse active region MCQ 8. If Vin is 10 V.in .41 (B) 2.gatehelp.2 W MCQ 8.40 (B) Cutoff region (D) Forward active region The three-terminal linear voltage regulator is connected to a 10 Ω load resistor as shown in the figure.6 W (C) 4. SP = 26FE H YEAR 2007 MCQ 8.39 (B) PC = 2700 H. SP = 2700 H (C) PC = 2800 H.nodia.

43 TWO MARKS The input signal Vin shown in the figure is a 1 kHz square wave voltage that alternates between + 7 V and − 7 V with a 50% duty cycle. C and D are input. C. Both transistor have the same current gain which is large. C and D is even (D) S = 1 only if the sum of A. D and Y is correct ? (A) S is always with zero or odd (B) S is always either zero or even (C) S = 1 only if the sum of A. and Y is the output bit in the XOR gate circuit of the figure below. (A) 46% (C) 63% (B) 55% (D) 92% GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www. Which of the following statements about the sum S of A.in . B.42 A.co. B. B.com PAGE 436 ANALOG & DIGITAL ELECTRONICS CHAP 8 rV R1 < R2 r < R2 (B) a voltage source with voltage V R1 r < R2 V (C) a current source with current c R1 + R2 m r (D) a current source with current c R2 mV R1 + R2 r (A) a voltage source with voltage MCQ 8.gatehelp.nodia. C and D is odd YEAR 2007 MCQ 8. What is the efficiency of this circuit for the given input ? choose the closest answer.www. The circuit delivers power to the load resistor RL . B.

The waveform appearing across the capacitor starting from t = 0 .co. it is opened at time t = 0 . You may neglect the zener diode forward voltage drops. What is the behavior of vout for t > 0 ? (A) It makes a transition from − 5 V to + 5 V at t = 12.CD is (A) 253.98 μs (B) It makes a transition from − 5 V to + 5 V at t = 2.46 IC 555 in the adjacent figure is configured as an astable multi-vibrator.com CHAP 8 ANALOG & DIGITAL ELECTRONICS PAGE 437 MCQ 8.632 MCQ 8. as observed on a storage CRO is GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www.in .44 The switch S in the circuit of the figure is initially closed.nodia.57 μs MCQ 8.45 The Octal equivalent of HEX and number AB.314 (B) 253.www. The pin description is : 1 and 8-supply. 6-threshold 7-discharge. 2-trigger. It is enabled to to oscillate at t = 0 by applying a high input to pin 4.98 μs (D) It makes a transition from + 5 V to − 5 V at t = 2.314 (D) 526.57 μs (C) It makes a transition from + 5 V to − 5 V at t = 12.632 (C) 526.gatehelp. 4-reset.

the voltage waveform at point P of the clamper circuit shown in figure will be GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www.www.co. D3 OFF (C) D1 ON.48 (B) D1 OFF. D3 ON MCQ 8. D2 OFF.in .47 ONE MARK What are the states of the three ideal diodes of the circuit shown in figure ? (A) D1 ON. D2 OFF. D3 OFF (D) D1 OFF.nodia. D3 ON For a given sinusoidal input voltage.gatehelp. D2 ON.com PAGE 438 ANALOG & DIGITAL ELECTRONICS CHAP 8 YEAR 2006 MCQ 8. D2 ON.

gatehelp.49 TWO MARKS Assuming the diodes D1 and D2 of the circuit shown in figure to be ideal ones.in .nodia. the transfer characteristics of the circuit will be GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www.com CHAP 8 ANALOG & DIGITAL ELECTRONICS PAGE 439 YEAR 2006 MCQ 8.co.www.

gatehelp. The voltage waveform at point P will be GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www. the transistor would be operating in (A) saturation region (C) breakdown region MCQ 8.co. The supply voltages of the OPAMP are ! 12 V . If the β of the transistor is 30 and ICBO is 20 mA and the input voltage is + 5 V .nodia.in .50 Consider the circuit shown in figure.www.com PAGE 440 ANALOG & DIGITAL ELECTRONICS CHAP 8 MCQ 8.51 (B) active region (D) cut-off region A relaxation oscillator is made using OPAMP as shown in figure.

The output achieved is different as shown in figure.gatehelp.7 V of both the transistors.co.0 V. What could be the possible cause of this error ? (A) The resistance values are incorrect option.com CHAP 8 ANALOG & DIGITAL ELECTRONICS PAGE 441 MCQ 8. GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www.in .53 A student has made a 3-bit binary down counter and connected to the R-2R ladder type DAC. then the states of the two transistors will be (A) Q1 ON and Q2 OFF (B) Q1 reverse ON and Q2 OFF (C) Q1 reverse ON and Q2 ON (D) Q1 OFF and Q2 reverse ON MCQ 8. if Vi = 3.52 A TTL NOT gate circuit is shown in figure. [Gain = (− 1 kΩ/2R)] as shown in figure to generate a staircase waveform. Assuming VBE = 0.www.nodia.

C) = Σ (1. 4. 2. B. C) implemented is (A) F (A. 6) MCQ 8.nodia.com PAGE 442 ANALOG & DIGITAL ELECTRONICS CHAP 8 (B) The counter is not working properly (C) The connection from the counter of DAC is not proper (D) The R and 2R resistance are interchanged MCQ 8. B.57 ONE MARK Assume that D1 and D2 in figure are ideal diodes. 255D MVI L. 2. B. The Boolean function F (A. it is desired to increment the contents of memory location whose address is available in (D.54 A 4 # 1 MUX is used to implement a 3-input Boolean function as shown in figure. The value of current is GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www. 6) (D) F (A. B.co. B.55 (B) F (A. The sequence of instruction is (A) XCHG (B) XCHG INR M (C) INX D XCHG (D) INX H INR M XCHG YEAR 2005 MCQ 8. 5. C) = Σ (1.56 In an 8085 A microprocessor based system.www. C) = Σ (2. 6) (C) F (A. 5. 6) A software delay subroutine is written as given below : DELAY : MVI H. 255D LOOP : DCR L JNZ LOOP DCR H JNZ LOOP How many times DCR L instruction will be executed ? (A) 255 (B) 510 (C) 65025 (D) 65279 MCQ 8. C) = Σ (1.E) register pair and store the result in same location.gatehelp.in . 4.

60 (B) 2 V (D) 0 V The digital circuit shown in the figure works as (A) JK flip-flop (C) T flip-flop (B) Clocked RS flip-flop (D) Ring counter YEAR 2005 MCQ 8.com CHAP 8 ANALOG & DIGITAL ELECTRONICS PAGE 443 (A) 0 mA (C) 1 mA MCQ 8.5 mA (D) 2 mA The 8085 assembly language instruction that stores the content of H and L register into the memory locations 2050H and 2051H .0 V the voltage Vab between nodes a and b is (A) 5 V (C) 1 V MCQ 8.61 TWO MARKS The common emitter amplifier shown in the figure is biased using a 1 mA ideal current source.co.58 (B) 0.59 Assume that the N-channel MOSFET shown in the figure is ideal.gatehelp.www.nodia.in . The approximate base current value is GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www. and that its threshold voltage is + 1. respectively is (B) SPHL 2051H (A) SPHL 2050H (C) SHLD 2050H (D) STAX 2050H MCQ 8.

The value of R1 should be (A) Infinity (C) 100 k Ω MCQ 8.gatehelp. if the input is a sinusoidal signal.in . The designer wishes to realize the input resistance seen by the small-signal source to be as large as possible.nodia.62 (B) 10 μA (D) 1000 μA Consider the inverting amplifier.63 (B) 1 M Ω (D) 40 k Ω The typical frequency response of a two-stage direct coupled voltage amplifier is as shown in figure MCQ 8.co.www. while keeping the voltage gain between − 10 and − 25 .com PAGE 444 ANALOG & DIGITAL ELECTRONICS CHAP 8 (A) 0 μA (C) 100 μA MCQ 8. The upper limit on RF is 1 M Ω .64 In the given figure. using an ideal operational amplifier shown in the figure. the output will appear as shown GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www.

in .com CHAP 8 ANALOG & DIGITAL ELECTRONICS PAGE 445 MCQ 8.65 Select the circuit which will produce the given output Q for the input signals X1 and X2 given in the figure GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www.gatehelp.co.www.nodia.

as long as X1 = 1 and X2 = 1. The output characteristics of the MOSFET are also shown MCQ 8. 68 and Q. the output Q remains (A) at 1 (C) at its initial value (B) at 0 (D) unstable Data for Q.66 If X1 and X2 are the inputs to the circuit shown in the figure.67 (B) X1 : X2 (D) X1 : X2 In the figure. the output Q is (A) X1 + X2 (C) X1 : X2 MCQ 8.in .www.gatehelp.nodia.68 The transconductance of the MOSFET is (A) 0. 69 are given below. Solve the problems and choose the correct option. Assume that the threshold voltage of the N-channel MOSFET shown in figure is + 0.75 V.com PAGE 446 ANALOG & DIGITAL ELECTRONICS CHAP 8 MCQ 8.co.75 ms (B) 1 ms (C) 2 ms (D) 10 ms GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www.

70 The current through the Zener diode in figure is (A) 33 mA (C) 2 mA MCQ 8.com CHAP 8 ANALOG & DIGITAL ELECTRONICS PAGE 447 MCQ 8.71 (B) 3.www.3 mA (D) 0 mA Two perfectly matched silicon transistor are connected as shown in figure.co.gatehelp.5 (D) − 10 ONE MARK MCQ 8.3 mA (D) 7.in .3 mA MCQ 8.72 (B) 2.3 mA The feedback used in the circuit shown in figure can be classified as GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www.nodia. The value of the current I is (A) 0 mA (C) 4.69 The voltage gain of the amplifier is (A) + 5 (C) + 10 YEAR 2004 (B) − 7.

76 (B) 5 mA (D) − 3 mA The trans-conductance gm of the transistor shown in figure is 10 mS.com PAGE 448 ANALOG & DIGITAL ELECTRONICS CHAP 8 (A) shunt-series feedback (C) series-shunt feedback MCQ 8. The value of the input resistance Rin is GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www.in .gatehelp.75 TWO MARKS Assuming that the diodes are ideal in figure.73 (B) shunt-shunt feedback (D) series-series feedback The digital circuit using two inverters shown in figure will act as (A) a bistable multi-vibrator (B) an astable multi-vibrator (C) a monostable multi-vibrator (D) an oscillator MCQ 8.co.nodia.www. the current in diode D1 is (A) 9 mA (C) 0 mA MCQ 8.74 The voltage comparator shown in figure can be used in the analog-to-digital conversion as (A) a 1-bit quantizer (B) a 2-bit quantizer (C) a 4-bit quantizer (D) a 8-bit quantizer YEAR 2004 MCQ 8.

3 kΩ (D) 2.5 kΩ The value of R for which the PMOS transistor in figure will be biased in linear region is (A) 220 Ω (C) 680 Ω MCQ 8. a pair of poles will be realized with ω0 equal to (A) 1000 rad/s (C) 10 rad/s (B) 100 rad/s (D) 1 rad/s GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www.0 kΩ (C) 5.77 (B) 8.78 (B) 470 Ω (D) 1200 Ω In the active filter circuit shown in figure.co.0 kΩ MCQ 8.nodia. if Q = 1.com CHAP 8 ANALOG & DIGITAL ELECTRONICS PAGE 449 (A) 10.gatehelp.www.in .

80 (B) − 100 kΩ (D) − 1 MΩ The simplified form of the Boolean expression Y = (A $ BC + D) (A $ D + B $ C ) can be written as (A) A $ D + B $ C $ D (C) (A + D) (B $ C + D ) (B) AD + B $ C $ D (D) A $ D + BC $ D MCQ 8. 0101 (D) 1010.gatehelp.81 A digit circuit which compares two numbers A3 A2 A1 A0 and B 3 B2 B1 B 0 is shown in figure. 1010 (C) 0010. 0010 MCQ 8.www. Choose the correct output waveform from the options given below. GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www.nodia. choose one pair of correct input numbers. To get output Y = 0 . 1011 The digital circuit shown in figure generates a modified clock pulse at the output. (A) 1010.co.79 The input resistance Rin = vx /ix of the circuit in figure is (A) + 100 kΩ (C) + 1 M Ω MCQ 8.com PAGE 450 ANALOG & DIGITAL ELECTRONICS CHAP 8 MCQ 8.in .82 (B) 0101.

gatehelp. if VCE (sat) = 0.co. Move 14 H to register A SHIFT RLC .com CHAP 8 ANALOG & DIGITAL ELECTRONICS PAGE 451 MCQ 8.nodia. 14H . Jump on non-zero to SHIFT HALT (A) 4 (B) 8 (C) 13 (D) 16 MCQ 8.in . Rotate left without carry JNZ SHIFT .www.1 V .83 If the following program is executed in a microprocessor.84 In the Schmitt trigger circuit shown in figure. the number of instruction cycle it will take from START to HALT is START MVI A. the output logic low level (VOL) is GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www.

nodia.7 V.gatehelp.35 V (D) 5.3)] mA For the circuit of figure with an ideal operational amplifier.co. assume that the transistor has hfe = 99 and VBE = 0.com PAGE 452 ANALOG & DIGITAL ELECTRONICS CHAP 8 (A) 1.3(33+3.3+3.3/(3. The MOSFET is (A) an n-channel depletion mode device (B) an n-channel enhancement mode device (C) an p-channel depletion mode device (D) an p-channel enhancement mode device MCQ 8.25 V (C) 2.86 In the circuit of figure.85 ONE MARK The variation of drain current with gate-to-source voltage ( ID − VGS characteristic) of a MOSFET is shown in figure. the maximum phase shift of the output vout with reference to the input vin is GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www.in .33] mA MCQ 8.00 V YEAR 2003 MCQ 8.87 (B) [3.3] mA (C) [3.3)] mA (D) [3.3/.50 V (B) 1. The value of collector current IC of the transistor is approximately (A) [3.www.3/3.

(C) the memory address of the instruction that is being currently executed (D) the memory address of the instruction that is to be executed next YEAR 2003 MCQ 8.com CHAP 8 ANALOG & DIGITAL ELECTRONICS PAGE 453 (A) 0c (C) + 90c MCQ 8.89 (B) I0 = I1 = C in.gatehelp.co.If the value of RD is increased to 4 kΩ .0 mA GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www. the threshold voltage Vth = 2 V.8 mA (C) 1. its Program Counter contains (A) the number of instructions in the current program that have already been executed (B) the total number of instructions in the program being executed. Which of the following combinations of inputs to I0. I2 = I3 = Cin (C) I0 = I3 = Cin.www. I1 = I2 = Cin When a program is being executed in an 8085 microprocessor. I2 = I3 = Cin (D) I0 = I3 = C in.in . I1. I2 and I3 of the MUX will realize the sum S ? (A) I0 = I1 = Cin.4 mA (B) 2.0 mA (D) 1.nodia. The drain current ID of the MOSFET is 4 mA when the drain resistance RD is 1 kΩ . I1 = I2 = Cin MCQ 8.88 (B) − 90c (D) ! 180c Figure shows a 4 to 1 MUX to be used to implement the sum S of a 1-bit full adder with input bits P and Q and the carry input Cin .90 TWO MARKS For the n-channel enhancement MOSFET shown in figure. drain current ID will become (A) 2.

nodia.in .www.co. and minimum values of the output waveform Vout of the circuit are respectively (A) + 10 V and − 10 V (C) + 7 V and − 4 V MCQ 8.gatehelp. RB = 3.75 for the output voltage waveform are (A) RA = 3. The maximum. as shown in figure.92 (B) − 20 (D) − 120 A voltage signal 10 sin ωt is applied to the circuit with ideal diodes. The value of the capacitor C is 10 nF.62 kΩ GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www. The values of the resistors RA and RB for a frequency of 10 kHz and a duty cycle of 0.93 (B) + 4 V and − 4 V (D) + 4 V and − 7 V The circuit of figure shows a 555 Timer IC connected as an astable multivibrator.91 Assuming the operational amplifier to be ideal.62 kΩ. the gain vout /vin for the circuit shown in figure is (A) − 1 (C) − 100 MCQ 8.com PAGE 454 ANALOG & DIGITAL ELECTRONICS CHAP 8 MCQ 8.

95 The shift register shown in figure is initially loaded with the bit pattern 1010.94 The boolean expression X Y Z + XY Z + XYZ + XY Z + XYZ simplified to (A) XZ + X Z + YZ (B) XY + Y Z + YZ (C) XY + YZ + XZ (D) XY + YZ + X Z can be MCQ 8.25 kΩ (C) RA = 7.62 kΩ (D) RA = 7. After how many clock pulses will the content of the shift register become 1010 again ? (A) 3 (C) 11 MCQ 8. Subsequently the shift register is clocked. K = Y (D) J = Y .96 (B) 7 (D) 15 An X-Y flip-flop. and with each clock pulse the pattern gets shifted by one bit position to the right. the bit at the serial input is pushed to the left most position (msb). RB = 7. With each shift.25 kΩ.co.in .25 kΩ MCQ 8. RB = 3.www.62 kΩ.nodia.com CHAP 8 ANALOG & DIGITAL ELECTRONICS PAGE 455 (B) RA = 3.25 kΩ. RB = 7. The total size of the memory system is (A) 16 kbytes (B) 32 kbytes (C) 48 kbytes (D) 64 kbytes GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www. whose Characteristic Table is given below is to be implemented using a J-K flip flop (A) J = X.97 (B) J = X.gatehelp. K = Y (C) J = Y. K = X A memory system has a total of 8 memory chips each with 12 address lines and 4 data lines. K = X MCQ 8.

A XOR A On completion of the execution of the program.com PAGE 456 ANALOG & DIGITAL ELECTRONICS CHAP 8 MCQ 8. 1FFE MOV B.nodia.co. The dc component of the source current is (A) Vm (B) Vm 50π 50π 2 Vm (C) (D) 2Vm 50π 100π 2 MCQ 8.100 (B) 2.101 The cut-in voltage of both zener diode DZ and diode D shown in Figure is 0. while break-down voltage of DZ is 3.gatehelp. the result of addition is found (A) in the register A (B) at the memory address 1000 (C) at the memory address 1F00 (D) at the memory address 2000 YEAR 2002 MCQ 8.5 kHz (D) 5 kHz The forward resistance of the diode shown in Figure is 5 Ω and the remaining parameters are same at those of an ideal diode.7 V.3 V and reverse break-down voltage of D is 50 V. The frequency of the signal available at Q is. The other parameters can be assumed to be the same GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www. M INR L MOV A. M ADD B INR L MOV M. (A) 10 kHz (C) 20 kHz MCQ 8.99 ONE MARK The frequency of the clock signal applied to the rising edge triggered D-flipflop shown in Figure is 10 kHz.98 The following program is written for an 8085 microprocessor to add two bytes located at memory addresses 1FFE and 1FFF LXI H.www.in .

25 ? (A) 4.46 kHz (D) 24. (D) 4 V in both positive and negative half cycle MCQ 8. (B) 4 V in the positive half cycle and 5 V in the negative half cycle. The peripheral will respond to addresses in the range.92 kHz (B) 0.co.102 The logic circuit used to generate the active low chip select (CS ) by an 8085 microprocessor to address a peripheral is shown in Figure.104 The output voltage (vo) of the Schmitt trigger shown in Figure swings between + 15 V and − 15 V . (C) 3.3 V in the positive half cycle and 1.nodia. Assume that the operational amplifier is ideal.gatehelp.103 TWO MARKS A first order. The output will change from + 15 V to − 15 V when the instantaneous value of the input sine wave is GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www.49 kHz (C) 2. What is the frequency at which the gain of the voltage transfer function of the filter is 0. low pass filter is given with R = 50 Ω and C = 5 μF .www.4 V in the negative half cycle.6 kHz MCQ 8.in .3 V in both positive and negative half cycles.com CHAP 8 ANALOG & DIGITAL ELECTRONICS PAGE 457 as those of an ideal diode. (A) E000-EFFF (C) 1000-FFFF (B) 000E-FFFE (D) 0001-FFF1 YEAR 2002 MCQ 8. The values of the peak output voltage (Vo) are (A) 3.

7 V MCQ 8. IE = 1 mA. the boolean expression for the output Y in terms of inputs P. β = 99 and VBE = 0.9 Volt (B) 14 Volt (D) None of these MCQ 8.105 For the circuit shown in Figure.106-108* For the circuit shown in Figure.20 mA (B) 1.co.106 The current through RC is (A) 0.1 Volt (C) 13. R and S is (A) P + Q + R + S (C) (P + Q ) (R + S ) (B) P + Q + R + S (D) (P + Q) (R + S) Common Data Questions Q.107 Output voltage V0 will be (A) 16.gatehelp.www.in .1 mA (D) 1 mA MCQ 8.com PAGE 458 ANALOG & DIGITAL ELECTRONICS CHAP 8 (A) 5 V in the positive slope only (B) 5 V in the negative slope only (C) 5 V in the positive and negative slopes (D) 3 V in the positive and negative slopes.99 mA (C) 1.108 Value of resistance RF is GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www. Q.nodia. MCQ 8.

9 kΩ (C) 130.111 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www.95-97*.nodia.co.90 kΩ (B) 124.5 kΩ (D) None of these Common data question Q.in .com CHAP 8 ANALOG & DIGITAL ELECTRONICS PAGE 459 (A) 110. given that R = 10 kΩ and C = 100 pF MCQ 8.109 The transfer function (A) (C) 2 Vy of the first network is Vx (B) (D) jωCR (1 − ω R2 C 2) + j2ωCR 2 jωCR (1 − ω R2 C 2) + j3ωCR jωCR 1 + j3ωCR jωCR 1 + j2ωCR 1 2RC MCQ 8. The following network is used as a feedback circuit in an oscillator shown in figure to generate sinusoidal oscillations.110 The frequency of oscillation will be (A) 1 RC (C) 1 4RC Value of RF is (A) 1 kΩ (C) 2 kΩ (B) (D) None of these (B) 4 kΩ (D) 8 kΩ MCQ 8.gatehelp.www. Assuming that the operation amplifier is ideal.

The circuit is operated in steady state at the boundary of continuous and discontinuous conduction.33 A (C) 66. are (A) 63. of the counter is: (A) 7 (C) 4 MCQ 8. the source I is a dc current source.114-115* In the circuit shown in Figure. Values of the on-time tON of the switch and peak current ip .co. 63. module no. 63. so that the inductor current i is as shown in Figure.com PAGE 460 ANALOG & DIGITAL ELECTRONICS CHAP 8 MCQ 8. The switching time period is T = tON + tOFF μs. the ideal switch S is switched on and off with a switching frequency f = 10 kHz . The signal levels at J and K inputs of all the flip flops are maintained at logic 1.gatehelp.66 μsec . You may assume GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www.66 mA (B) 63.112 *The ripple counter shown in figure is made up of negative edge triggered J-K flip-flops.nodia.www. 66.in .33 μsec .The switch S is operated with a time period T and a duty ratio D .33 μsec .113 (B) 5 (D) 8 *In Figure . Assume all the outputs are cleared just prior to applying the clock signal.33 μA (D) none of these Common Data Questions Q.

115 YEAR 2001 MCQ 8. (B) I (1 − DT) (A) I C C (C) I (1 − D) T (D) − I T C C The average output voltage V0.114 The voltage Vc. Then.com CHAP 8 ANALOG & DIGITAL ELECTRONICS PAGE 461 that the capacitance C has a finite value which is large enough so that the voltage.www. VC has negligible ripple.116 ONE MARK In the single-stage transistor amplifier circuit shown in Figure.co. the capacitor CE is removed.gatehelp. with the polarity shown in Figure.nodia. in terms of D . with the polarity shown in figure (B) − I D2 T (A) − I T C 2C (C) I (1 − DT) (D) I (1 − D) T 2C 2C MCQ 8. the ac small-signal mid-band voltage gain of the amplifier (A) increase (C) is unaffected (B) decreases (D) drops to zero GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www.in . I and R MCQ 8. calculate the following under steady state conditions.

The gate is either (A) a NAND or an EX-OR gate (B) a NOR or an EX-OR gate (C) an AND or an EX-NOR gate (D) a NOR or an EX-NOR gate MCQ 8. then the new upper cut-off frequency is (A) 10 Hz (B) 100 Hz (C) 10 kHz (D) 100 kHz YEAR 2001 MCQ 8.co. If this op-amp is connected as an amplifier with a closedloop gain of 100.nodia.119 The output f of the 4-to-1 MUX shown in Figure is (A) xy + x (C) x + y MCQ 8.com PAGE 462 ANALOG & DIGITAL ELECTRONICS CHAP 8 MCQ 8.in . the slowest ADC (analog-to-digital converter) is (A) parallel-comparator (i.117 Among the following four.www.118 The output of a logic gate is “1” when all its inputs are at logic “0”. flash) type (B) successive approximation type (C) integrating type (D) counting type MCQ 8.121 TWO MARKS For the oscillator circuit shown in Figure.gatehelp.e. the expression for the time period of oscillation can be given by (where τ = RC ) GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www.120 (B) x + y (D) xy + x An op-amp has an open-loop gain of 105 and an open-loop upper cut-off frequency of 10 Hz.

having a slew rate of 62.25 mA (C) 25. then the minimum frequency at which the slew rate limited distortion would set in at the output is (A) 1. The conversion time of the ADC is 1 μ sec.0 MHz (D) 62. The maximum value of the input signal to the S/H circuit is 5 V.www. and during this time.122 An Intel 8085 processor is executing the program given below.N ring counter.5 μA MCQ 8.1 nF. The leakage current of the S/H circuit should be less than (A) 2.126 *The circuit shown in the figure is a MOD. If the maximum amplitude of the input sinusoidal is 10 V.0 (C) 2.5 (D) 3.5 (B) 2. is used at the input of an ADC (analog-to-digital converter). shows a transconductance (gm) of 1 mA/V when the applied gate -to-source voltage (VGS ) is − 3 V .in .0 μA (D) 2. the capacitor should not loose more than 0. having a pinch off voltage (Vp ) of − 5 V . 10 H MVI B. 10 H BACK: NOP ADD B RLC INC BACK HLT The number of times that the operation NOP will be executed is equal to (A) 1 (B) 2 (C) 3 (D) 4 MCQ 8.gatehelp. MVI A.124 An op-amp. is connected in a voltage follower configuration.com CHAP 8 ANALOG & DIGITAL ELECTRONICS PAGE 463 (A) τ ln 3 (C) τ ln 2 (B) 2τ ln 3 (D) 2τ ln 2 MCQ 8. Its maximum transconductance (in mA/V) is (A) 1.8 V/ μ sec .5% of the charge put across it during the sampling time.123 A sample-and-hold (S/H) circuit.co.125 An n-channel JFET. having a holding capacitor of 0.5 mA (B) 0.nodia.0 MCQ 8.8 MHz MCQ 8.28 MHz (C) 10.0 MHz (B) 6. Value of N is GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www.

gatehelp. Assume that the op-amps are ideal.co. determine the output voltage vo .in . (A) − 8 V 7 (C) − 10 V (B) − 20 V 7 (D) None of these Common Data Questions Q. Q 3 Q2 Q1 Q 0 = 1110 ). r b = 0.e.128-129*.127 (B) 15 (D) 6 *For the op-amp circuit shown in Figure.www. (A) 4 (C) 7 MCQ 8. and r 0 " 3 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www. β0 = 200. The transistor in the amplifier circuit shown in Figure is biased at IC = 1 mA Use VT = kT/q = 26 mV.nodia.com PAGE 464 ANALOG & DIGITAL ELECTRONICS CHAP 8 (assume initial state of the counter is 1110 i.

62 (D) − 1 MCQ 8.59 mF (C) 5 μF (D) 10 μF Common Data Questions Q. 1000 k Ω . 100 k Ω .128 Small-signal mid-band voltage gain vo /vi is (B) 38. 15.nodia.gatehelp.131 If the above filter has a 3 dB frequency of 1 kHz.in .46 (A) − 8 (C) − 6.co. 15.9 nF (D) none of these ************ GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www.11 μ F (C) 100 k Ω .9 nF (B) 10 k Ω . 0.15 mF (B) 1. a high frequency input resistance of 100 kΩ and a high frequency gain of magnitude 10.130-131* For the circuit shown in figure MCQ 8. Then values of R1. R2 and C respectively are :(A) 100 k Ω .com CHAP 8 ANALOG & DIGITAL ELECTRONICS PAGE 465 MCQ 8. 1000 k Ω .130 The circuit shown is a (A) Low pass filter (C) Band Reject filter (B) Band pass filter (D) High pass filter MCQ 8.www.129 What is the required value of CE for the circuit to have a lower cut-off frequency of 10 Hz (A) 0.

Prime implicants are the terms that we get by solving K-map F = XY + XY 1 4 424 43 prime implicants SOL 8. Let v > 0.7 D (1000) − v = 0 500 10 − (v − 0.7 3 i = v − 0.2 mA 500 500 (Assumption is true) So.nodia. when A > B A = a1 a 0.com PAGE 466 ANALOG & DIGITAL ELECTRONICS CHAP 8 SOLUTION SOL 8.7 V and diode is forward biased.8 V > 0.7) # 2 − v = 0 v = 11.7 = 6.2 Option (D) is correct. Applying Kirchoff’s voltage law 10 − i # 1k − v = 0 10 − :v − 0.www. Y = 1.8 − 0.in .7 = 3.1 Option (A) is correct.gatehelp.co.3 Option (B) is correct. B = b1 b 0 a1 0 1 1 1 1 1 a0 1 0 0 1 1 1 b1 0 0 0 0 0 1 b0 0 0 1 0 1 0 Y 1 1 1 1 1 1 Total combination = 6 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www. SOL 8.4 = 3.

Option (C): When CLK = 1. If Y1 = 0 . So race around doesn’t occur for the condition. Option (A) will be correct. So. Y1 = Y2 = 1 and it will also remain the same for the clock period. Option (A): When CLK = 0 Output of the NAND gate will be A1 = B1 = 0 = 1. Option (D): When CLK = 1. Y2) oscillates between ‘0’ and ‘1’ checking it from the options. 1. here race around doesn’t occur for the condition CLK = 0 . If Y2 = 0 .co. it won’t oscillate for CLK = 0 .4 Option (A) is correct.www.com CHAP 8 ANALOG & DIGITAL ELECTRONICS PAGE 467 SOL 8. GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www. A1 = B1 = 1 And again as described for Option (B) race around doesn’t occur for the condition. A = B = 1 A1 = B1 = 0 and so Y1 = Y2 = 1 And it will remain same for the clock period.gatehelp. So. A = B = 0 So.in . SOL 8. The given circuit is Condition for the race-around It occurs when the output of the circuit (Y1. 3.5 Option (D) is correct. So. Y2 = Y1 = 1 and it will remain the same and doesn’t oscillate. DC Analysis : Using KVL in input loop. 2.nodia. Due to these input to the next NAND gate. Y2 = Y1 : 1 = Y1 and Y1 = Y2 : 1 = Y2 .

16 # 10 v 0 − 1 # 10 v 0 Rs = 10 kΩ (source resistance) 10 # 10 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www.01 mA β 100 = 0.7 − VC = 100I B 12 # 103 Solving equation (i) and (ii). gm = 0.1 # 10−4) − v 0 RF Substituting Vπ from equation (i) vi = − 5.5 kΩ IB 0..01 mA .72 Rs RF . IB = 0..33 # 10−5) + v π (0.04 s v 0 (9.04) = 0 v 0 =− 428.04 s gm = = rπ 2..(ii) Small Signal Analysis : Transforming given input voltage source into equivalent current source.gatehelp. rπ = VT = 25 mV = 2.7 = 0 VC = 100IB + 0..(i) .(i) vi −6 −5 3 =− 1.IE = 13.www. This is a shunt-shunt feedback amplifier.com PAGE 468 ANALOG & DIGITAL ELECTRONICS CHAP 8 VC − 100IB − 0..co.in .72Vπ Writing KCL at input node vi = v π + v π + v π − vo = v 1 + 1 + 1 − v 0 π: Rs Rs rπ RF Rs rπ RF D RF = v π (5.7 − VC = (β + 1) IB 12k 13.5 # 1000 Writing KCL at output node v0 + g v + v0 − vπ = 0 m π RC RF v 0 : 1 + 1 D + v π :gm − 1 D = 0 RC RF RF Substituting RC = 12 kΩ. Given parameters.nodia.1 # 10−4 v − v 0 0 428. RF = 100 kΩ..7 IC .

D = Y = AX 0 + AX1 Qn + 1 = D = AX 0 + AX1 Qn + 1 = A Qn + AQn Qn + 1 = Qn Qn + 1 = Qn If A = 0.6 Option (D) is correct.in .8.116 # 10−5 10 # 103 1 Av = v 0 = . so V (jω) =− R2 V (jω) o R1 i ωC ISBN: 9788192276243 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Visit us at: www. so V = 0 o ωC 1 " 0.7 Option (B) is correct. So state diagram is X 0 = Q .com CHAP 8 ANALOG & DIGITAL ELECTRONICS PAGE 469 vi =− 1. Published by: NODIA and COMPANY Vi (jω) R2 R1 − j 1 ωC 1 " 3.gatehelp.96 vi 10 # 103 # 1. If A = 1. From the given below figure.116 # 10−5 SOL 8. 0 − Vi (jω) 0 − Vo (jω) =0 + 1 +R R2 1 jω C Vo (jω) − Vi (jω) = 1 +R R2 1 jω C Vo (jω) =− At ω " 0 (Low frequencies). X1 = Q (toggle of previous state) SOL 8. At ω " 3 (higher frequencies). First we obtain the transfer function.www.co. Let Qn + 1 is next state and Qn is the present state.nodia.

com PAGE 470 ANALOG & DIGITAL ELECTRONICS CHAP 8 The filter passes high frequencies so it is a high pass filter. 1 & R2 = 1 1 ω C2 ω 2C 2 2 0 ω0 = SOL 8.8 1 R1 C Option (D) is correct.in .nodia. gain will be 2 times of maximum gain 6H (3)@ H ^ jω0h = 1 H (3) 2 R2 R2 1 = b l 2 2 R1 + 21 2 R1 ω0 C 2 2 2R 1 = R1 + So.gatehelp. it will act as a Band pass filter.www.co. GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www. So. H (jω) = Vo = − R2 Vi R1 − j 1 ωC R R − 2 2 H (3) = = R1 R1 At 3 dB frequency.

SOL 8.in .www.gatehelp. so it acts as an schmitt trigger.nodia.co. Threshold value VTH = 12 = 6 V 2 VTL =− 6 V Option (A) is correct. Since Va =− Vi this is a non-inverting schmitt trigger. The first half of the circuit is a differential amplifier (negative feedback) Va =− (Vi) Second op-amp has a positive feedback.9 Option (D) is correct.11 Option (C) is correct.com CHAP 8 ANALOG & DIGITAL ELECTRONICS PAGE 471 SOL 8. POP H & HL = LP + 3 DAD D & HL = HL + DE GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www. LXI D. DISP LP : CALL SUB LP + 3 When CALL SUB is executed LP+3 value is pushed(inserted) in the stack.10 Y = X5X = X X + XX = XX + X X = X+X = 1 SOL 8.

2k Y βIB Note:.com PAGE 472 ANALOG & DIGITAL ELECTRONICS CHAP 8 = LP + 3 + DE PUSH H & The last two value of the stack will be HL value i.e.nodia. K = QB The output of JK flip flop QA (n + 1) = QB QA + QB QA = QB (QA + QA) = QB Output of T flip-flop QB (n + 1) = Q A Clock pulse Initially(tn ) tn + 1 tn + 2 tn + 3 QA 1 1 1 1 QB 0 0 0 0 QA (n + 1) 1 1 1 1 QB (n + 1) 0 0 0 0 Qn + 1 is the next state GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www.www.In saturation mode IC SOL 8.12 Option (D) is correct.2 = 5.in .gatehelp.13 Option (C) is correct. So the BJT is operating in saturation.36 mA 2. Collector current IC = 12 − 0. Zener Diode is used as stabilizer.co. The circuit is assumed to be as We can see that both BE and BC Junction are forwarded biased. The characteristics equation of the JK flip-flop is Q n + 1 = JQ n + KQn From figure it is clear that J = QB . LP + DISP + 3 SOL 8.

both zener and diode D will be off. the equivalent circuit is vo = 5 + 0.7 V . The circuit is Output follows input i. vi # − 0.gatehelp.e vo = vi Note that zener goes in reverse breakdown(i.7 = 5. 1. When − 0.7 V SOL 8. When vi > 5.7 V 2.e acts as a constant battery) only when difference between its p-n junction voltages exceeds 10 V.14 Option (C) is correct.nodia. the diode D will be forward biased and zener remains off.co. 3. Since the op-amp is ideal v+ = v− =+ 2 volt By writing node equation v− − 0 + v− − vo = 0 R 2R GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www.7 V .in .7 .15 Option (B) is correct.www.7 1 vi # 5. zener diode becomes forward biased and diode D will be off so the equivalent circuit looks like The output vo =− 0.com CHAP 8 ANALOG & DIGITAL ELECTRONICS PAGE 473 SOL 8. We can obtain three operating regions depending on whether the Zener and PN diodes are forward biased or reversed biased.

whether D1 . Given circuit is.in .co.nodia.. D1 is ON in this condition and V0 = 10 10 10 + 10 # = 5 volt SOL 8..com PAGE 474 ANALOG & DIGITAL ELECTRONICS CHAP 8 2 + (2 − vo) = 0 R 2R 4 + 2 − vo = 0 vo = 6 volt SOL 8. We can observe that diode D2 is always off. So equivalent circuit is.(1) So.IE = βIB V0 = 100I B 100 V0 IB = 10 # 103 .17 Option (A) is correct. Put IB into equation (1) GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www.www.16 Option (B) is correct.is on or off. By writing KVL equation for input loop (Base emitter loop) 10 − (10 kΩ) IB − VBE − V0 = 0 Emitter current IE = V0 100 IC .gatehelp.

co. Address performs two operations (1) PUSH PC & Save the contents of PC (Program Counter) into stack.3 − 2V0 = 0 V0 = 9. (PC) ! Addr GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www.7 − V0 = 0 10 # 103 9.65 A 2 SOL 8.nodia.com CHAP 8 ANALOG & DIGITAL ELECTRONICS PAGE 475 10 − (10 # 103) & V0 − 0. SOL 8. SP = SP − 2 (decrement) ((SP)) ! (PC) (2) Addr stored in PC.3 = 4.in . The circuit is Output Y is written as Y = X5B Since each gate has a propagation delay of 10 ns. CALL.18 Option (A) is correct.gatehelp.www.19 Option (D) is correct.

24 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www.21 Option (D) is correct. Since F = X Y + YZ In option (D) SOL 8. Option (B) is correct.20 Option (B) is correct.co.www.gatehelp. F = X Y + YZ SOL 8.nodia. Function F can be minimized by grouping of all 1’s in K-map as following.23 SOL 8.22 Option (A) is correct.com PAGE 476 ANALOG & DIGITAL ELECTRONICS CHAP 8 SOL 8. Figure shows current characteristic of diode during switching. The increasing order of speed is as following Magnetic tape> CD-ROM> Dynamic RAM>Cache Memory>Processor register Option (B) is correct.in . Equivalent circuit of given amplifier SOL 8.

For the given instruction set. Option (A) is correct.− 0 + V.in . it is a voltage-voltage feedback. Is = Vs − V0 R Is = RCs Vs R Is = jωCVs Is = ωCVs + + 90% Is = 2πf # 10 # 10 . F0 H & B = F0 H GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www. then V+ = V.25 Option () is correct. V.26 SOL 8.= Vs (ideal op-amp) In the circuit we have.gatehelp.− V0 (s) = 0 (1 + RCs) Vs = V0 (s) Similarly current Is is.+ V.www. So. voltage gain (A v) = 1 current gain (Ai) > 1 Power (Pout) = Av Ai Pin Since emitter follower has a high current gain so Pout > Pin SOL 8.co. leading by 90% SOL 8.com CHAP 8 ANALOG & DIGITAL ELECTRONICS PAGE 477 Feedback samples output voltage and adds a negative feedback voltage (vfb) to input.− V0 (s) = 0 1 R ` Cs j (RCs) V.nodia.28 Option (D) is correct.27 Option (D) is correct. XRA A & XOR A with A & A = 0 MVI B . SOL 8. Input and output power of a transformer is same Pin = Pout for emitter follower. NOR and NAND gates considered as universal gates.6 # 10 Is = 2 # π # 50 # 10 # 10 .6 # 10 Is = 10π mA. Let voltages at positive and negative terminals of op-amp are V+ and Vrespectively.

www. VOH =+ 6 volt VOL =− 3 volt Threshold voltages at non-inverting terminals of op-amp is given as VTH − 6 + VTH − 0 = 0 2 1 3VTH − 6 = 0 VTH = 2 V (Upper threshold) Similarly VTL − (− 3) VTL =0 + 2 1 3VTL + 3 = 0 VTL =− 1 V (Lower threshold) For Vin < 2 Volt.29 Option (D) is correct.30 Option (A) is correct.nodia. V0 =+ 6 Volt Vin > 2 Volt. V0 =− 3 Volt Vin < − 1 Volt V0 =+ 6 Volt Vin > − 1 Volt V0 =− 3 Volt Output waveform SOL 8. output can takes two states only.in .co.com PAGE 478 ANALOG & DIGITAL ELECTRONICS CHAP 8 SUB B & A A B 2’s complement of (− B) A + (− B) = A − B = A−B = 00000000 = 1111 0 0 0 0 = 0 0 010 0 0 0 = 0 0 010 0 0 0 = 10 H SOL 8. This is a schmitt trigger circuit.gatehelp. Assume the diode is in reverse bias so equivalent circuit is GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www.

co.gatehelp.nodia.com CHAP 8 ANALOG & DIGITAL ELECTRONICS PAGE 479 V0 = 10 sin ωt # 10 = 5 sin ωt 10 + 10 Due to resistor divider. In positive half cycle of input.7) =− 4. So. So it in reverse bias for given input.www. diode D1 is in forward bias and D2 is off.3 mA 1 SOL 8. voltage across diode VD < 0 (always). V0 = 5 sin ωt Output voltage SOL 8.3) = = 4. This is a current mirror circuit. IB1 = IB2 VB = (− 5 + 0.31 Option (C) is correct. Since β is high so IC1 = IC2. I = IC2 = IC1 0 − (− 4.3 volt Diode D1 is forward biased.in . the equivalent circuit is Capacitor C1 will charge upto + 5 volt. VC1 =+ 5 volt GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www.32 Option (D) is correct. current I is. Output.

33 Option () is correct. Now capacitor VC2 will charge upto − 10 volt in opposite direction.in .nodia. Let input Vin is a sine wave shown below According to given transfer characteristics of rectifiers output of rectifier P is.com PAGE 480 ANALOG & DIGITAL ELECTRONICS CHAP 8 In negative halt cycle diode D1 is off and D2 is on.co.gatehelp. SOL 8.www. Similarly output of rectifier Q is Output of a full wave rectifier is given as GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www.

vA − vi + vA − 0 = 0 R3 R4 2vA = vin . So. P should connected at inverting terminal of op-amp and Q with noninverting terminal.34 SOL 8. so 1 " 3 ωC Equivalent circuit is.gatehelp. SOL 8. Applying node equation at positive and negative input terminals of op-amp. Option (C) is correct. then 1 " 0 ωC Equivalent circuit is. For low frequencies. vA − vi + vA − vo = 0 R1 R2 2vA = vi + vo . ω " 0 .www.nodia.co.35 Option () is correct. For high frequencies.in . GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 a R1 = R 2 = R A a R 3 = R 4 = RB Visit us at: www.com CHAP 8 ANALOG & DIGITAL ELECTRONICS PAGE 481 To get output V0 V0 = K (− VP + VQ) K − gain of op-amp So. vo = 0 It will stop low frequency signals. ω " 3 . Similarly.

equivalent circuit is. So this is is Band pass filter. SOL 8.com PAGE 482 ANALOG & DIGITAL ELECTRONICS CHAP 8 Output.gatehelp. vo = vi So it will pass high frequency signal. SOL 8.7. In Q. 3. F is written as F = Σm (1. 6) = X Y Z + X YZ + XY Z + XYZ Solving from K.36 Option (D) is correct.co. 1 ωh = 2πRA C Here given circuit is a low pass filter with cutoff frequency.21 cutoff frequency of high pass filter is given by. This is a high pass filter.in .37 Option (B) is correct. amplitude response is given by. 1 2 ωL = = R 2 R π A AC 2π C 2 ωL = 2ωh When both the circuits are connected together. 5. In SOP form.www.nodia.map GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www.

10 − IC (1 # 103) − 0.0 Visit us at: www.gatehelp.050 mA β 100 IB 1 IB (sat). ` IC = βIB IB (β + 270) = 9.7 − 270 # 103 IB = 0 βIB + 270 IB = 9.3 mA = 0. base current is given by.025 mA 270 + 100 In saturation. Given that SP = 2700 H PC = 2100 H HL = 0000 H Executing given instruction set in following steps.nodia. PC = 2700 H. DAD SP & Add register pair (SP) to HL register HL = HL + SP HL = 0000 H + 2700 H HL = 2700 H PCHL & Load program counter with HL contents PC = HL = 2700 H So after execution contents are.in .co. HL = 2700 H SOL 8.38 Option (B) is correct. IB (sat) = GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 IC .39 Option (D) is correct. so transistor is in forward active region.3 mA IB = 9. By applying KVL for input loop. If transistor is in normal active region.3 mA. base current can be calculated as following.com CHAP 8 ANALOG & DIGITAL ELECTRONICS PAGE 483 F = X Z + Y Z + XYZ In POS form F = (Y + Z) (X + Z) (X + Y + Z ) Since all outputs are active low so each input in above expression is complemented F = (Y + Z ) (X + Z ) (X + Y + Z) SOL 8. 10 − IC (1) − VCE − IE (1) = 0 10 = I C (sat) 2 IC (sat) = 5 mA IC (sat) = 5 = .IE VCE .www.

Output current depends on input voltage.6 amp Option (D) is correct.6 6. IE = IB + IL IE = 6 − 6.co.www.com PAGE 484 ANALOG & DIGITAL ELECTRONICS CHAP 8 SOL 8.6 + 6 . PT = VCE # IC = 4 # 0.= v1 Writing node equation.41 ` IC .40 Option (B) is correct. v1 − v + v1 − 0 = 0 R1 R2 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www. Since op-amp is ideal v+ = v. VBE (ON) = 0.6 VE = 6.6 volt VB − VE = 0.6 = 6 volt At emitter (by applying KCL).IE = 0.in .6 = 2.6 amp 1 kΩ 10 Ω VCE = VC − VE = 10 − 6 = 4 volt Power dissipated in transistor is given by. In the circuit We can analyze that the transistor is operating in active region.gatehelp. This is a voltage-to-current converter circuit.6 − 0.0.nodia.4 W SOL 8.6 − VE = 0.

in . at inverting terminal of opamp) is given by vc (t) = vc (3) + [vc (0) − vc (3)] e vc (t) = 20 (1 − e ) Voltage at positive terminal of op-amp GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 -t RC -t RC Visit us at: www.nodia.com CHAP 8 ANALOG & DIGITAL ELECTRONICS PAGE 485 v1 c R1 + R2 m = V R1 R1 R2 R2 R1 + R2 m Since the op-amp is ideal therefore iL = i1 = v1 = V c R2 m r R1 + R2 r v1 = V c SOL 8. for t " 3 (steady state) for t < 0 (initial) So at any time t . This is a class-B amplifier whose efficiency is given as η = π VP 4 VCC where VP " peak value of input signal VCC " supply voltage here VP = 7 volt. SOL 8. VCC = 10 volt so.42 Option (D) is correct.44 Option (B) is correct. In the circuit output Y is given as Y = [A 5 B] 5 [C 5 D] Output Y will be 1 if no. of 1’s in the input is odd.43 Option () is correct. In the circuit the capacitor starts charging from 0 V (as switch was initially closed) towards a steady state value of 20 V.e.95% .55% 10 4 SOL 8.www.co. η = π # 7 # 100 = 54.gatehelp. voltage across capacitor (i.

t/RC 22 t = RC ln ` 22 j = 1 # 103 # . charging of capacitor occurs through resistor (RA + RB) and discharging through resistor RB only. AB.com PAGE 486 ANALOG & DIGITAL ELECTRONICS CHAP 8 v+ − vout v+ − 0 =0 + 10 100 v+ = 10 vout 11 Due to zener diodes.45 Option (B) is correct. Hexadecimal no.46 Option (B) is correct.t/RC ) = 10 # 5 11 1 − e . (AB.co.632) 8 SOL 8. then binary to octal. CD 1 0 10 S 1 0 11 $ 1 10 11 0 1 Binary equivalent S A BB B0 CS C A B D To convert in octal group three binary digits together as shown 0 1 0 1 0 1 0 11 $ 11 0 0 11 0 1 0 SSSSSS 5 2 3 6 3 2 So. GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www. So 20 (1 − e .CD) H = (253.in .nodia. First convert the given number from hexadecimal to its binary equivalent.01 # 10 .6 # 0. In a 555 astable multi vibrator circuit.www.257 = 2. Time for charging and discharging is given as.57 μsec 17 Voltage waveforms in the circuit is shown below SOL 8.t/RC = 5 22 17 = e . − 5 # vout # + 5 So.gatehelp. v+ = 10 (5) V 11 Transistor form − 5 V to + 5 V occurs when capacitor charges upto v+ .

GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www.www.693 RB C But in the given circuit the diode will go in the forward bias during charging. In the positive half cycle of input.693 (RA + RB) C = 0. Let diode D2 is OFF then the circuit is In the above circuit diode D1 must be ON. First we can check for diode D2 . Diode D1 will be reverse biased and equivalent circuit is.47 RA = RB TC = TD Option (A) is correct. so the capacitor will charge through resistor RA only and discharge through RB only.com CHAP 8 ANALOG & DIGITAL ELECTRONICS PAGE 487 TC = 0. as it is connected with 10 V battery now the circuit is Because we assumed diode D2 OFF so voltage across it VD2 # 0 and it is possible only when D3 is off.nodia.in . a So SOL 8. all assumptions are true.48 Option (D) is correct. So. SOL 8.gatehelp.co.

= 0 and VP = Vγ = 0. diode D1 is in forward bias and equivalent circuit is shown below. both D1 and D2 are off.nodia.in .co. GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www.gatehelp.www. In the circuit when Vi < 10 V. Input is applied at inverting terminal so. VP =− VCC =− 12 V In negative half cycle of input. So equivalent circuit is. Output VP = Vγ + VOp-amp is at virtual ground so V+ = V.49 Option (A) is correct.7 V Voltage wave form at point P is SOL 8.com PAGE 488 ANALOG & DIGITAL ELECTRONICS CHAP 8 Since there is no feed back to the op-amp and op-amp has a high open loop gain so it goes in saturation.

nodia. Vo = 10 volt When Vi > 10 V ( D1 is in forward bias and D2 is off So the equivalent circuit is. Assume that BJT is in active region.com CHAP 8 ANALOG & DIGITAL ELECTRONICS PAGE 489 Output.co. thevenin equivalent of input circuit is obtained as Vth − Vi + Vth − (− 12) = 0 15 100 20Vth − 20Vi + 3Vth + 36 23Vth Vth Thevenin resistance Rth So the circuit is GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 =0 = 20 # 5 − 36 .78 V = 15 KΩ || 100 KΩ = 13.www.gatehelp. Output.04 KΩ Visit us at: www. Vo = Vi Transfer characteristic of the circuit is SOL 8.in .50 Option (B) is correct. Vi = 5 V = 2.

writing node equation at positive terminal of op-amp Vth − 12 + Vth − 0 = 0 10 10 Vth = 6 volt (Positive threshold) GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www.com PAGE 490 ANALOG & DIGITAL ELECTRONICS CHAP 8 Writing KVL for input loop 2.in .4 mA 2. equivalent circuit is.78 − Rth IB − 0. therefore assumption is true.157 mA Current in saturation is given as.7 = 0 IB = 0. Here output of the multi vibrator is V0 = ! 12 volt Threshold voltage at positive terminal of op-amp can be obtained as following When output V0 =+ 12 V.2 So.gatehelp.www.51 Option (C) is correct.181 mA 30 Since IB (sat) > IB .45 mA = 0.co. SOL 8. I IB (sat) = C (sat) β IC (sat) = 12.2 = 5.nodia. IB (sat) = 5.

the capacitor will charge upto 6 volt. 2.com CHAP 8 ANALOG & DIGITAL ELECTRONICS PAGE 491 So.www.nodia. At terminal P voltage waveform is. F = I0 S1 S0 + I1 S1 S0 + I2 S1 S0 + I3 S1 S0 = AB C + A B C + 1 $ BC + 0 $ BC = AB C + A BC + BC = AB C + A BC + BC (A + A) = AB C + A BC + ABC + A BC = Σ (1.54 Option () is correct. When output V0 =− 12 V. Option () is correct.co. Function F can be obtain as.53 SOL 8. SOL 8. the equivalent circuit is. 6) GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www.in .gatehelp. node equation Vth + 12 + Vth − 0 = 0 2 10 5 Vth + 60 + Vth = 0 Vth =− 10 volt (negative threshold) So the capacitor will discharge upto − 10 volt.52 SOL 8. Option (A) is correct. 4.

DCR L decrements L by 1 and JNZ checks whether the value of L is zero or not. since L is of 8 bit so no more decrement possible and it terminates. SHLD transfers contain of HL pair to memory location.59 Visit us at: www. so equivalent circuit is. This is a N-channel MOSFET with VGS = 2 V VTH =+ 1 V VDS (sat) = VGS − VTH VDS (sat) = 2 − 1 = 1 V GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 SOL 8. Option (A) is correct. Voltage Vn is given by Vn = 1 # 2 = 2 Volt Vp = 0 Vn > Vp (so diode is in reverse bias. assumption is true) Current through D2 is ID2 = 0 SOL 8. INR M & Increment the contents of memory whose address is stored in HL pair. Exchange the contain of DE register pair with HL pair So now addresses of memory locations are stored in HL pair.www. MVI H and MVI L stores the value 255 in H and L registers.gatehelp. Let assume that D2 is in reverse bias.55 Option (A) is correct. So DCR L executed 255 times till value of L becomes ‘0’. SOL 8. SHLD 2050 & L " M [2050H] H " M [2051H] Option (D) is correct.co. From the circuit we can observe that Diode D1 must be in forward bias (since current is flowing through diode).58 Option (C) is correct. Then DCR H will be executed and it goes to ‘Loop’ again.57 Option (A) is correct.com PAGE 492 ANALOG & DIGITAL ELECTRONICS CHAP 8 SOL 8.56 XCHG & SOL 8.in .nodia.

62 Option (C) is correct.nodia. Q (t + 1) = D = Q (t) 5 X = Q (t) X + Q (t) X = Q (t). so input to D-flip flop is given by. Let the present state is Q(t). if X = 1 Q (t + 1) = Q (t). RF = 1 MΩ R1 R1 R1 =− 1 # 10 Av Av =− 10 to − 25 so value of R1 6 R1 = 10 = 100 kΩ 10 6 ' R1 = 10 = 40 kΩ 25 6 for Av =− 10 for Av =− 25 R1 should be as large as possible so R1 = 100 kΩ SOL 8. So. SOL 8. βIB IB = IE = 1 mA = 10 μA β 100 SOL 8. channel conductivity is high and a high current flows through drain to source and it acts as a short circuit. Gain of the inverting amplifier is given by.co.gatehelp. IE . D = Q (t) 5 X Next state can be obtained as.60 Option (C) is correct. if X = 0 and So the circuit behaves as a T flip flop.61 Option (B) is correct. Direct coupled amplifiers or DC-coupled amplifiers provides gain at dc or very low frequency also.com CHAP 8 ANALOG & DIGITAL ELECTRONICS PAGE 493 Due to 10 V source VDS > VDS (sat) so the NMOS goes in saturation.in . Since the transistor is operating in active region. 6 Av =− RF =− 1 # 10 .63 Option (B) is correct.www. Vab = 0 SOL 8. GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www.

for X1 = 0. Since there is no feedback in the circuit and ideally op-amp has a very high value of open loop gain. Option (B) is correct. In option (C). the next state is given by Q (t + 1) = Q (t) (unstable) SOL 8.com PAGE 494 ANALOG & DIGITAL ELECTRONICS CHAP 8 SOL 8.65 CHECK SOL 8.gatehelp. Q4 and Q5 are in parallel works as an OR circuit and Q2 is an output inverter. Option (D) is correct. Q = 0 so it is eliminated. Q = 0 (always). So output is Q = X1 + X2 = X1 . Only option (B) satisfies the truth table. The input is applied to negative terminal of op-amp.nodia. Q = 1. so it is also eliminated.68 Option (B) is correct. so it goes into saturation (ouput is either + V or − V ) for small values of input. Let Q (t) is the present state then from the circuit.www. for X1 = 1.64 Option (C) is correct.X2 SOL 8. which does not match the truth table. From the given input output waveforms truth table for the circuit is drawn as X1 X2 Q 1 0 1 0 0 1 0 1 0 In option (A). In the given circuit NMOS Q1 and Q3 makes an inverter circuit. for X1 = 0.in . In option (D).67 Option (D) is correct.66 SOL 8.co. so in positive half cycle it saturates to − V and in negative half cycle it goes to + V . Trans-conductance of MOSFET is given by gm = 2iD 2VGS GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www. So.

In the circuit V1 = 3.5 − 3.www.70 vo =− gm vgs RD vgs = vin vo =− gm RD vin Av = vo =− gm RD =− (1 mS) (10 kΩ) =− 10 vi Option (C) is correct.3 = 2 mA RZ 0. Voltage gain can be obtain by small signal equivalent circuit of given amplifier.69 Option (D) is correct. IZ = V1 − VZ = 3. Given circuit.co. Since VBE is the same in both devices.com CHAP 8 ANALOG & DIGITAL ELECTRONICS PAGE 495 = (2 − 1) mA = 1 mS (2 − 1) V SOL 8.71 Option (C) is correct. This is a current mirror circuit. and transistors are perfectly matched.1 # 103 SOL 8. GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www.in .5 V (given) Current in zener is.gatehelp. So.nodia. Voltage gain SOL 8. then IB1 = IB2 and IC1 = IC2 From the circuit we have.

4. In the given circuit output is stable for both 1 or 0. GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www.nodia.72 Option (B) is correct. So it is a bistable multivibrator.com PAGE 496 ANALOG & DIGITAL ELECTRONICS CHAP 8 IR = IC1 + IB1 + IB2 = IC1 + 2IB2 = IC2 + 2IC2 β IR = IC2 c1 + 2 m β IR IC2 = I = 2 c1 + β m IR can be calculate as . 3 I = .3 mA 2 1 + ` 100 j a IB1 = IB2 a IC1 = IC2. The small signal equivalent circuit of given amplifier Here the feedback circuit samples the output voltage and produces a feed back current Ifb which is in shunt with input signal.gatehelp. So this is a shunt-shunt feedback configuration. SOL 8.3 mA IR = − 5 + 03 1 # 10 4. IC2 = βIB2 So.73 Option (A) is correct.www.in .7 =− 4. SOL 8.co.

For D1 let assume it is in reverse bias.5 Vn = 0 Vp < Vn (so the assumption is true and D1 is in reverse bias) and current in D1 ID1 = 0 mA SOL 8. From the circuit. The small signal ac equivalent circuit of given amplifier is as following.co.www.76 Option (D) is correct.in . Here RB = (10 kΩ < 10 kΩ) = 5 kΩ ISBN: 9788192276243 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.75 Option (C) is correct.74 Option (A) is correct. we can see the that diode D2 must be in forward Bias. For an n -bit Quantizer 2n = No.gatehelp. of levels 2n = 2 n =1 SOL 8. Voltages at p and n terminal of D1 is given by Vp and Vn Vp < Vn ( D1 is reverse biased) Applying node equation Vp − 5 Vp + 8 =0 + 1 1 2Vp =− 3 Vp =− 1. Since there are two levels (+ VCC or − VCC ) of output in the given comparator circuit.com CHAP 8 ANALOG & DIGITAL ELECTRONICS PAGE 497 SOL 8.

. If op-amp is ideal. So current ix is v − vy .co..5 kΩ SOL 8. no current will enter in op-amp.(2) Visit us at: www.(1) ix = x 1 # 106 (ideal op-amp) v+ = v− = vx vx − vy + vx − 0 3 = 0 3 100 # 10 10 # 10 vx − vy + 10vx = 0 11vx = vy For equation (1) & (2) x x ix = vx − 11v =− 10v 6 6 1 # 10 10 Input impedance of the circuit. Option (B is correct.3 Input resistance Rin = RB < rπ = 5 kΩ < 5 kΩ = 2. VSD VS − VD 4 − ID R 1 ID R R > 1000 Ω = 3 Volt <3 <3 <3 < ID R > 1.gatehelp.www.78 SOL 8.79 Option () is correct.. "a VSG = 4 − 0 = 4 volt ID = 1 mA SOL 8.77 Option (D) is correct.. For PMOS to be biased in non-saturation region. 6 Rin = vx =− 10 =− 100 kΩ 10 ix GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 .nodia. VSD < VSD(sat) and VSD(sat) = VSG + VT VSD(sat) = 4 − 1 So.in .com PAGE 498 ANALOG & DIGITAL ELECTRONICS CHAP 8 gm = 10 ms 50 a gm rπ = β & rπ = = 5 kΩ 10 # 10 .

START MVI A.gatehelp. SOL 8. The program is executed in following steps.80 Option (A) is correct. In the given circuit. Given Boolean expression.82 Option (B) is correct.83 Option (C) is correct. Y = (A0 5 B0) 9 (A1 5 B1) 9 (A2 5 B2) 9 (A3 5 B3) For option (A) Y = (1 5 1) 9 (0 5 0) 9 (1 5 1) 9 (0 5 0) = 0909090 = 1 For option (B) Y = (0 5 0) 9 (1 5 1) 9 (0 5 0) 9 (1 5 1) = 0909090 = 1 For option (C) Y = (0 5 0) 9 (0 5 0) 9 (1 5 1) 9 (0 5 0) = 0909090 = 1 For option (D) Y = (1 5 1) 9 (0 5 0) 9 (1 5 1) 9 (0 5 1) = 0909091 = 0 SOL 8. RLC & rotate accumulator left without carry RLC is executed 6 times till value of accumulator becomes zero. it is executed 5 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www.com CHAP 8 ANALOG & DIGITAL ELECTRONICS PAGE 499 SOL 8. waveforms are given as. output is given as. 14H " one instruction cycle. JNZ. Y = (A $ BC + D) (A $ D + B $ C ) = (A $ BCD) + (ABC $ B $ C ) + (AD) + B C D = A BCD + AD + B C D = AD (BC + 1) + B C D = AD + B C D SOL 8.81 Option (D) is correct.co.in .nodia. In the given circuit. JNZ checks whether accumulator value is zero or not.www.

So total no.in .25 5 − IC RC V0 =0 =0 = 1.35 = 1. HALT " 1-instruction cycle. 5 − IC RC − VCE (sat) − 1. In the given circuit Vi = 0 V So.www. of instruction cycles are n = 1+6+5+1 = 13 SOL 8.84 Option (B) is correct.1 − 1.25 5 − IC RC − 0.35 "a V0 = 5 − IC RC GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www.gatehelp.co.com PAGE 500 ANALOG & DIGITAL ELECTRONICS CHAP 8 times.nodia. transistor Q1 is in cut-off region and Q2 is in saturation.

Applying KVL in input loop.3 # 103) (hfe + 1) IB = 0 3.= vin + vout Similarly.− vout = 0 R1 R1 2 v-.7 − (3.3 3.gatehelp. v.co. Option (B) is correct.3 SOL 8. Let the voltages at positive and negative terminals of op-amp are v+ and vrespectively.3] # 100 0.33 + 3.3 # 103 # 100 IC = hfe IB 99 # 3.3 = mA = mA [0. so it is a depletion mode device. v+ − vin v −0 =0 + + R 1 c jωC m GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 .3 # 103) (99 + 1)@ IB 3.33 + 3.3 # 103) IE = 0 a IE = (hfe + 1) IB 4 − (33 # 103) IB − 0.com CHAP 8 ANALOG & DIGITAL ELECTRONICS PAGE 501 SOL 8. ID increases for negative values of gate voltages so it is a p -type depletion mode device.in .86 SOL 8.(1) Visit us at: www.3 IB = 33 # 103 + 3.87 Option (D) is correct.nodia. Since there exists a drain current for zero gate voltage (VGS = 0)..85 Option (C) is correct. 4 − (33 # 103) IB − VBE − (3.www. Then by applying nodal equations.− vin + v.3 = 6(33 # 103) + (3.

. I3 = Cin SOL 8.1 (ωCR) θ =π Option (C) is correct.1 (ωCR) − tan . P 0 0 0 0 1 1 1 1 Q 0 0 1 1 0 0 1 1 Cin 0 1 0 1 0 1 0 1 Sum 0 1 1 0 1 0 0 1 Sum = P Q Cin + PQ Cin + P Q Cin + P Q Cin Output of MUX can be written as F = P Q $ I0 + PQ $ I1 + PQ $ I2 + PQ $ I3 Inputs are.in .(2) "a v+ = v. so output of MUX is given by. F = Sum = A 5 Q 5 Cin Truth table can be obtain as. Program counter contains address of the instruction that is to be executed next.com PAGE 502 ANALOG & DIGITAL ELECTRONICS CHAP 8 v+ − vin + v+ (jωCR) v+ (1 + jωCR) By equation (1) & (2) 2vin 1 + jωCR 2 − 1E vin . 1 + jωCR =0 = Vin = vin + vout = vout (1 − jωCR) 1 + jωCR .89 Option (D) is correct.gatehelp. GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www.co.1 (ωCR) Maximum phase shift SOL 8. I2 = Cin. I1 = Cin.www. In given circuit MUX implements a 1-bit full adder.nodia.1 (ωCR) = π − tan .88 = π − 2 tan .1 (− ωCR) − tan .(ideal op-amp) vout = vin Phase shift in output is given by θ = tan . I0 = Cin.

com CHAP 8 ANALOG & DIGITAL ELECTRONICS PAGE 503 SOL 8.84 mA SOL 8. So.in . ID = K (VGS − VTH ) 2 4 = K (VGS − 2) 2 VGS is given by VGS = VDS = 10 − ID RD = 10 − 4 # 1 = 6 Volt 4 = K (6 − 2) 2 K =1 4 ' ' ' Now RD is increased to 4 kΩ .gatehelp.nodia.91 Option (D) is correct. VDS = VGS So VDS (sat) = VDS − 2 & VDS = VDS (sat) + 2 VDS > VDS (sat) Therefore transistor is in saturation region and current equation is given by.90 Option (A) is correct.co. So.and v+ respectively. Let current is ID and voltages are VDS = VGS Applying current equation. For a n -channel enhancement mode MOSFET transition point is given by.= 0 (ideal op-amp) GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www. Let the voltages at input terminals of op-amp are v. VDS (sat) = VGS − VTH a VTH = 2 volt VDS (sat) = VGS − 2 From the circuit. v+ = v.www. ' ' ' 2 4I D = (10 − 4ID − 2) 2 = (8 − 4ID ) ' 2 = 16 (2 − ID ) ' 2 ' ID = 4 (4 + I'D − 4ID ) 2 4I ' D − 17 + 16 = 0 2 I' D = 2. ' ' ID = K (VGS − VTH ) 2 ' ' ID = 1 (VGS − 2) 2 4 ' ' ' ' ' VGS = VDS = 10 − 4ID = 10 − ID # RD So.

SOL 8.in .co. In the positive half cycle (when Vin > 4 V ) diode D2 conducts and D1 will be off so the equivalent circuit is.92 Option (D) is correct.. Vout = + 4 Volt In the negative half cycle diode D1 conducts and D2 will be off so the circuit is.www..nodia. Applying KVL Vin − 10I + 4 − 10I = 0 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www. 0 − vin + 0 − vx = 0 1 10 At node x vx − 0 + vx − vout + vx − 0 = 0 10 10 1 vx + vx − vout + 10vx = 0 12 vx = vout vx = vout 12 vin + vx = 0 1 10 vin =− vout 120 vout =− 120 vin .(1) From equation (1).gatehelp.com PAGE 504 ANALOG & DIGITAL ELECTRONICS CHAP 8 Applying node equation at negative terminal of op-amp.

.(1) and SOL 8.693 (RA + RB) C TD = 0..693 (RA + 2RB) # 10 # 10 .www.75 T 0.in . Given boolean expression can be written as.9 14.4 # 103 = RA + 2RB duty cycle = TC = 0.21 kΩ RB = 3.94 Option (B) is correct.gatehelp..co. Charging and discharging time is given as.60 kΩ .693 RB C Frequency 1 1 f= 1 = = T TD + TC 0. TC = 0.693 (RA + 2RB) C 1 = 10 # 103 0.nodia.93 Option (C) is correct..693 (RA + RB) C =3 0. In the circuit.693 (RA + 2RB) C 4 4RA + 4RB = 3RA + 6RB RA = 2RB From (1) and (2) 2RA = 14.(2) .com CHAP 8 ANALOG & DIGITAL ELECTRONICS PAGE 505 Vin + 4 = I 20 Vin =− 10 V (Maximum value in negative half cycle) So. I = − 10 + 4 =− 3 mA 20 10 Vin − Vout = I 10 − 10 − Vout =− 3 10 10 Vout =− (10 − 3) Vout =− 7 volt SOL 8.4 # 103 RA = 7. F = XYZ + X Y Z + XY Z + XYZ + XYZ = X YZ + Y Z (X + X ) + XY (Z + Z) = XYZ + Y Z + XY = Y Z + Y (X + X Z ) a A + BC = (A + B) (A + C) GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www. the capacitor charges through resistor (RA + RB) and discharges through RB .

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PAGE 506

ANALOG & DIGITAL ELECTRONICS

CHAP 8

= Y Z + Y (X + X ) (X + Z ) = Y Z + Y (X + Z ) = Y Z + YX + YZ

SOL 8.95

Option (B) is correct.

X = X1 5 X 0 , Y = X 2 Serial Input Z = X 5 Y = [X1 5 X0] 5 X2 Truth table for the circuit can be obtain as. Clock pulse Initially 1 2 3 4 5 6 Serial Input 1 0 0 0 1 0 1 Shift register 1010 1101 0110 0011 0001 1000 0100

**7 1 1010 So after 7 clock pulses contents of the shift register is 1010 again.
**

SOL 8.96

**Option (D) is correct. Characteristic table of the X-Y flip flop is obtained as. X 0 0 0 0 1 1 1 1 Y 0 0 1 1 0 0 1 1 Qn 0 1 0 1 0 1 0 0 Qn+1 1 1 0 1 1 0 0 0
**

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CHAP 8

ANALOG & DIGITAL ELECTRONICS

PAGE 507

Solving from k-map

Characteristic equation of X-Y flip flop is Qn + 1 = Y Qn + XQn Characteristic equation of a J-K flip-flop is given by Qn + 1 = KQn + J Qn by comparing above two characteristic equations J =Y, K=X

SOL 8.97

Option (A) is correct. Total size of the memory system is given by. = (212 # 4) # 8 bits = 214 # 8 bits = 214 Bytes = 16 K bytes

SOL 8.98

Option (C) is correct. Executing all the instructions one by one. LXI H, 1FFE MOV B, M & B INR L & L MOV A, M & A ADD B & A INR L & L & H = (1F) H, L = (FE) H = Memory [HL] = Memory [1FFE] = L + (1) H = (FF) H = Memory [HL] = Memory [1FFF] = A+B = L + (1) H = (FF) H + (1) H = 00

**MOV M, A & Memory [HL] = A Memory [1F00] = A XOR A & A = A XOR A = 0 So the result of addition is stored at memory address 1F00.
**

SOL 8.99

Option (D) is correct. Let the initial state Q(t) = 0, So D = Q = 1, the output waveform is.

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PAGE 508

ANALOG & DIGITAL ELECTRONICS

CHAP 8

**So frequency of the output is, f f out = in = 10 = 5 kHz 2 2
**

SOL 8.100

Option (A) is correct. This is a half-wave rectifier circuit, so the DC voltage is given by Vdc = Vm π Equivalent circuit with forward resistance is

DC current in the circuit Idc Idc Vm (Vm /π) = π = rf + R (5 + 45) = Vm 50π

SOL 8.101

Option (B) is correct. In the positive half cycle zener diode ( Dz ) will be in reverse bias (behaves as a constant voltage source) and diode (D) is in forward bias. So equivalent circuit for positive half cycle is.

Vo = VD + Vz = 0.7 + 3.3 = 4 Volt In the negative halt cycle, zener diode (Dz ) is in forward bias and diode (D) Output GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia

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25 H (jω) = Given that 1 =1 2 2 2 4 ω1 C R +1 2 2 2 16 = ω1 R C +1 2 2 2 ω1 R C = 15 4π2 f12 (50) 2 (5 # 10 .gatehelp. A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1110 0000 0000 0000 h h h h 1110 1111 1111 1111 So address range is E000-EFFF SOL 8.in .103 Option (C) is correct.6) 2 = 15 f 1 = 2. A first order low pass filter is shown in following figure. Transfer function V0 (jω) 1 1 = # 1 = j ω cR +1 V1 (jω) 1 j ω C R+ jω C H (jω1) = 0. Vo = 10 # 1 (1 + 1) Vo = 5 Volt SOL 8.46 kHz GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www.com CHAP 8 ANALOG & DIGITAL ELECTRONICS PAGE 509 is in reverse bias mode. For active low chip select CS = 0 .www.co. so the address range can be obtain as.102 Option (A) is correct. So equivalent circuit is. So the peak output is.nodia.

So final output Y is. voltage at positive terminal of op-amp is given by v+ − vo v+ − 2 =0 + 10 3 3 (v+ − vo) + 10 (v+ − 2) = 0 13v+ = 20 + 3vo Output changes from + 15 V to − 15 V .www.in .co.gatehelp.99 mA I = IC = (β + 1) E (99 + 1) In the circuit GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www.106 a AB = A + B Option (B) is correct.105 Option (B) is correct.when v.nodia.> v+ 20 + (3 # 15) v+ = = 5 Volt (for positive half cycle) 13 SOL 8.com PAGE 510 ANALOG & DIGITAL ELECTRONICS CHAP 8 SOL 8. We can analyze that the transistor is in active region.104 Option (A) is correct. Output for each stage can be obtain as. β 99 (1 mA) = 0. In the circuit. Y = P Q $ R S = (P + Q) $ (R + S) = P+Q+R+S SOL 8.

7 V VE = IE # 1 kΩ VB − VE = 0.gatehelp.109 Option (A) is correct.9 kΩ SOL 8.1 mA) (1 kΩ) = 13.7 volt Current through R1 IR = VB = 1.7 + 1 = 1. Output voltage V0 = 15 − I1 RC = 15 − (1.107 Option (D) is correct.nodia.9 − 1.108 Option (A) is correct.in .7 = 100 μA 17 kΩ 17 kΩ IB = IE = 1 mA = 10 μA β+1 (99 + 1) Current through RF .99 mA + 110 μA = 1.co. By writing node equations in the circuit GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www.7 VB = 0.1 mA SOL 8.www. by writing KCL at Base 1 =1V IRF = IB + IR1 = 10 + 100 = 110 μA Current through RC I1 = IC + IRF = 0.com CHAP 8 ANALOG & DIGITAL ELECTRONICS PAGE 511 In the circuit VBE = 0.9 V SOL 8. Current in RF IRF = V0 − VB RF 0.11 mA = 13.7 kΩ RF RF = 110.

110 Option (A) is correct.www. Vy V0 R RF + R V0 R RF + R V jω0 CR = y = 2 V0 1 − ω0 C2 R2 + j3ω0 CR = 1 RC j = =1 3j 3 =1 3 RF = 2R = 2 # 1 = 2 kΩ GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www. 1 − C2 R2 ω2 0 = 0 1 R C2 ω0 = 1 RC ω2 0 = 2 SOL 8.. − sCR E = Vx sCR Vy (1 + 3sCR + 2s2 C2 R2 − s2 C2 R2) = Vx sCR T (s) = Vy sCR = Vx 1 + 3sCR + s2 C2 R2 jωCR jωCR T (jω) = = 2 2 2 2 2 2 1 + j3ωCR − C R ω (1 − C R ω ) + 3jωCR Transfer function SOL 8.gatehelp..co.111 Option (C) is correct. Applying Barkhausen criterion of oscillation phase shift will be zero. +T (jω0) = 0 ω0 " frequency of oscillation.(2) .com PAGE 512 ANALOG & DIGITAL ELECTRONICS CHAP 8 Va − Vx + V Cs + (V − V ) Cs = 0 a a y R or or Va (1 + 2RCs) − Vx − sCRVy = 0 (Vy − Va) Cs + Vy =0 R ..(1) or Vy (1 + sCR) − Va sCR = 0 From equation (1) & (2) 1 + sCR c sCR m (1 + 2sCR) Vy − Vx − sCRVy = 0 (1 + sCR) (1 + 2sCR) Vy .. In figure Vy = T (jω) ω So.nodia.in .

SOL 8. output of NAND gate becomes 0 or CLR = 0.e.com CHAP 8 ANALOG & DIGITAL ELECTRONICS PAGE 513 SOL 8.writing KVL in the circuit.nodia. i = 106 t After a duration of TON the current will be maximum given as i Peak = 106 TON When the switch is opened (i. Thus it is modulo 4 counter.112 Option (C) is correct.gatehelp. writing KVL again 500 =− (100 # 10− 6) di dt i =− 5 # 106 t + i (0) GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www.co.e. during TON ) the equivalent circuit is Diode is off during TON .www. so all FFs are reset.in . 100 − (100 # 10− 6) di = 0 dt di = 106 dt i = # 106 dt = 106 t + i (0) Since initial current is zero i (0) = 0 So.113 Option (A) is correct. When the switch is closed (i. When it goes to state 101. By writing truth table for the circuit CLK Initially 1 2 3 4 Q2 0 0 0 0 1 Q1 0 0 1 1 0 Q0 0 1 0 1 0 1 0 1 All flip flops are reset. during Toff ) the equivalent circuit is Diode is ON during Toff .

co.gatehelp.33 μ sec 1.114 Option (C) is correct. & Given that 0 =− 5 # 106 t Toff + 106 TON TON = 5 Toff TON + Toff = 100 μ sec TON + TON = 100 μ sec 5 TON = 100 = 63. current i = 0 So. When the switch is opened.com PAGE 514 ANALOG & DIGITAL ELECTRONICS CHAP 8 i (0) = i p = 106 TON So.33 # 10− 6 # 106 = 63.2 Peak current i p = 106 # TON = 63. current flows through capacitor and diode is ON in this condition. so the equivalent circuit during TOFF is & Initially I = C dVc dt Vc = I t + Vc (0) C Vc (0) = 0 Vc = I t C t = Toff Vc = I Toff C TON D = = TON TON + TOFF T TON = DT TOFF = T − TON = T − DT At Duty cycle GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www.www.in .33 A SOL 8. i =− 5 # 106 t + 106 TON After a duration of Toff .nodia.

in .nodia. In the circuit ib = vs hie vo = hfe ib . Equivalent hybrid circuit of given transistor amplifier when RE is by passed is shown below. # b−C t l dt + T 0 ON a dVc = I dt C #0 TOFF 0 dtE 2 DT 2 2 2 =− 1 . I . When the switch is closed.gatehelp.T 2 T C 2 0 T C C 2 SOL 8.RC hie GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 .116 Option (B) is correct.co..com CHAP 8 ANALOG & DIGITAL ELECTRONICS PAGE 515 Vc = I (T − DT) C = I (1 − D) T C During TOFF . I :t D =− 1 . SOL 8. D T =− I D . So.(1) Visit us at: www.115 Option (B) is correct. diode is off and the circuit is In steady state condition C dVc = I2 dt I2 = C I C V0 =− Vc = − I t C Average output voltage DT = T I V0 = 1 .www.RC = hfe . output voltage V0 = 0 volt .. vs .

(3) SOL 8. F = A 9 B (Ex-NOR) Output is 1 when A = B = 0 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www.gatehelp.RC from equation (2) and (3) vs hie + (1 + hfe) RE hfe RC Voltage gain.in .RC Av < Av 2 1 ..co... F = A + B (NOR) Output is 1 when A = B = 0 OR.www. Av2 = v0 = vs hie + (1 + hfe) RE Av1 = hie + (1 + hfe) RE = 1 + (1 + hfe) RE So hie hie Av2 v0 = hfe .118 Option (D) is correct. So it is slowest.(2) .nodia. 1 In the circuit vs = ib hie + (ib + hfe ib) RE vs = ib [hie + (1 + hfe) RE ] v0 = hfe ib .117 Option (C) is correct.. Conversion time for different type of ADC is given as Counting type TT " Conversion time TT = 2n TC TC " Clock period Integrating type TT = 2n + 1 TC Successive Approximation type TT = nTC Parallel (flash) type " fastest Conversion time is highest for integrating type ADC. SOL 8.com PAGE 516 ANALOG & DIGITAL ELECTRONICS CHAP 8 h R Voltage gain Av = vo = fe C vi hie Equivalent hybrid circuit when RE is not bypassed by the capacitor.

τ = RC T = 2τ ln c 1 − βm β " feedback factor β= So. Output of the multiplexer is written as f = I0 S1 S0 + I1 S1 S0 + I2 S1 S0 + I3 S1 S0 I0 = 0 . time period is given as 1+β . 10 H & MOV (10) H in register B B = (10) H GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www. I1 = I2 = I 3 = 1 f = 0 + xy + xy + xy = xy + xy + xy = xy + x (y + y ) = xy + x a y+y = 1 = (x + x) (x + y) A + BC = (A + B) (A + C) = x+y a x+x = 1 So.121 Option (B) is correct.nodia. v+ =1 vo 2 J1 + 1 N 2 O = 2τ ln 3 T = 2τ ln K K 1 K1 − O O 2P L SOL 8. Since gain-bandwidth product remains constant Therefore 105 # 10 = 100 # fCL fCL = 10 kHz SOL 8.119 Option (B) is correct.com CHAP 8 ANALOG & DIGITAL ELECTRONICS PAGE 517 SOL 8.122 Option (C) is correct.120 Option (C) is correct. MVI A.in . 10 H & MOV (10) H in accumulator A = (10)H MVI B.gatehelp. Given circuit is an astable multi vibrator circuit.co. SOL 8.www.

gatehelp.co.com PAGE 518 ANALOG & DIGITAL ELECTRONICS CHAP 8 BACK : NOP ADDB & Adds contents of register B to accumulator and result stores in accumulator A = A + B = (10) H + (10) H 000 10000 ADD 0 0 0 1 0 0 0 0 A=001 00000 = (20) H RLC & Rotate accumulator left without carry JNC BACK & JUMP TO Back if CY = 0 NOP ADD B &A = A + B = (40) H + (10) H 0100 0000 ADD 0 0 0 1 0 0 0 0 A=0101 0000 = (60) H A = (A0) H JNC BACK NOP ADDB & A = A + B = (A0) H + (10) H 1010 0000 ADD 0 0 0 1 0 0 0 0 A=1011 0 0 0 0 A = (B0) H GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www.nodia.www.in .

1 − = (gm) max # 2 (− 5) E 5 (gm) max = 5 = 2.5 # 100 # Q 100 I Leakage = = = t t t −2 −9 # 10 # 5 = 0.5 μA 10 6 SOL 8. SOL 8.125 Option (C) is correct. therefore NOP will be executed 3 times. Trans conductance of an n-channel JFET. Here gm = (gm) max c1 − VGS m VP (− 3) 1 = (gm) max .in .com CHAP 8 ANALOG & DIGITAL ELECTRONICS PAGE 519 CY = 1 So it goes to HLT.5 # 10− 6 = 2.1− 6 1 # 10 − 13 10 = 25 # − = 2. Leakage current is given by 1 0.www.8 # 106 6 f = 62.5 # 10 # 0.123 Option (D) is correct.5 2 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www.8 # 10 = 1 MHz 62.co. Slew rate is defined as the maximum rate of change in output voltage per unit time.source voltage VGS = 0 (gm) max = − 2IDSS VP So. Slew rate = dv0 dt For voltage follower.5 # 1 # CV Ql 0.8 volt/μsec (given) 10 # 2πf = 62. gm = 2IDS = − 2IDSS c1 − VGS m 2VGS VP VP Trans conductance (gm) is maximum when gate .to .124 Option (A) is correct.8 SOL 8.nodia. So. is given by.gatehelp. vin = 10 sin ωt dt = d (10 sin ωt) = 10ω cos ωt dt = 10ω = 62. v0 = vin Slew rate = dvin .

(1) Visit us at: www. Where input to the flip flops are D3 = Q3 + Q2 + Q1 D2 = Q3 .co. D 0 = Q1 Truth table of the circuit can be drawn as CLK Initial state 1 2 3 4 5 6 7 Q3 1 0 0 0 1 0 0 0 Q2 1 1 0 0 0 1 0 0 Q1 1 1 1 0 0 0 1 0 Q0 0 1 1 1 0 0 0 1 8 1 0 0 0 From the truth table we can see that counter states at N = 4 and N = 8 are same.com PAGE 520 ANALOG & DIGITAL ELECTRONICS CHAP 8 SOL 8.in . The circuit is a synchronous counter.127 Option (B) is correct.. So mod number is 4.126 Option () is correct.gatehelp. SOL 8.www. In the circuit Writing node equation in the circuit at the negative terminal of op amp-1 v1 − 1 + v1 − v2 = 0 1 2 3v1 − v2 = 2 Similarly. at the positive terminal of op amp-1 v1 − vo + v1 − 0 = 0 3 1 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 .. D1 = Q2 .nodia.

(3) Option (C) is correct...2 kX gm vπ = GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www.in . for mid-band frequencies vo =− gm vπ RC In the input loop vi rπ RB + rπ − gm RC rπ vi So. vo = RB + rπ − gm rπ RC Gain Av = vo = vi RB + rπ Trans-conductance (1 mA) gm = IC = = 1 A/V VT (26 mV) 26 β gm rπ = β0 & rπ = 0 = 200 # 26 = 5.nodia.128 .www..(2) .co.gatehelp..com CHAP 8 ANALOG & DIGITAL ELECTRONICS PAGE 521 4v1 − vo = 0 At the negative terminals of op-amp-2 − 1 − v2 + − 1 − vo = 0 m c m c 4 8 − 2 − 2v2 − 1 − vo = 0 vo + 2v2 =− 3 From equation (1) and (2) 3 vo − 2v2 = 1 4 From equation (3) 3 v − 2 (− 3 − v ) = 1 o 4 o 3 v + v =− 5 o 4 o 7 v =− 5 4 o vo =− 20 volt 7 SOL 8. Small signal circuit is (mid-band frequency range) CE " 0 .

com PAGE 522 ANALOG & DIGITAL ELECTRONICS CHAP 8 So gain Av = − 200 # (1 kΩ) =− 6.2) # 103 CE = = 1.2) # 106 SOL 8. RE (RB + rπ) RE + RB + rπ 1 (RE + RB + rπ) f0 = = 10 Hz (given) 2πRE (RB + rπ) CE (0. For low frequencies ω " 0 & 1 " 3 (i.2 kΩ) SOL 8.62 (25 kΩ + 5.1 + 25 + 5.nodia.www.in .co.1 (25 + 5.129 Option (B) is correct.e. We can approximately analyze the circuit at low and high frequencies as following. Cut off frequency due to CE is obtained as f0 = 1 2πReq CE Req " Equivalent resistance seen through capacitor CE Req = RE < RB + rπ = So So.gatehelp.130 Option (D) is correct.59 mF 2π # 0. capacitor is open) ωc Equivalent circuit is GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www.

capacitor behaves as short circuit ωc and gain of the filter is given as Av = − R2 = 10 R1 R2 = 10 R1 Input resistance of the circuit Rin = R1 = 100 kΩ So. SOL 8.131 At high frequency ω " 3 & 1 " 0 . For high frequencies ω " 3 & 1 " 0 (i.92 nF *********** GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276243 Visit us at: www.www. it does not pass the low frequencies.e.14 # 103 # 10 4 = 15.gatehelp. This is a high pass filter. capacitor is short) ωc Equivalent circuit is vo =− R2 vi R1 So it does pass the high frequencies.co.in .nodia.com CHAP 8 ANALOG & DIGITAL ELECTRONICS PAGE 523 So. R2 = 10 # 100 kΩ = 1 MΩ Transfer function of the circuit Vo (jω) − jωR2 C = 1 + jω R1 C Vi (jω) High frequency gain Av3 = 10 At cutoff frequency gain is − jωc R2 C Av = 10 = 1 + jωc R1 C 2 ωc R2 C 10 = 2 2 2 2 1 + ωc R1 C 2 2 2 2 2 2 100 + 100ωc R 1 C = 2ωc R 2 C 2 10 2 2 12 2 100 + 100 # ωc # 10 # C = 2 # ωc # 10 # C 2 2 100 = ωc C # 1012 C2 = 2 100 12 ωc # 10 1 1 = C = 2πfc # 10 4 2 # 3.

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