Service Manual

Model #: VIZIO JV50P HDTV10A

V, Inc 320A Kalmus Drive Costa Mesa, CA 92626 TEL : +714-668-0588 FAX :+714-668-9099

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Table of Contents
CONTENTS Sections 1. Features 2. Specifications 3. On Screen Display 4. Factory Preset Timings 5. Pin Assignment 6. Main Board I/O Connections 7. Theory of Circuit Operation 8. Waveforms 9. Trouble Shooting 10. Block Diagram 11. Spare parts list 12. Complete Parts List 1-1 2-1 3-1 4-1 5-1 6-1 7-1 8-1 9-1 10-1 11-1 12-1 PAGE

Appendix 1. Main Board Circuit Diagram 2. Main Board PCB Layout 3. Assembly Explosion Drawing Block Diagram

VIZIO JV50P HDTV10A Service Manual

VINC
COPYRIGHT © 2000 V, INC. ALL RIGHTS RESERVED.

Service Manual
VIZIO JV50P HDTV10A

IBM and IBM products are registered trademarks of International Business Machines Corporation. Macintosh and Power Macintosh are registered trademarks of Apple Computer, Inc. VINC and VINC products are registered trademarks of V, Inc. VESA, EDID, DPMS and DDC are registered trademarks of Video Electronics Standards Association (VESA). Energy Star is a registered trademark of the US Environmental Protection Agency (EPA). No part of this document may be copied, reproduced or transmitted by any means for any purpose without prior written permission from VINC. FCC INFORMATION This equipment has been tested and found to comply with the limits of a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy, and if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that the interference will not occur in a particular installation. If this equipment does cause unacceptable interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures -- reorient or relocate the receiving antenna; increase the separation between equipment and receiver; or connect the into an outlet on a circuit different from that to which the receiver is connected. FCC WARNING To assure continued FCC compliance, the user must use a grounded power supply cord and the provided shielded video interface cable with bonded ferrite cores. Also, any unauthorized changes or modifications to Amtrak products will void the user’s authority to operate this device. Thus VINC Will not be held responsible for the product and its safety. CE CERTIFICATION This device complies with the requirements of the EEC directive 89/336/EEC with regard to “Electromagnetic compatibility.” SAFETY CAUTION Use a power cable that is properly grounded. Always use the AC cords as follows – USA (UL); Canada (CSA); Germany (VDE); Switzerland (SEV); Britain (BASEC/BS); Japan (Electric Appliance Control Act); or an AC cord that meets the local safety standards.

VIZIO JV50P HDTV10A Service Manual

Support 16bit. Audio AUX IN 5. RX channel: 4 channels in 5. User unique ID pairing function. 15. HDMI . brightness.e. Smoothing function enables display of smooth texts and graphics even if image with resolution lower than 1366x768 is magnified 7. 10. composite video.ATV out and DTV out .Chapter 1 Features 1. color. PIP. aspect and gamma or reset all setting. RF Modulation: Direct Sequence Spreading Spectrum (DSSS) 11. Simulatnueous display of PC and TV images 3.8GHz ISM band with auto scan and synchronization functions. On Screen Display: user can define display mode (i. Center Frequency 1 5745MHz 2 5765MHz 3 5785MHz 4 5805MHz CONFIDENTIAL – DO NOT COPY Page 1-1 File No. 32/44. sound setting. backlight). Picture In Picture (PIP) function to show TV or VCR/DVD images 8. 13. RF channel Carrier Frequency: Channel No. TX/RX distance: 10Meters (indoor with free space) min. Built in auto adjust function for automatic adjument of screen display 6. Connectable to PC’s analog RGB port 4. Built in HDTV. sharpness. Built in TV channel selector for TV viewing 2.1/48KHz digital audio transmission and receiving. TV channel program. Power saving to reduce consumption power too less than 3W 9. SG-0228 . 12. contrast. 14.

400 W (Full-White) 20.5 Kg (Net 1EA) Specification 2. SG-0228 . SPDIF Out (Optical Audio) 4. 3rows). RCAX2 (AUDIO in). SPDIF IN(Optical Audio) 3. RCAX2 (composite).5mm 810 ㎛(H) × 810 ㎛(V) 270 ㎛ (H) × 810 ㎛ (V) (Green Cell basis) 1366(H) × 768(V) (1pixel=3 RGB cells) (R)1.Input Connectors RJ11.500cd/㎡ (1/100 White Window pattern at center) Average 130:1 (In a bright room with 100Lux at center) Typical 15. PDP CHARACTERISTICS PDP50X4 (50”WXGA PDP MODULE) Item Active Screen Size Outline Dimension Display Area Pixel Pitch Cell Pitch Pixel Format Number of Gradations Peak Brightness Contrast Ratio 50 inch diagonal 1190(H) × 700(V) × 58(D) ± 1mm 1106.000:1 (In a dark room 1/100 White Window pattern at center) Viewing Angle(L/R/U/D) Free Power Consumption Weight Max.5(H) × 622.024 colors Typical 1.Output Connectors Stereo RCA Jack (Analog audio out) .024 × (B)1. Tuner.Chapter 2 Specification 1. RCAX2 (AUDIO in). D-SUB15PIN (MINI. HDMIX3.1(V) ± 0. POWER SUPPLY Power Consumption: 550W MAX Power OFF: to less than 3W MAX SUBWOOFER POWER SUPPLY Power Consumption: 70W MAX Sleep mode(or TV off): to less than 3W MAX CONFIDENTIAL – DO NOT COPY Page 2-1 File No.024 × (G)1.4±0. RCAX2 (component).

CONFIDENTIAL – DO NOT COPY Page 2-2 File No. And the case on which a module is mounted should have sufficient strength so that external force is not transmitted directly to the module. (4) You should adopt radiation structure to satisfy the temperature specification.0mm Height: 856. ENVIRONMENT 7-1. TV net 52. Operating Altitude: 0 .5. TV and spk gross 72. DIMENSIONS (Physical dimension) Width: 1241. Operating Humidity: Ta= 35 °C.14. Twisted stress) is not applied to the module. Operating Temperature: 5c~35c (Ambient) 7-2. (3) Please attach the surface transparent protective plate to the surface in order to protect the polarizer. MOUNTING PRECAUTIONS (1) You must mount a module using holes arranged in four corners or four sides. WEIGHT (Physical weight) a. 90%RH (Non-condensing) 7-3.0kg c.000 feet (Non-Operating) 7.2mm 8.6kg b.3mm Depth: 291. (2) You should consider the mounting structure so that uneven force (ex.Please pay attention to the followings when you use this PDP module. Transparent protective plate should have sufficient strength in order to the resist external force. SG-0228 . Spk net 8.0kg 9.Speaker Output 10W (max) X3 Wireless Speaker : (1) Rear Right 10W(max) (2) Rear Left 10W(max) (3) Subwoofer 20W(max) 6. 9-1.

And please do not rub with dust clothes with chemical treatment. smear or spot will occur. Grounding and shielding methods may be important to minimize the interference. (6) Do not touch. (5) Module has high frequency circuits. it becomes longer.) (3) Be careful for condensation at sudden temperature change. toluene and alcohol because they cause chemical damage to the polarizer. Their long time contact with polarizer causes deformations and color fading. (9) Do not open the case because inside circuits do not have sufficient strength. System manufacturers shall do sufficient suppression to the electromagnetic interference.(Some cosmetics are detrimental to the polarizer. (4) When fixed patterns are displayed for a long time. (8) Wipe off saliva or water drops as soon as possible. Do not touch the surface of polarizer for bare hand or greasy cloth. OPERATING PRECAUTIONS (1) The spike noise causes the mis-operation of circuits. 9-2. Do not use acetone.) (7) When the surface becomes dusty. It should be lower than following voltage : V=±200mV(Over and under shoot voltage) (2) Response time depends on the temperature.(5) Acetic acid type and chlorine type materials for the cover case are not desirable because the former generates corrosive gas of attacking the polarizer at high temperature and the latter causes circuit break by electro-chemical reaction. SG-0228 . remnant image is likely to occur. please wipe gently with absorbent cotton or other soft materials like chamois soaks with petroleum benzene. push or rub the exposed polarizes with glass. CONFIDENTIAL – DO NOT COPY Page 2-3 File No. (In lower temperature. tweezers or anything harder than HB pencil lead. And after fading condensation. Normal-hexane is recommended for cleaning the adhesives used to attach front / rear polarizers. Condensation makes damage to polarizer or electrical contacted parts.

HANDLING PRECAUTIONS FOR PROTECTION (1) The protection film is attached to the bezel with a small masking tape. When the glue remains on the bezel surface or its vestige is recognized. (3) You can remove the glue easily. (2) When the module with protection film attached is stored for a long time. etc.9-3. This should be peeled off slowly and carefully by people who are electrically grounded and with well ion-blown equipment or in such a condition. CONFIDENTIAL – DO NOT COPY Page 2-4 File No. When the protection film is peeled off. SG-0228 . please wipe them off with absorbent cotton waste or other soft material like chamois soaked with normal-hexane. sometimes there remains a very small amount of glue still on the bezel after the protection film is peeled off. static electricity is generated between the film and polarizer.

BRIGHTNESS (0~100) d. DNR(OFF/LOW/MEDIUM/STRONG) i-2. BLACK LEVEL EXTENDER (ON/OFF) i-3. PICTURE: a. SG-0228 . TINT (-32~32) g. SHARPNESS (0~100) h. COLOR TEMPERATURE (CUSTOM/COOL/NORMAL/WARM) i. WHITE PEAK LIMITATOR (ON/OFF) i-4 CTI(OFF/LOW/MEDIUM/STRONG) i-5 FLESH TONE (ON/OFF) i-6 ADAPTIVE LUMA (ON/OFF) CONFIDENTIAL – DO NOT COPY Page 3-1 File No. BACKLIGHT (0~100) c.Chapter 3 Main unit button Power MENU CH ▲ CH ▼ VOL + VOL Input On Screen Display On Screen Display TV Source A. COLOR (0~100) f. PICTURE MODE (CUSTOM/ STANDARD / MOVIE / GAME) b. CONTRAST (0~100) e. ADVANCED VIDEO i-1.

SPEAKER DISTANCE SETUP h-3-1. Rear Right(0~100) h-2-5. SPEAKERS (ON/OFF) f.) h-3-2. VOLUME (0~100) b. Digital Audio Out (Off / Dolby Digital / PCM) e. Daylight Saving(ON/OFF) CONFIDENTIAL – DO NOT COPY Page 3-2 File No. BASS (0~100) c. SKIP CHANNEL (TABLE) d. TV (0~15ft. Center(0~100) h-2-6. Left(0~100) h-2-2. AUTO SEARCH (RUN) c. Wireless SPEAKERS (ON/OFF) g. Rear Left(0~15ft. Right(0~100) h-2-3. TUNER MODE (ANTENNA/CABLE) b. SPDIF IN( Off / AV1 / AV2 / COMPONENT1 /COMPONENT2 / HDMI1 / HDMI2 / HDMI3 ) h. SPEAKER SETTING h-1. TREBLE (0~100) d.) C.B. AUDIO: a. TIME ZONE (HAWALL/EASTTERN/INDIANA/CENTRAL/MOUNTAIN/ARIZONA/PACIFIC/ALASKA) f. DCR( Off / 1/4 / 1/2 / 3/4 / Full ) e. Rear Right(0~15ft. SPEAKER LOCATION( Auto / Left / Center /Right / Rear Right / Sub Woofer / Rear Left ) h-2. SG-0228 .) h-3-2. TV: a. Rear Left(0~100) h-2-4. TRIM h-2-1. Sub Woofer(0~100) h-3.

MOVIE RATING a-4. CAPTION STYLE (AS BROADCASTER/CUSTOM) e-2. CHANNEL BLOCK a-2. FONT OPACITY (SOLID/TRANSLUCENT/TRANSPARENT) e-5. WINDOW OPATITY (SOLID/TRANSLUCENT/TRANSPARENT) f. DIGITAL CC STYLE e-1. LANGUAGE (ENGLISH/FRENCH/SPANISH) b. SETUP: a. WINDOW COLOR (GREEN/BLUE//RED/CYAN/YELLOW/MAGENTA/BLACK/WHITE) e-8. BLOCK TV UNRATED a-5. BACKGROUND COLOR (GREEN/BLUE//RED/CYAN/YELLOW/MAGENTA/BLACK/WHITE) e-6. DIGITAL CC(OFF/SERVICE1/ SERVICE2/ SERVICE3/ SERVICE4/ SERVICE5/ SERVICE6) e. TV RATING a-3. ACCESS CODE EDIT CONFIDENTIAL – DO NOT COPY Page 3-3 File No. ANALOG CC (OFF/CC1/CC2/CC3/CC4) d. BACKGROUND OPACITY (SOLID/TRANSLUCENT/TRANSPARENT) e-7. SG-0228 . FONT COLOR (GREEN/BLUE//RED/CYAN/YELLOW/MAGENTA/BLACK/WHITE) e-4. RESET ALL SETTING E. PASSWORD a-1.D. Image Cleaner g. SLEEP TIMER (OFF/30/60/90/120) c. FONT SIZE(SMALL/MEDIUM/LARGE) e-3. PARENTAL: a.

SPEAKER SETTING h-1. H-POSITION (0~100) h. Right(0~100) h-2-3. VOLUME (0~100) b. BRIGHTNESS (0~100) d.9300K) f. TV (0~15ft. COLOR TEMPERATURE(CUSTOM. SPEAKERS (ON/OFF) f. V-POSITION (0~100) i.RGB Mode A. BASS (0~100) c. TRIM h-2-1. Rear Left(0~100) h-2-4. AUDIO: a. PICTURE ADJUST: a.) h-3-2. 6500K. TREBLE (0~100) d. Wireless SPEAKERS (ON/OFF) g. SPEAKER DISTANCE SETUP h-3-1. Left(0~100) h-2-2. Rear Right(0~15ft. H-SIZE (0~255) g. SPEAKER LOCATION ( Auto / Left / Center / Right / Rear Right / SubWoofer / Rear Left ) h-2. BACKLIGHT (0~100) c. AUTO PICTURE (Run) b.) CONFIDENTIAL – DO NOT COPY Page 3-4 File No. CONTRAST (0~100) e.) h-3-2. FINE TUNE (0~31) B. Sub Woofer(0~100) h-3. Rear Left(0~15ft. DCR( Off / 1/4 / 1/2 / 3/4 / Full ) e. Rear Right(0~100) h-2-5. SPDIF IN( Off / AV1 / AV2 / COMPONENT1 /COMPONENT2 / HDMI1 / HDMI2 / HDMI3 ) h. Center(0~100) h-2-6. SG-0228 .

Image Cleaner d. SHARPNESS (0~100) g. ADVANCED VIDEO h-1. WHITE PEAK LIMITATOR (ON/OFF) h-4 CTI(OFF/LOW/MEDIUM/STRONG) h-5 FLESH TONE (ON/OFF) h-6 ADAPTIVE LUMA (ON/OFF) B. SETUP: a.C. RESET ALL SETTING HDMI MODE A. TINT (-32~32) f. SG-0228 . COLOR TEMPERATURE (CUSTOM/COOL/NORMAL/WARM) h. PICTURE: a. SPEAKER SETTING h-1. LANGUAGE (ENGLISH/FRENCH/SPANISH) b. TREBLE (0~100) d. BLACK LEVEL EXTENDER (ON/OFF) h-3. BASS (0~100) c. DNR(OFF/LOW/MEDIUM/STRONG) h-2. PICTURE MODE (CUSTOM/ STANDARD /MOVIE / GAME) b. SPEAKERS (ON/OFF) f. SPEAKER LOCATION ( Auto / Left / Center / Right / Rear Right / SubWoofer / Rear Left ) CONFIDENTIAL – DO NOT COPY Page 3-5 File No. SPDIF IN( Off / AV1 / AV2 / COMPONENT1 /COMPONENT2 / HDMI1 / HDMI2 / HDMI3 ) h. SLEEP TIMER (OFF/30/60/90/120) c. AUDIO: a. CONTRAST (0~100) d. VOLUME (0~100) b. COLOR (0~100) e. Wireless SPEAKERS (ON/OFF) g. DCR( Off / 1/4 / 1/2 / 3/4 / Full ) e. BRIGHTNESS (0~100) c.

TV (0~15ft. TINT (-32~32) f. PICTURE MODE (CUSTOM/ STANDARD /MOVIE / GAME) b.) h-3-3. SHARPNESS (0~100) g. Image Cleaner d. Rear Left(0~100) h-2-4.h-2. Center(0~100) h-2-6. COLOR TEMPERATURE(CUSTOM/COOL/NORMAL/WARM) h. LANGUAGE (ENGLISH/FRENCH/SPANISH) b. SPEAKER DISTANCE SETUP h-3-1. SLEEP TIMER (OFF/30/60/90/120) c. ADVANCED VIDEO h-1. BLACK LEVEL EXTENDER (ON/OFF) h-3. WHITE PEAK LIMITATOR (ON/OFF) h-4 CTI(OFF/LOW/MEDIUM/STRONG) h-5 FLESH TONE (ON/OFF) h-6 ADAPTIVE LUMA (ON/OFF) CONFIDENTIAL – DO NOT COPY Page 3-6 File No. Left(0~100) h-2-2. BRIGHTNESS (0~100) c. COLOR (0~100) e. SG-0228 .) C. Right(0~100) h-2-3. TRIM h-2-1. RESET ALL SETTING Video Sources: AV1、AV2、COMPONENT1、COMPONENT2 A. PICTURE: a. SETUP: a. Rear Right(0~100) h-2-5.) h-3-2. DNR(OFF/LOW/MEDIUM/STRONG) h-2. Rear Left(0~15ft. CONTRAST (0~100) d. Sub Woofer(0~100) h-3. Rear Right(0~15ft.

DCR( Off / 1/4 / 1/2 / 3/4 / Full ) e. SPEAKERS (ON/OFF) f. SPEAKER SETTING h-1. Rear Right(0~100) h-2-5. Right(0~100) h-2-3. SPDIF IN( Off / AV1 / AV2 / COMPONENT1 /COMPONENT2 / HDMI1 / HDMI2 / HDMI3 ) h. LANGUAGE (ENGLISH/FRENCH/SPANISH) b. Center(0~100) h-2-6. RESET ALL SETTING CONFIDENTIAL – DO NOT COPY Page 3-7 File No. Image Cleaner e. Wireless SPEAKERS (ON/OFF) g.B. Rear Right(0~15ft.) h-3-2. SLEEP TIMER (OFF/30/60/90/120) c.) C. SPEAKER DISTANCE SETUP h-3-1. VOLUME (0~100) b. SG-0228 . TREBLE (0~100) d. Analog CC(Off/CC1/CC2/CC3/CC4) d. Sub Woofer(0~100) h-3. SETUP: a. SPEAKER LOCATION( Auto / Left / Center / Right / Rear Right / SubWoofer / Rear Left ) h-2. BASS (0~100) c. TV (0~15ft. TRIM h-2-1. Rear Left(0~100) h-2-4. Left(0~100) h-2-2.) h-3-3. Rear Left(0~15ft. AUDIO: a.

TV RATING a-3. SG-0228 . PASSWORD a-1. ACCESS CODE EDIT CONFIDENTIAL – DO NOT COPY Page 3-8 File No. MOVIE RATING a-4. CHANNEL BLOCK a-2. PARENTAL: a. BLOCK TV UNRATED a-5.D.

175MHz 31.9kHz 53.06Hz 60.01Hz 75.00Hz 85. SG-0228 .7kHz Vertical Frequency 60Hz Horizontal Polarity P Vertical Polarity N Pixel Rate 85.03Hz 70.5kHz 37.250 MHz 65.46kHz 47.500 MHz Native Resolution Resolution 1366X768 Refresh rate 60Hz Horizontal Frequency 47.000 MHz 49.00Hz 60.320 MHz 85.4kHz 60.5kHz 37.9kHz 46.500 MHz 56.750 MHz 28. Resolution 640x480 640x480 800X600 800x600 800X600 1024x768 1024X768 720x400 1366X768 Remark: Refresh rate 60Hz 75Hz 60Hz 75Hz 85Hz 60Hz 75Hz 70Hz 60 P: positive Horizontal Frequency 31.500 MHz 40.000 MHz 78.317Hz 75.Chapter4 Factory preset timings This timing chart is already preset for the TFT LCD analog & digital display monitors.0kHz 31.5MHz CONFIDENTIAL – DO NOT COPY Page 4-1 File No.00HZ Horizontal Polarity N N P P P N P N P Vertical Polarity N N P P P N P P N Pixel Rate 25.94Hz 75.7kHz 48.7KHZ N: negative Vertical Frequency 59.08Hz 60.

SG-0228 .Chapter5 Pin Assignment The PDP analog display monitors use a 15 Pin Mini D-Sub connector as video input source. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Red Green Blue Ground Ground R-Ground G-Ground B-Ground +5V for DDC Ground No Connection (SDA) H-Sync (Composite Sync) V-Sync (SCL) Description 1 6 11 5 10 15 CONFIDENTIAL – DO NOT COPY Page 5-1 File No.

Sync Type TTL (Separate / Composite) or Sync. Video Amplitude RGB: 0.7Vp-p d.RGB Signal: a. Sync polarity Positive or Negative c.C on device) SCL SDA DDC/CEC Ground +5V Power Hot Plug Detect CONFIDENTIAL – DO NOT COPY Page 5-2 File No. female g. On Green b. SG-0228 . Frequency H: support to 30K~70KHz V: support to 50~85Hz e. Pixel Clock: support to 110MHz f. Impedance: 75Ω HDMI CONNECT PIN ASSIGNMENT: PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 SIGNAL ASSIGNMENT TMDS Data2+ TMDS Data2 Shield TMDS Data2TMDS Data1+ TMDS Data1 Shield TMDS Data1TMDS Data0+ TMDS Data0 Shield TMDS Data0TMDS Clock+ TMDS Clock Shield TMDS ClockCEC Reserved (N. Connector type: 15-pin D-Sub.

Frequency 57~803 MHz QAM system (supporting clear QAM) a. IF-output level 1Vp-p minimum b. Pin Assignment Refer to HDMI Pin Assignment b. Polarity Positive or Negative d. Frequency 55~801 MHz ATSC system a. Frequency 57~849 MHz CONFIDENTIAL – DO NOT COPY Page 5-3 File No.734KHz V: 60Hz (NTSC-480i) H: 31KHz V: 60Hz (NTSC-480p) H: 45KHz V: 60Hz (NTSC-720p) H: 33KHz V: 60Hz (NTSC-1080i) F-Type TV RF connector NTSC system a. Frequency H: 15. IF-output level 1Vp-p minimum b. Signal level Analog 1Vp-p typical b.HDMI Signal (HDMI): a. Type A c. SG-0228 .

Peak emission wavelength: 630 – 690 µm b.734KHz V: 60Hz (NTSC) b.AV/Composite Video (CVBS) Connector a. Impedance: 75Ω d. Impedance: 560Ω c. Frequency: 30Hz-20KHz d. Connector type: RCA Jack Analog audio in a.0Vrms b. Connector type: Optical fiber receiver CONFIDENTIAL – DO NOT COPY Page 5-4 File No. Transmission Speed: 13. Connector type: RCA L/R Analog Audio out a. SG-0228 .2M pbs c. Impedance: 75Ω d.0Vmax b. Signal level: Video ( Y + C ):1Vp-p Sync (H+V):0. Signal level: Y: 1Vp-p Pb: ±0. Peak emission wavelength: 650nm b.350Vp-p c. Frequency: H: 15. Connector type: RCA Jack Component video Connector a. Connector type: Optical fiber transmitter Digital audio in a. Transmission Speed: 16M pbs c.3V below Video (Y+C) c. Impedance: 47KΩ c.734KHz V: 60Hz (NTSC-480i) H: 31KHz V: 60Hz (NTSC-480p) H: 45KHz V: 60Hz (NTSC-720p) H: 33KHz V: 60Hz (NTSC-1080i) b. Frequency: H: 15. Signal level: 2. Frequency Response: 30Hz-20KHz (exclude wireless on mode) d. Connector type: RCA L/R: Digital audio out a.350Vp-p Pr: ±0. Signal level 1.

SG-0228 .Chapter 6 Main Board I/o Connections J10 CONNECTION (MAIN TO PANEL PSU) Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Description VS_ON PDP_12VFAN PDP_12VSC GND GND GND GND GND GND PDP_5VSC PDP_5VSC PDP_5VSC PDP_5VSB RLY_ON ACD J12 CONNECTION (MAIN TO AUDIO BOARD) Pin 1 2 3 4 5 6 7 8 Description AUDIO_CT DACGND AUDIO_OUTR AMP_MUT AUDIO_OUTL DACGND GND ACD CONFIDENTIAL – DO NOT COPY Page 6-1 File No.

J13 CONNECTION Pin 1 2 Description +5V GND

J9 CONNECTION Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Description AMBER WHITE OIRI 5VSB 5VSB GND GND ADIN-1 ADIN-2 DV33SB HPL_IN GND HPR_IN HPIN_DET

CONFIDENTIAL – DO NOT COPY

Page 6-2 File No. SG-0228

J14 CONNECTION Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Description +5V PGND NC NC TX_SGND ID_Trigge NC NC NC NC TX_Mute NC NC ACD_mute AO1LRCK AO1SDATA1 AO1BCK AO1MCLK

CONFIDENTIAL – DO NOT COPY

Page 6-3 File No. SG-0228

J7 CONNECTION Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Description GND GND A7P A7N CK2P CK2N A6P A6N A5P A5N A4P A4N A3P A3N CK1P Pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Description CK1N A2P A2N A1P A1N A0P A0N LVDS_ROTATE LVDS_OPTION GND GND GND LVDSVDD LVDSVDD LVDSVDD

AUDIO BD I/O CONNECTIONS OF TV
J1 CONNECTION (MAIN BOARD→AUDIO BOARD) Pin 1 2 3 4 5 6 7 8 Description “CT” “COM” “R” “mute” “L” “SGND” “GND” “AC_detect”

CONFIDENTIAL – DO NOT COPY

Page 6-4 File No. SG-0228

SG-0228 .J2 CONNECTION (POWER BOARD→ADUIO BOARD) Pin 1 2 3 4 Description “+24V” “+24V” “GND” “GND” J3 CONNECTION (AUDIO BOARD→EMI BOARD) Pin 1 2 3 4 5 6 WAFER INFORMATION Description “ROUT+” “GND” “CTOUT+” “GND” “LOUT+” “GND” Pin1 CONFIDENTIAL – DO NOT COPY Page 6-5 File No.

SG-0228 .EMI BD I/O CONNECTIONS J1 CONNECTION (AUDIO BOARD→EMI BOARD) Pin 1 2 3 4 5 6 Description “ROUT+” “GND” “CTOUT+” “GND” “LOUT+” “GND” J2 CONNECTION (EMI BOARD→SPEAKERS) Pin 1 2 3 4 5 6 Description “ROUT+” “GND” “CTOUT+” “GND” “LOUT+” “GND” CONFIDENTIAL – DO NOT COPY Page 6-6 File No.

WAFER INFORMATION Pin1 Pin1 CONFIDENTIAL – DO NOT COPY Page 6-7 File No. SG-0228 .

SG-0228 .AUDIO BD I/O CONNECTIONS OF SUBWOOFER J1 CONNECTION (RX MODULE→AUDIO BOARD) Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Audio BD Description “VCCIO” “PGND” “RS” “PGND” “SGND” “NC” “LS” “NC” “PGND” “NC” “Mute” “NC” “NC” “CH/ID” “NC” “LED-” “NC” “SYSTEM_MUTE” Module Description “VCCIO” “PGND” “-” “PGND” “UGND” “TEST” “-” “-” “-” “-” “Mute” “-” “-” “CH/ID” “-“ “-” “-” “GPIO” J2 CONNECTION (POWER→AUDIO BOARD) Pin 1 2 3 4 5 6 7 Description “GND” “5V” “AC_detect” “GND” “GND” “24V+” “24V+” CONFIDENTIAL – DO NOT COPY Page 6-8 File No.

J3 CONNECTION (AUDIO BOARD→I/O BOARD) Pin 1 2 3 4 Description “LOUT+” “LGND” “ROUT+” “RGND” J4 CONNECTION (AUDIO BOARD→SUBWOOFER) Pin 1 2 Description “SWOUT+” “SWOUT-” J5 CONNECTION (AUDIO BOARD→LED BOARD) Pin 1 2 Description “GND” “+5V” J6 CONNECTION (AUDIO BOARD→I/O BOARD) Pin 1 2 3 Description “CH/ID” “GND” “GND” CONFIDENTIAL – DO NOT COPY Page 6-9 File No. SG-0228 .

SG-0228 .WAFER INFORMATION Pin1 Pin1 CONFIDENTIAL – DO NOT COPY Page 6-10 File No.

SG-0228 .Pin1 CONFIDENTIAL – DO NOT COPY Page 6-11 File No.

SG-0228 .CONNECTOR BD I/O CONNECTIONS J1 CONNECTION (TOP→BOTTOM) Pin 1 2 3 4 5 6 7 J2 CONNECTION (TOP→BOTTOM) Pin 1s 1t 2s 2t WAFER INFORMATION Description “LS-” “LS+” “RS-” “RS+” Description “RS+” “RS-” “LS+” “LS-” “Switch+” “Switch-” “GND” Blue circle : 1s Red circle : 1t Green circle : 2s Brown circle : 2t CONFIDENTIAL – DO NOT COPY Page 6-12 File No.

SG-0228 .Pin1 CONFIDENTIAL – DO NOT COPY Page 6-13 File No.

Input. CONFIDENTIAL – DO NOT COPY Page 7-1 File No. The operation of Video & S-Video route The Video and S-Video signal is transmission signal to the MT5372 then MT5372 generates the vertical and horizontal timing signals for display device.Then MT5372 process to MT8291 and output to Audio Board transfer to speaker.Chapter 7 Theory of Circuit Operation The operation of D-SUB 15pin route The D-SUB 15pin is input analog signal to the MT5372 transfer A/D converter then generates the vertical and horizontal timing signals for display device. SG-0228 . the MT5372 generates the vertical and horizontal timing signals for display device. The operation of HDMI CON route Then transfer to the MT5372. The operation of HDTV & Component route HDTV & Component signal is input to the MT5372 then MT5372 generates the vertical and horizontal timing signals for display device. Then MT5372 process to MT8291 and output to Audio Board transfer to speaker. The operation of Audio AUX In route Audio optical signal is processes to the CS8416 generates I2S audio signal transmission to MT5372 . The operation of TV route TV signal is processes to the tuner and output to MT5372 then MT5372 generates the vertical and horizontal timing signals for display device. OSD”. + -. The operation of DTV route DTV signal is processes to the tuner and transmission to MT5112 and output signal to MT5372 generates the vertical and horizontal timing signals for display device. They are “Power. ▼▲. The operation of keypad There are 7 keys to control and select the function of VX32L and also has one LED to indicate the status of operation. Audio is processes to the tuner output to SIF circuit and output to MT5372.

its analog input also support popular S-Video. It includes one 3D/2D TV Decoder recovering the best image from CVBS. and in addition. On-chip microprocessor and reference FW reduces the system BOM and shortens the schedule of UI design by high-level C program. With truly SOC design. VGA video source. MT5372 offers our customers the real cost-effective high performance HDTV-ready solution. Its on-chip audio processor decodes whole world standard audio signals from tuner with lip sync control. On-chip advanced motion adaptive de-interlacer (MDDitm) converts accordingly the interlace video into smooth non-flicking progressive motion pictures. SG-0228 . Component. Flexible scalar provides wide adoption to various LCD panel for different video sources.MT5372 Application MT5372 is a highly integrated video and audio single chip processor for emerging HDTV-Ready LCD TV. delivering high quality post-processed sound effect to customers. With on-chip advanced 2D Graphic processor.MT5372 provides customers with high quality UI adding significant end product value. CONFIDENTIAL – DO NOT COPY Page 7-2 File No.

SG-0228 .CONFIDENTIAL – DO NOT COPY Page 7-3 File No.

Supporting Macro vision detection YPbPr 1. Video input a.Supporting Separate/Composite/SOG sync types CONFIDENTIAL – DO NOT COPY Page 7-4 File No.DTV 480i/480p/720p/1080p 2. Input Multiplexing 1.Supporting various VGA input timings up to SXGA (1280x1024@75Hz).VGA X1 5.Automatic TV standard detection supporting NTSC.support HDTV 480i/480p/720p/1080p 2.support 480i/408p/720p/1080i/1080p 4.Enhanced 2nd generation NTSC Motion Adaptive 3D comb filter 4.support VGA input up to 1366x168@60HZ 6.composite X2 3. NTSC-4.component X2 2.Motion Adaptive 3D Noise Reduction 5.43.Embedded VBI decoder for Closed-Caption/XDS/ Teletext/WSS/VPS 6.support Y/C signal 1VP-P/75Ω 3. SG-0228 . Decoder TVD 1.support RF NTSC system Frequency 55~801MHZ.Single 2nd generation TV decoder 2. Input formats: 1.RF&DTV X1 b.HDMI X3 4.Smart detection on Scart function for European region VGA 1. 3. 2.1.Supporting HDTV 480i/480p/576i/576p/720p/1080i input 2.

Automatic vertical scrolling of OSD image 9. 3.Supporting alpha blending among these two planes and video 2. SG-0228 .Digital port 1. 8. to support Main/PIP Teletext/Close-caption functions together with setup menu 1.Supporting bitblt 5.Supporting Clip Mask 7.Dual VBI decoders for the application of V-Chip/Closed-Caption/XDS/ Teletext/WSS/VPS 2.1 digital port supporting DVI 24-bit RGB or CCIR-656/601 digital video input format 2.Supporting color Key function 6.Supporting line/rectangle/gradient fill 4.Supporting OSD mirror and upside down CONFIDENTIAL – DO NOT COPY Page 7-5 File No.65535/256/16/4/2-color bitmap format OSD.VBI decoder up to 1000 pages Teletext.1 additional 8 bit digital port for ITU656 video format VBI 1.Supporting external VBI decoder by YPrPb input 3. 2D-Graphic/OSD processor Embedded two backend RGB domain OSD planes and one YUV domain OSD plane.43 Automatic Luma / Chroma gain control Automatic TV standard detection NTSC Motion Adaptive 3D comb filter Motion adaptive 3D Noise Reduction VBI decoder for closed-caption/XDS/Teletext/WSS/VPS Macro vision detection 4.Supporting Text/Bitmap decoder 3. Support Formats: Support NTSC. NTSC-4.

5. (For skin.Color Management Fully 10-bit processing to enhance the video quality Advanced flesh tone and multiple-color enhancement. After that the Reset will transits to high state and the MT5372 start to work that microprocessor executes the programs and configures the internal registers. and grass…) Gamma/anti-Gamma correction Advanced Color Transient Improvement (CTI) Saturation/hue adjustment 2. PIP/POP HARDWARE LIMITION: Main SUB DTV/TV AV Component RGB HDMI AUX IN 6. Microprocessor interface When power is supplied and power key is pressed then the rest circuit lets Reset to low state that will reset the MT5372 to initial state. sky.Contrast/Brightness/Sharpness Management Sharpness and DLTI/DCTI Brightness and contrast adjustment Black level extender White peak level limiter Adaptive Luma/Chroma management DTV/TV AV Component ˇ ˇ RGB ˇ ˇ HDMI ˇ ˇ ˇ ˇ AUX IN ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ CONFIDENTIAL – DO NOT COPY Page 7-6 File No. Video processor 1. The execution speed of CPU is 162 MHz. SG-0228 .

and single 8x16 DDR for simple function support Lists are the comparison chart between function support lists of (2xDDR) and (1xDDR) CONFIDENTIAL – DO NOT COPY Page 7-7 File No.For features of 5372. from 1/32X to 32X Advanced linear and non-linear Panorama scaling Programmable Zoom viewer Picture-in-Picture (PIP) Picture-Out-Picture (POP) 5.Display Advanced dithering processing for LCD display with 6/8/10 bit output 10bit gamma correction Supporting alpha blending for Video and two OSD planes Frame rate conversion 6.De-interlacing 2nd generation advanced Motion adaptive de-interlacing Automatic detect film or video source 3:2/2:2 pull down source detection Main/PIP 2 independent de-interlacing processor 4. All the video functions (De-interlace/3D comb/NR/Flesh tone/CTI) can be included 7. Dual for enhance features support.Seamless performance comparing demonstration function Support Left/Right video processing comparing function without additional resources (DRAM…) for customers’ demonstration. DRAM Usage 1.Scaling 2nd generation high resolution arbitrary ratio vertical/horizontal scaling of video. SG-0228 .3.

For single DDR. the MT8291 supports master. then output from DAC1 and DAC2 independently. Due to DDR Bandwidth limitation on PIP when single DDR. It’s up to 24bit serial values at sample rates up to 192kHz. CONFIDENTIAL – DO NOT COPY Page 7-8 File No. SG-0228 . slave modes and three data formats in serial interface.The MT8291 performs stereo analog-to-digital and two digital-to-analog conversions with single-ended analog voltage input and output. two Left/Right line outputs with volume gain/attenuation -127dB to +12dB and digital de-emphasis function. MT8291 Application The MT8291 is highly integrated stereo audio CODEC. The two DAC outputs reach 2Vrms at 12V supply.A7:1 stereo input multiplexer and automatic level control are included.5 steps.With single DDR. (Non-3D de interlace) 3. Sampled data is transmitted by the serial audio interface at rates from 32kHz to 192kHz. The PGA is available for line inputs and provides gain/attenuation of 21dB in 0. they also include headphone.For audio clock application.2. it is suggested not to support PIP/POP features.5372only support 1080i bob mode de-interlacing. Individual two I2S clock and data supported different sample rates for ADC and DAC parts simultaneously.

512Fs.2V to +13.BLOCK DIAGRAM Feature List ● 24-bit Sigma. SG-0228 .5dB step ● Two individual sets of I2S ports simultaneously support different sample rates for the ADC and DACs and then output from DAC1 and DAC2 independently CONFIDENTIAL – DO NOT COPY Page 7-9 File No. right justified and I2S up to 24 bits ● +3.Delta ADC and DAC ● Allows 2Vrms input swing into ADC part ● ADC up to 96 kHz sampling rates ● 90 dB ADC dynamic range ● Automatic Gain Control (AGC) ● 90 dB DAC dynamic range ● DAC up to 192 kHz sampling rates ● Two channels of ADC and four independent channels of DACs (two L/R line outputs and a headphone output) ● Supports two sets of I2S clocks and data inputs independently ● System clocks: 128Fs. 256Fs.0V to +3. 192Fs.6V digital power supply ● +8.2V analog power supply ● 7-channel input multiplexer with ADC programmable gain amplifier’s (PGA’s) gain from +21dB to –21dB in 0. 384Fs. 768Fs ● Selectable serial audio interface formats:left justified.

CONTROL INTERFACE TIMING . SG-0228 . Control Port Timing CONFIDENTIAL – DO NOT COPY Page 7-10 File No.2 WIRE PORT Figure.

Master Mode Figure. fs=48kHz. Master Mode Timing CONFIDENTIAL – DO NOT COPY Page 7-11 File No. MCLK=256fs.DVDD=3.ADCGND/DACGND=0V. Ta=  25 C.3V. SG-0228 .AUDIO INTERFACE TIMING1 AVDD=12V. 24bit data.

AUDIO INTERFACE TIMING2 AVDD=12V. MCLK=256fs.3V.ADCGND/DACGND=0V.DVDD=3. Slave Mode Figure. Slave Mode Timing CONFIDENTIAL – DO NOT COPY Page 7-12 File No. Ta= ° + 25 C. fs=48kHz. 24bit data. SG-0228 .

A resulting calculated to an XOR mask during each clock cycle to decrypt the audio/video data in sync with the host. 4 . The decryption process is entirely controlled by the host microprocessor through a set sequence of register reads and wires through the DDC channel.16K I-Cache and 16K D-Cache 3. 2. 4. MP@HL and MPEG-1 video standards. ARM 926EJ 2. 3 . 8K Data TCM and 8K instruction 4. Pre-programmed HDCP keys and key Selection Vector are used in the decryption process. HDCP Decryption HDCP decryption contains all necessary logic to decrypt the incoming audio and video data. Support TS recording via IEEE1394 interface. CONFIDENTIAL – DO NOT COPY Page 7-13 File No.General Feature List : 1 . Decode Base-line or progressive JPEG file.3. MPEG2 Decoder : 1. Transport Demuxer : 1. 5. Support ATSC . Support dual MPEG-2 HD decoder or up to 8 SD decoder. Host CPU: 1. and MPEG2 transport stream inputs. JPEG Decoder : 1. 96 PID filter and 128 section filters. SG-0228 . Complaint to MP@ML . Support serial/parallel interface for each transport stream input 3. 4. Programmable sync detection. Support 3 independent transport stream inputs 2. Watch Dog timers 2 . Support DES/3-DES De-scramble. DVB . 6. 7. JTAG ICE interface 5.

7 . 2. Mixing one video and one OSD. Support Quad-Picture. YCrCb to RGB color space transfer. Font rendering by color expansion. 480i/576i/480p/576p/720p/1080i output 9 . 2. 5. 4. 2D Graphics : 1. 7. 8 . Contrast/Brightness adjustment. 4. Advanced Motion adaptive de-interlace on SDTV resolution. alpha composition and stretch. 6. OSD Display : 1. 3:2/2:2 pull down source detection. Bitblt with transparent . Auxiliary Display : 1. 3. 480i/576i output. 4. Mixing two video and three OSD and hardware cursor. 6 . 3. 5. 3 linking list OSDs with multiple color mode. 7. CONFIDENTIAL – DO NOT COPY Page 7-14 File No. 32x32 or 64x64 pixel . Support multiple color modes. horizontal/vertical line primitive drawing. Point . Main Display : 1. 2. Picture-Out-Picture( POP ). SG-0228 . hardware cursor. 5. Support Edge preserve. 2. 6. Support clip masks. 3. Support horizontal edge enhancement. Video Processing : 1. Picture-in-Picture( PIP ). alpha blending . 2. Rectangle fill and gradient fill functions.5 . OSD scaling with arbitary ratio from 1/2x to 2x. from 1/15X to 16X. 6. Square size . Gamma correction. Arbitrary ratio vertical/horizontal scaling of video . Support clip 3.

Support NOR/NAND flash. Main audio output : 5. DDR333 . 2. 13 . Support CableCard host control bus. Pink noise and white noise generator. Auxiliary audio output : 2ch. 7. 12. Six 12-bit video DACs for CVBS . MP3 decoding. 11 . 3.1.1ch + 2ch ( down mix ) 5. Audio and video lip synchronization. 3D surround processing include virtual surround. Support NTSC M/N . JEDEC specification compliant SDRAM. Bass management. 4. PAL M/N/B/D/G/H/I 2. Support DDR266 . Equalizer. Support Dolby Digital AC-3 decoding. Support reverberation. S-video or RGB/YPbPr output. Support 8/16 for SD/HD digital video input. 13. Dolby prologic II. 12 . 2. MPEG-1 layer I/II .10 . SPDIF out. Support 64Mb to 1Gb DDR DRAM devices. 5. Peripheral Bus Interface : 1. 2. DRAM Controller : 1. CGMS/WSS. DDR400 . Support SAV/EAV. Closed Captioning. Audio : 1. 2. TV Encoder : 1. I2S I/F. 3. 3. Support 8 bits digital output for aux display. Digital Video Interface : 1. 6. 4. 14 . 8. 11. 4. 10. SG-0228 . Macrovision Rev 7. Configurable 32/64 bit data bus interface.L1 3. CONFIDENTIAL – DO NOT COPY Page 7-15 File No. 9. Support 8/16/24 bits digital output for main display.

allowing operation of high-speed microprocessors without wait states. MXIC's Flash memories offer the most cost-effective and reliable read/write non-volatile random access memory. 3. the MX29LV320AT/B has separate chip enable (CE) and output enable (OE) controls. IR blaster and receiver. SG-0228 . 100MB/s. Two PWMs.2V dual Voltage.SD . IEEE1394 link controller. It is designed to be reprogrammed and erased in system or in standard EPROM programmers.6V VCC supply to perform the High Reliability Erase and auto Program/Erase algorithms. 8. two of them have hardware flow control. The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. The MX29LV320AT/B uses a 2. MX29LV320BTTC (Flash) Application : The MX29LV320AT/B is a 32-mega bit Flash memory organized as 4M bytes of 8 bits and 2M words of 16 bits. 4. The standard MX29LV320AT/B offers access time as fast as 70ns. PCMCIA/POD/CI interface 16 .3V/1.15 . MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. Real-time clock and watchdog controller. 471 Pin BGA Package.000 erase and program cycles. MXIC Flash technology reliably stores memory contents even after 100. 5.7V to 3. 7. CONFIDENTIAL – DO NOT COPY Page 7-16 File No. In addition. 2. one is master only the other can be set to master mode or slave mode. The MX29LV320AT/B uses a command register to manage this functionality. 3. Latch-up protection is proved for stresses up to 100 milliamperes on address and data pin from -1V to VCC + 1V. Memory card I/F : MS/MS-pro . Three UARTs with Tx and Rx FIFO . 2. IC Outline : 1. 6. IDE bus : ATA/ATAPI7 UDMA mode 5 . Two serial interfaces . The MXIC cell is designed to optimize the erase and program mechanisms. the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling.and MMC 9. Peripherals : 1.CF . To eliminate bus contention. The MX29LV320AT/B is packaged in 48-pin TSOP and 48-ball CSP.

CONFIDENTIAL – DO NOT COPY Page 7-17 File No. SG-0228 .

SG-0228 .BLOCK DIAGRAM CONFIDENTIAL – DO NOT COPY Page 7-18 File No.

Address are A20:A0 in word mode (BYTE=VIH). AIN=Address IN.DIN or Dout as required by command sequence.If WP/ACC=VIL.5-12. data polling.5V. See the "Sector Group Protection and Chip Unprotection" section. 2.5V. 3.The sector group protect and chip unprotect functions may also be implemented via programming equipment. H=Logic High=VIH.DOUT=Data OUT Notes: 1. See "Accelerated Program Operations" for more information. VHH=11.0 0. X=Don't Care. If WP/ACC=VHH. 5. all sectors will be unprotected. or sector protection algorithm. the device enters the accelerated program mode. DIN=Data IN.BUS OPERATION--1 Legend: L=Logic LOW=VIL. the two outermost boot sectors remain protected. the two outermost boot sector protection depends on whether they were last protected or unprotected using the method described in "Sector/Sector Block Protection and Unprotection". SG-0228 . 4. VID=12. If WP/ACC=VIH. A20:A-1 in byte mode (BYTE=VIL). When the WP/ACC pin is at VHH. CONFIDENTIAL – DO NOT COPY Page 7-19 File No.

WRITE COMMANDS/COMMAND SEQUENCES To program data to the device or erase sectors of memory . the device enters the Automatic Select mode. multiple sectors . the system must drive WE and CE to VIL.Code=99 means factory locked. After the system writes the Automatic Select command sequence. or suspending/resuming the erase operation.Code=00h means unprotected. 2. Refer to the Automatic Select Mode and Automatic Select Command Sequence section for more information.BUS OPERATION--2 Notes: 1. SG-0228 . Section has details on erasing a sector or the entire chip. The system can then read Automatic Select codes from the internal register (which is separate from the memory array) on Q7-Q0. or the entire device.An erase operation can erase one sector. Writing specific address and data commands or sequences into the command register initiates device operations. Table A defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. or code=19h not factory locked. A "sector address" consists of the address bits required to uniquely select a sector. CONFIDENTIAL – DO NOT COPY Page 7-20 File No. or code=01h protected. The "AC Characteristics" section contains timing specification table and timing diagrams for write operations.ICC2 in the DC Characteristics table represents the active current specification for the write mode. Standard read cycle timings apply in this mode. and OE to VIH.

PA=Address of the memory location to be programmed. 7. 3. 22A8h(Bottom) Notes: 1.The system may read and program functions in non-erasing sectors. Data is latched on the rising edge of WE or CE pulse.TABLE A. A20=1 to verify sectors 32~70 for Top Boot device. 2. Address bits A20-A12 uniquely select any sector.The data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block. 8. all bus cycles are write operation. 4. SA=Address of the sector to be erased or verified. MX29LV320AT/B COMMAND DEFINITIONS Legend: X=Don't care RA=Address of the memory location to be read.The Reset command is required to return to the read mode when the device is in the Automatic Select mode or if Q5 goes high.The Erase Resume command is valid only during the Erase Suspend mode.The data is 99h for factory locked and 19h for not factory locked.Command is valid when device is ready to read array data or when device is in Automatic Select mode. SG-0228 . 5.The fourth cycle of the Automatic Select command sequence is a read cycle.All values are in hexadecimal. address bit A20=0 to verify sectors 0~31. 9. CONFIDENTIAL – DO NOT COPY Page 7-21 File No. or enter the Automatic Select mode. PD=Data to be programmed at location PA.Except when reading array or Automatic Select data. In the third cycle of the command sequence. when in the erase Suspend mode. ID=22A7h(Top). The Erase Suspend command is valid only during a sector erase operation. 6. RD=Data read from location RA during read operation. Addresses are latched on the falling edge of the WE or CE pulse.

Once the RESET pin is taken high. the device immediately terminates any operation in progress. RESET OPERATION 01The RESET pin provides a hardware method of resetting the device to reading array data.3V.). a CMOS standby mode is achieved with RESET input held at Vss  0. It is not necessary to control CE. the current consumed is less than 0. SG-0228 .The RESET pin may be tied to system reset circuitry. a CMOS Standby mode is achieved with both pins held at Vcc ±0. the current consumed is typically 0. but the standby current will be larger.3V. and ignores all read/write commands for the duration of the RESET pulse. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence.2uA (CMOS level). One is using both CE and RESET pins and the other one is using RESET pin only. When the RESET pin is driven low for at least a period of tRP.MX29LV320AT/B is capable to provide the Automatic Standby Mode to restrain power consumption during readout of data. This mode can be used effectively with an application requested low power consumption such as handy terminals. When using both pins of CE and RESET. independent of the OE input. the device is back to active without recovery delay. To active this mode. The device can be read with standard access time (tCE) from either of these standby modes. Vcc active current (ICC2) is required even CE = "H" until the operation is completed. When using only RESET. A system reset would that also reset the Flash memory. and OE on the mode. CONFIDENTIAL – DO NOT COPY Page 7-22 File No. Under the mode. tristates all output pins. The device also resets the internal state machine to reading array data.3V. If both of the CE and RESET are held at VIH.2uA (typ. to ensure data integrity. If RESET is held at VIL but not within VSS 0. enabling the system to read the boot-up firm-ware from the Flash memory. MX29LV320AT/B automatically switch themselves to low power mode when MX29LV320AT/B addresses remain stable during access time of tACC+30ns. When RESET is held at VSS 0. During Auto Algorithm operation. but not within the range of VCC ± 0.In the standby mode the outputs are in the high impedance state. the device draws CMOS standby current (ICC4).3V. the device will still be in the standby mode.). the standby current will be greater. WE.3V. Current is reduced for the duration of the RESET pulse.STANDBY MODE MX29LV320AT/B can be set into Standby mode with two different approaches. Under this condition. Under this condition the current is consumed less than 1uA (typ.

whichever happens first. If RESET is asserted when a program or erase operation is not executing (RY/BY pin is "1"). All addresses are latched on the falling edge of WE or CE. Either of the two reset command sequences will reset the device (whenapplicable). If the system asserts VIH on the WP/ACC pin. sector protection or unprotection for these two sectors depends on whether they were last protected or unprotected using the method described in "Sector/Sector Group Protection and Chip Unprotection". whichever happens later. The two outermost 8 Kbyte boot sectors are the two sectors containing the lowest addresses in a bottom-boot-configured device. or the two sectors containing the highest addresses in a top-boot-configured device. Writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. inconsistent behavior of the device may result. the RY/BY pin remains a "0" (busy) until the internal reset operation is complete. SOFTWARE COMMAND DEFINITIONS : Device operations are selected by writing specific address and data sequences into the command register. All data are latched on rising edge of WE or CE. Table 3 defines the valid register command sequences. Note that the WP/ACC pin must not be left floating or unconnected. which requires a time of tREADY (during Embedded Algorithms). the device reverts to whether the two outermost 8K Byte boot sectors were last set to be protected or unprotected. Refer to the AC Characteristics tables for RESET parameters and to Figure 14 for the timing diagram. That is. SG-0228 . the reset operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET pin returns to VIH. the device disables program and erase functions in the two "outermost" 8 Kbyte boot sectors independently of whether those sectors were protected or unprotected using the method described in Sector/Sector Group Protection and Chip Unprotection". Note that the Erase Suspend (B0H) and Erase Resume (30H) commands are valid only while the Sector Erase operation is in progress. If the system asserts VIL on the WP/ACC pin. The system can thus monitor RY/BY to determine whether the reset operation is complete. CONFIDENTIAL – DO NOT COPY Page 7-23 File No. WRITE PROTECT (WP) The write protect function provides a hardware method to protect boot sectors without using VID.If RESET is asserted during a program or erase operation.

and RY/BY. Table B. 3. Q3.Reading the byte/word address being programmed while in the erase-suspend program mode will indicate logic "1" at the Q2 bit. 2.Performing successive read operations from the erase-suspended sector will cause Q2 to toggle. successive reads from the erase-suspended sector will cause Q2 to toggle.WRITE OPERATION STATUS The device provides several bits to determine the status of a write operation: Q2. Q7. These three bits are discussed first. Q7.Table B and the following subsections describe the functions of these bits. CONFIDENTIAL – DO NOT COPY Page 7-24 File No. Write Operation Status Notes: 1. SG-0228 . and Q6 each offer a method for determining whether a program or erase operation is complete or in progress. Q6.Performing successive read operations from any address will cause Q6 to toggle. RY/BY. However. Q5.

Fig C. COMMAND WRITE OPERATION Fig D. SG-0228 . READ TIMING WAVEFORMS CONFIDENTIAL – DO NOT COPY Page 7-25 File No.

RESET TIMING WAVEFORM CONFIDENTIAL – DO NOT COPY Page 7-26 File No. SG-0228 .Fig E.

register definition. BA1 select the bank. Block Diagram (16Mb x 16) Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of the device. Note: DM is a unidirectional signal (input only).Prior to normal operation. The following sections provide detailed information covering device initialization. Read and write accesses to the DDR SDRAM are burst oriented. The address bits registered coincident with the Read or Write command are used to select the starting column location for the burst access. 435. Accesses begin with the registration of an Active command. which is then followed by a Read or Write command. dynamic random-access memory containing 268. A0-A12 select the row). SG-0228 . it does not represent an actual circuit implementation. command descriptions and device operation. one-half clock cycle data transfers at the I/O pins. The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. The address bits registered coincident with the Active command are used to select the bank and row to be accessed (BA0. The 256Mb DDR SDRAM is internally configured as a quad-bank DRAM. CONFIDENTIAL – DO NOT COPY Page 7-27 File No. A single read or write access for the 256Mb DDR SDRAM consists of a single 2n-bit wide. 456 bits. the DDR SDRAM must be initialized. but is internally loaded to match the load of the bidirectional DQ and DQS signals. The double-data-rate architecture is essentially a 2n prefetch architecture. with an interface designed to transfer two data words per clock cycle at the I/O pins. one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide.DDR SDRAM (NT5DS16M16CS-5T) Application: Functional Description The 256Mb DDR SDRAM is a high-speed CMOS. accesses start at a selected location and continue for a programmed number of locations in a programmed sequence.

Pin Configuration . SG-0228 .400mil TSOP II (x4 / x8 / x16) CONFIDENTIAL – DO NOT COPY Page 7-28 File No.

SG-0228 . bit A8 set to one. A Mode Register Set command issued to reset the DLL should always be followed by a Mode Register Set command to select normal operating mode. A DLL reset is initiated by issuing a Mode Register Set command with bits A7 and A9-A12 each set to zero. and bits A0-A6 set to the desired values. Test modes and reserved states should not be used as unknown operation or incompatibility with future versions may result.Mode Register Operation Operating Mode The normal operating mode is selected by issuing a Mode Register Set Command with bits A7-A12 to zero. and bits A0-A6 set to the desired values. CONFIDENTIAL – DO NOT COPY Page 7-29 File No. All other combinations of values for A7-A12 are reserved for future use and/or test modes.

Extended Mode Register Definition CONFIDENTIAL – DO NOT COPY Page 7-30 File No. bit A1. these additional functions include DLL enable/disable. These functions are controlled via the bit settings shown in the Extended Mode Register Definition. The Extended Mode Register is programmed via the Mode Register Set command (with BA0 = 1 and BA1 = 0) and retains the stored information until it is programmed again or the device loses power.Extended Mode Register The Extended Mode Register controls functions beyond those controlled by the Mode Register. bit A2 (NTC optional). The Extended Mode Register must be loaded when all banks are idle. bit A0. output drive strength selection. Violating either of these requirements result in unspecified operation. and the controller must wait the specified time before initiating any subsequent operation. and QFC output enable/disable. SG-0228 .

BA1 inputs selects the bank. This row remains active (or open) for accesses until a Precharge (or Read or Write with Auto Precharge) is issued to that bank. Applies only to read bursts with Auto Precharge disabled. BA1 = 0 selects . A10 LOW: BA0. A0-A12 provide the op-code to be written to the selected Mode Register. j = 11] for x4) selects the starting column location. A Precharge (or Read or Write with Auto Precharge) command must be issued and completed before opening a different row in the same bank. other combinations of BA0-BA1 are reserved. this command is undefined (and should not be used) for read bursts with Auto Precharge enabled or for write bursts 9. BA0 = 1. 8. all inputs and I/Os are “Don’t Care” except for CKE. and the address provided on inputs A0-Ai. If Auto Precharge is selected. 11 for x4).” 6. CKE is high for all commands shown except Self Refresh. A10 low disables the Auto Precharge feature. j = don’t care] for x8. BA0-BA1 provide bank address and A0-A12 provide row address. The value on the BA0. 2. The value on the BA0. the row remains open for subsequent accesses.BA1 inputs selects the bank. BA1 determine which bank is precharged. BA0. Internal refresh counter controls row and bank addressing. Deselect and NOP are functionally interchangeable. CONFIDENTIAL – DO NOT COPY Page 7-31 File No. 5. Read The Read command is used to initiate a burst read access to an active (open) row.A10 HIGH: all banks are precharged and BA0.Extended Mode Register. 4. where [i = 9. if Auto Precharge is not selected. BA1 select either the Base or the Extended Mode Register (BA0 = 0. and the address provided on inputs A0-A12 selects the row. SG-0228 .Truth Table a: Commands 1. This command is auto refresh if CKE is high. BA1 are “Don’t Care. 7. Active The Active command is used to open (or activate) a row in a particular bank for a subsequent access. Self Refresh if CKE is low. A0-Ai provide column address (where i = 9 for x8 and 9.) 3. The value on input A10 determines whether or not Auto Precharge is used. BA0. the row being accessed is precharged at the end of the Read burst. BA1 = 0 selects Mode Register. Aj (where [i = 9. A10 high enables the Auto Precharge feature (non-persistent). BA1 provide bank address.

If a given DM signal is registered low. and a Write is not executed to that byte/column location. the row being accessed is precharged at the end of the Write burst. The 256Mb DDR SDRAM requires Auto Refresh cycles at an average periodic interval of 7. BA1 inputs selects the bank. and the address provided on inputs A0-Ai. Self Refresh The Self Refresh command can be used to retain data in the DDR SDRAM. The value on the BA0. The value on input A10 determines whether or not Auto Precharge is used. The Self Refresh command is initiated as an Auto Refresh command coincident with CKE transitioning low. Auto Refresh Auto Refresh is used during normal operation of the DDR SDRAM and is analogous to CAS Before RAS (CBR) Refresh in previous DRAM types.Write The Write command is used to initiate a burst write access to an active (open) row. if the DM signal is registered high. This makes the address bits “Don’t Care” during an Auto Refresh command. the row remains open for subsequent accesses. j = don’t care] for x8. so it must be issued each time a refresh is required. This command is nonpersistent. and is automatically enabled upon exiting Self Refresh (200 clock cycles must then occur before a Read command can be issued). CONFIDENTIAL – DO NOT COPY Page 7-32 File No.When in the self refresh mode. Input data appearing on the DQs is written to the memory array subject to the DM input logic level appearing coincident with the data. A simple algorithm for meeting both refresh and DLL requirements is to apply NOPs for 200 clock cycles before applying any other command. j = 11] for x4) selects the starting column location. the DDR SDRAM retains data without external clocking. CK (and CK) must be stable prior to CKE returning high. the corresponding data inputs are ignored. SG-0228 . Once CKE is high. The DLL is automatically disabled upon entering Self Refresh. the corresponding data is written to memory. if Auto Precharge is not selected. where [i = 9. The procedure for exiting self refresh requires a sequence of commands.8µs (maximum). even if the rest of the system is powered down. the SDRAM must have NOP commands issued for tXSNR because time is required for the completion of any internal refresh in progress. Aj (where [i = 9. If Auto Precharge is selected. Input signals except CKE (low) are “Don’t Care” during Self Refresh operation.The refresh addressing is generated by the internal refresh controller.

In either case. a continuous flow of data can be maintained. assuming no other commands have been initiated.e. DQS is driven by the DDR SDRAM along with output data. the DQs and DQS goes High-Z. 4 or 8) within a page (or pages) can be performed as shown on following: CONFIDENTIAL – DO NOT COPY Page 7-33 File No. Each subsequent data-out element is valid nominally at the next positive or negative clock edge (i. For the generic Read commands used in the following illustrations. During Read bursts. SG-0228 . This is shown in timing figure entitled “Consecutive Read Bursts: CAS Latencies (Burst Length =4 or 8)”. If Auto Precharge is enabled. Upon completion of a burst. provided tRAS has been satisfied. Nonconsecutive Read data is shown in timing figure entitled “Non-Consecutive Read Bursts: CAS Latencies (Burst Length = 4)”. and burst length. The first data element from the new burst follows either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. Data from any Read burst may be concatenated with or truncated with data from a subsequent Read command. Auto Precharge is disabled. Full-speed Random Read Accesses: CAS Latencies (Burst Length = 2. the low state coincident with the last data-out element is known as the read postamble . the row that is accessed starts precharge at the completion of the burst. where x equals the number of desired data element pairs (pairs are required by the 2n prefetch architecture). The initial low state on DQS is known as the read preamble. The following timing figure entitled “Read Burst: CAS Latencies (Burst Length=4)” illustrates the general timing for each supported CAS latency setting.Operations: Reads Subsequent to programming the mode register with CAS latency. The starting column and bank addresses are provided with the Read command and Auto Precharge is either enabled or disabled for that burst access. burst type. Read bursts are initiated with a Read command. The new Read command should be issued x cycles after the first Read command.A Read command can be initiated on any positive clock cycle following a previous Read command. the valid data-out element from the starting column address is available following the CAS latency after the Read command. at the next crossing of CK and CK).

SG-0228 . 4 or 8) CONFIDENTIAL – DO NOT COPY Page 7-34 File No.Random Read Accesses: CAS Latencies (Burst Length = 2.

In either case. as shown in timing figure Write Command on following: The starting column and bank addresses are provided with the Write command. so most of the Write diagrams that follow are drawn for the two extreme cases (i. Upon completion of a burst. a continuous flow of input data can be maintained. Timing figure Write Burst (Burst Length = 4) on page 33 shows the two extremes of tDQSS for a burst of four. CONFIDENTIAL – DO NOT COPY Page 7-35 File No. If Auto Precharge is enabled. the DQs and DQS enters High-Z and any additional input data is ignored. and Auto Precharge is either enabled or disabled for that access.Read Command Writes Write bursts are initiated with a Write command. The time between the Write command and the first corresponding rising edge of DQS (tDQSS) is specified with a relatively wide range (from 75% to 125% of one clock cycle). For the generic Write commands used in the following illustrations.e. the row being accessed is precharged at the completion of the burst.Data for any Write burst may be concatenated with or truncated with a subsequent Write command. the first valid data-in element is registered on the first rising edge of DQS following the write command. Auto Precharge is disabled. and subsequent data elements are registered on successive edges of DQS. SG-0228 . the Low state on DQS following the last data-in element is known as the write postamble. tDQSS(min) and tDQSS(max)). The Low state on DQS between the Write command and the first rising edge is known as the write preamble. During Write bursts. assuming no other commands have been initiated.

The new Write command should be issued x cycles after the first Write command.The new Write command can be issued on any positive edge of clock following the previous Write command. SG-0228 . The first data element from the new burst is applied after either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. Write Command Data Input (Write) CONFIDENTIAL – DO NOT COPY Page 7-36 File No. where x equals the number of desired data element pairs (pairs are required by the 2n prefetch architecture).

SG-0228 .Data Output (Read) CONFIDENTIAL – DO NOT COPY Page 7-37 File No.

and EIAJ CP1201 interface standards. dedicated pins are used to select audio stream inputs for decoding and transmission to a dedicated TX pin.IEC60958. operate at the VL voltage. Please note that all I/O pins. The CS8416 utilizes an 8:2 multiplexer to select between eight inputs for decoding and to allow an input signal to be routed to an output of the CS8416. In hardware mode. The channel status and Q-channel subcode portion of the user data are assembled in registers and may be accessed through an SPI or I²C port. including RXN and RXP[7:0]. The decoded audio data is output through a configurable. Input data is either differential or single-ended.Optical Receiver CS8416 Application: The CS8416 is a monolithic CMOS device which receives and decodes audio data according to the AES3. S/PDIF. Figure A and Figure B show the power supply and external connections to the CS8416 when configured for software and hardware modes. A low jitter clock is recovered from the incoming data using a PLL. Three General Purpose Output (GPO) pins are provided to allow a variety of signals to be accessed under software control. Hardware mode also allows direct access to channel status and user data output pins. SG-0228 . CONFIDENTIAL – DO NOT COPY Page 7-38 File No.3-wire serial audio output port.

Software Mode CONFIDENTIAL – DO NOT COPY Page 7-39 File No. SG-0228 . Typical Connection Diagram .TYPICAL CONNECTION DIAGRAMS Figure A.

and a decoder which separates the audio data from the channel status and user data. driven through analog input pins RXP0 to RXP7 and a common RXN. CONFIDENTIAL – DO NOT COPY Page 7-40 File No. External components are used to terminate the incoming data cables and isolate the CS8416. The receiver accepts and decodes bi-phase encoded audio and digital data according to the AES3.Hardware Mode S/PDIF RECEIVER The CS8416 includes an AES3/SPDIF digital audio receiver. IEC60958 (S/PDIF).Figure B. a PLL based clock recovery circuit. Typical Connection Diagram . Figure 9 shows the input structure of the receiver. and EIAJ CP-1201 interface standards. These components are detailed in “Appendix A: External AES3/SPDIF/IEC60958 Receiver Components” on page 51. The receiver consists of an analog differential input stage. SG-0228 .

Receiver Input Structure 8:2 S/PDIF Input Multiplexer The CS8416 employs a 8:2 S/PDIF input multiplexer to accommodate up to eight channels of input digital audio data. If RXP[7:0] is selected by both the receiver MUX and the TX passthrough MUX.e. Differential inputs utilize RXP[7:0] and a shared RXN. Figure.All active inputs to the CS8416 8:2 input multiplexer should be coupled through a capacitor as these inputs are biased at VL/2 when selected. N=0 (i. If RXP[7:0] is not selected at all.If RXP[7:0] is selected by either the receiver MUX or the TX passthrough MUX. high impedance). The recommended capacitor value is 0. N=2. VL. These inputs are floating when not selected.The input voltage range for the input multiplexer is set by the I/O power supply pin. CONFIDENTIAL – DO NOT COPY Page 7-41 File No. N=1. Digital audio data may be single-ended or differential. Unused multiplexer inputs should be left floating or tied to AGND. Input signals with voltage levels above VL or below DGND may degrade performance or damage the part.01 µF to 0. Single ended signals are accommodated by using the RXP[7:0] inputs and AC coupling RXN to ground. SG-0228 .The recommended dielectrics for the AC coupling capacitors are C0G or X7R. The input voltage of the RXP[7:0] and RXN pins is also set by the level of VL.1 µF.

The multiplexer defaults to RXP0. In Software mode the automatic clock switching feature is enabled by setting SWCLK bit in Control1 register to a “1”. This singleended signal is resolved to full-rail. RXSEL[1:0]. the OSCLK and OLRCK will be based on the VCO when the PLL is not locked.Software Mode The multiplexer select line control is accessed through bits RXSEL[2:0] in control port register 04h. Table 2 shows an example of output clocks based on clock switching being enabled or disabled. OSCLK and OLRCK are derived from the OMCK input when the clock has been switched and the serial port is in master mode. once the clock switching feature has been enabled. but is not de-jittered before it is output.The pass through signal is selected by dedicated pins.This single-ended signal is resolved to full-rail. OMCK can be manually forced to output on RMCK by using the FSWCLK bit in the Control0 register.Selectable inputs are restricted to RXP0 to RXP3 for both the receiver and the TX output pin. This pass through signal is selected by TXSEL[2:0] in control port register 04h.the frequency of the VCO drops to ~500 kHz. This is accomplished without spurious transitions or glitches on RMCK. When clock switching is enabled and the PLL is not locked. OMCK System Clock Mode A special clock switching mode is available that allows the OMCK clock input to automatically replace RMCK when the PLL becomes unlocked. but is not de-jittered before it is output. Therefore to not enable the clock switching feature in Hardware mode. Additionally in Software mode. However. Hardware Mode In hardware mode the input to the decoder is selected by dedicated pins. In Hardware mode this feature is enabled by a transition (rising edge active) on the OMCK pin after reset. CONFIDENTIAL – DO NOT COPY Page 7-42 File No. OLRCK will be OMCK/256 and OSCLK will be OMCK/4. in Hardware mode. OMCK should be tied to DGND or VL. When this system clock mode is not enabled. These inputs are selected by RXSEL[1:0] and TXSEL[1:0] respectively. TXSEL[1:0] for output on the dedicated TX pin. The second output of the input multiplexer is used to provide the selected input as a source to be output on a GPO pin. SG-0228 .When the clock switching feature is enabled. it can only be disabled by resetting the part. When the PLL loses lock.

All GPO pins default to GND after reset.Table. and layout considerations. Clock Switching Output Clock Rates Clock Recovery and PLL Filter Please see “Appendix C: PLL Filter” on page 55 for a general description of the PLL. SG-0228 . GENERAL PURPOSE OUTPUTS Three General Purpose Outputs (GPO) are provided to allow the equipment designer flexibility in configuring the CS8416. The outputs of the GPO pins are set through the GPOxSEL[3:0] bits in the Control2 (02h) and Control3 (03h) registers. selection of recommended PLL filter components. Fourteen signals are available to be routed to any of the GPO pins. Figure 5 and Figure 6 shows the recommended configuration of the two capacitors and one resistor that comprise the PLL filter. GPO pins may be configured to provide the following data: CONFIDENTIAL – DO NOT COPY Page 7-43 File No.

Table. GPO Pin Configurations Notes: 16. Frequency = 25 MHz Max, duty cycle not guaranteed, target duty cycle = 50% @ FS = 48 kHz.

CS8416 Block Diagram.

MP7720/7722 Application
In JV50P TV the MP7720 is a mono 10W Class D Audio Amplifier and the MP7722 is a stereo 10W Class D Audio Amplifier. It has each output power of 10 W at 24V supply into a 6 ohm load.

CONFIDENTIAL – DO NOT COPY

Page 7-44 File No. SG-0228

TYPICAL APPLICATION for MP7720

TYPICAL APPLICATION for MP7722

CONFIDENTIAL – DO NOT COPY

Page 7-45 File No. SG-0228

1. DESCRIPTION The MP7722 utilizes a single ended output structure capable of delivering 2 x 20W into 4Ω speakers. MPS Class D Audio Amplifiers exhibit the high fidelity of a Class A/B amplifier at efficiencies greater than 90%. The circuit is based on the MPS’ proprietary variable frequency topology that delivers low distortion, fast response time and operates on a single power supply.

2. Output power measurement
The output power as a function of the supply voltage is measured on the output pins at THD = 10%,in the JV50P TV Vcc=24V so we can see as shown in the following figure output.

CONFIDENTIAL – DO NOT COPY

Page 7-46 File No. SG-0228

drive EN with a 2. CONFIDENTIAL – DO NOT COPY Page 7-47 File No.0V or greater voltage. To enable the MP7722.4V. To disable the Amplifier. Mute/Enable Function The MP7722 EN inputs are active high enable controls. the VDD operating current is less than 10µA and the output driver MOSFETs are turned off. drive it below 0.3. While the MP7722 is disabled. SG-0228 . The MP7722 requires approximately 500ms from the time that EN is asserted (driven high) to when the amplifier begins normal operation.

CONFIDENTIAL – DO NOT COPY Page 7-48 File No. It has output power of 1 x50 W into 6 ohm with 24V supply. this device exhibits the high fidelity of a Class AB amplifier with an efficiency of 90%. SG-0228 .MP7782 Application In JV50P TV the MP7782 is a mono. As in all other MPS Class D audio amplifiers. 50W Class D Audio Amplifier. TYPICAL APPLICATION DESCRIPTION The MP7782 utilizes a full bridge output structure capable of delivering 50W into 6Ω speakers.

CH2 V-sync (L53) CONFIDENTIAL – DO NOT COPY Page 8-1 File No.Chapter8 Waveforms PC MODE(1366X768 60HZ) CH1 H-sync (R209). SG-0228 . CH2 H-sync (L52) CH1 V-sync (R213).

SG-0228 .CH1 R (R203) CH1 R (C95) CH1 B (R199) CH1 B (C92) CONFIDENTIAL – DO NOT COPY Page 8-2 File No.

CH1 G (R195) CH1 G (C89) AV&TV MODE (AV1/AV2/TV) VIDEO CH1 TV CONFIDENTIAL – DO NOT COPY Page 8-3 File No. SG-0228 .

SG-0228 .CH1 AV1 CH1 AV2 CONFIDENTIAL – DO NOT COPY Page 8-4 File No.

COMPONENT MODE CH1 YPBPR1_Y CH1 YPBPR2_Y CONFIDENTIAL – DO NOT COPY Page 8-5 File No. SG-0228 .

SG-0228 .HDMI 1 CH1 RX1. CH2 RX1-B HDMI 2 CH1 RX1. CH2 RX1-B CONFIDENTIAL – DO NOT COPY Page 8-6 File No.

HDMI 3 CH1 RX1. SG-0228 . CH1: C200 + . Frequency: 1KHz (L and R and CT) 1. CH2 RX1-B Audio BD of TV Î Input Level: 100mV . CH2: J3 PIN3 CONFIDENTIAL – DO NOT COPY Page 8-7 File No.

CH1: C108 - . SG-0228 . CH2: U1 PIN7 3.2. CH1: ZD2 PIN2 . CH2: ZD2 PIN1 [signal on] CONFIDENTIAL – DO NOT COPY Page 8-8 File No.

[signal off] CH1: C271 + . CH2: J3 PIN3 CONFIDENTIAL – DO NOT COPY Page 8-9 File No. SG-0228 .

SG-0228 . CH1: ZD4 PIN2 .4. CH2: ZD4 PIN1 [signal on] [signal off] CONFIDENTIAL – DO NOT COPY Page 8-10 File No.

CH1: C192 + [Power on] . SG-0228 . CH2: EN1 [Power off] CONFIDENTIAL – DO NOT COPY Page 8-11 File No.5.

CH1: C108 - .Audio BD of Subwoofer Î Input Level: 100mV . SG-0228 . CH1: C200 + . CH2: U1 PIN7 CONFIDENTIAL – DO NOT COPY Page 8-12 File No. Frequency: 1KHz (LS and RS) 50Hz (Subwoofer) 1. CH2: J3 PIN3 2.

3. CH2: ZD2 PIN1 [signal on] [signal off] CONFIDENTIAL – DO NOT COPY Page 8-13 File No. CH1: ZD2 PIN2 . SG-0228 .

CH1: C170 + . CH2: J4 PIN2 5. CH1: ZD4 PIN2 . SG-0228 .4. CH2: ZD4 PIN1 [signal on] CONFIDENTIAL – DO NOT COPY Page 8-14 File No.

CH1: C192 + [Power on] .[signal off] 6. SG-0228 . CH2: EN1 CONFIDENTIAL – DO NOT COPY Page 8-15 File No.

SG-0228 . CH2: C142 + CONFIDENTIAL – DO NOT COPY Page 8-16 File No.[Power off] 7. CH1: R154 [Power on] .

CH1: R228 [Power off] .[Power off] 8. CH2: EN1 CONFIDENTIAL – DO NOT COPY Page 8-17 File No. SG-0228 .

3.Check J10 PIN14 2. LED is lighted Is Power board output +5VSB &DV12? Is J10 connector good? Is DC-DC OK? Is U1 (+5V) working ok? Yes N0 LED is lighting? It is in power saving 1. Check video cable 2.Is J7 connecting OK? 2.Chapter 9 Trouble shooting MONITOR DISPLAY NOTHING (PC MODE) Start N0 1. Check P3 D-sub Input correct 5.Is Power Board ok? Yes Yes N0 U14 no data out? It means data to LVDS 1. Check sync input 4.Is panel ok? 4. 2. 4. Check analog input route Yes END CONFIDENTIAL – DO NOT COPY Page 9-1 File No. Check VGA SOG rout if analog (SOG) Yes N0 Is backlight on? 1. SG-0228 . Is the timing supported? 3.Check J1 +5V & +12V 3.

Is panel working ok? END CONFIDENTIAL – DO NOT COPY Page 9-2 File No. Check U14 :DV33&DV12&AV15&AV12 2.Check video 2. COMPOSITE VIDEO ) IS NOT DISPLAY CORRECTLY Start N0 Input signal good? 1.Check U14 clock (27MHz) 3.Check LVDS 5V or 12V Yes 1.Check signal between U14 (IF IN AV mode) 3. SG-0228 .Chcak J7 Connect is good? 2. Check X1 is OK? Yes N0 LVDS output correct? 1.Check P11(VIDEO) signal 2.(TV.Check Tuner & U13 (IF TV mode) Yes N0 U14 output correct? 1.Check LVDS LINE 2.Check DVD player Yes N0 U14 input correct? 1.

Check host’s setting Yes N0 P1 input correct? 1.Is J7 connected good? 2.Check U14 2.Check video 2. SG-0228 .Check U14 Clock (27MHZ) 3.Check signal between U14&P1 2.Is panel working ok? END CONFIDENTIAL – DO NOT COPY Page 9-3 File No. Check LVDS 5V or 12V Yes 1.(COMPONENT) IS NOT DISPLAY CORRECTLY Start N0 Input signal good? 1.Check signal between P1 2.Check U14 :DV33&DV12&AV15&AV12 Yes N0 LVDS output correct ? 1.Check power 12V& 5v Yes N0 U14 input correct? 1.

Check U22 signal Yes N0 U14 no data out ? 1.Check host’s setting N0 U22 input correct? 1.(HDMI) IS NOT DISPLAY CORRECTLY Start N0 Input signal good? 1.Check p6 & p7& P13 connect 2.Check U14 power 2.Is J7 connected good? 2.Check between signal U22 and U14 3.Check U14 clock 27MHZ Yes 1.Check video 2. SG-0228 .Is panel working ok? Yes END CONFIDENTIAL – DO NOT COPY Page 9-4 File No.

3V Yes N0 U7 pin2 The voltage is about +1.Check power board 2.Check power cable connection J10 Yes N0 J10 PIN 2.J10 connection good 2.Check power board Yes N0 U1 pin 5 6 7 8 The voltage is about +5V while power switch on 1.3 transform +5V_TUNER 3.ROUBLE OF DC-DC CONVERTER Start Yes N0 J10 PIN10.11. Check U14 OPWRSB & OPCTRL2 Pin Yes N0 U4.5V Yes U35 pin2 The voltage is about +3. SG-0228 .3 The voltage is about + 12V while power switch on 1.U2 pin2 The voltage is about +3.6V Yes N0 U33 pin2 The voltage is about +3.J10 connection good 2.12 The voltage is about + 5V 1.3V Yes N0 U10 pin2 The voltage is about +2.3V END CONFIDENTIAL – DO NOT COPY Page 9-5 File No.2V Yes U9 pin2 The voltage is about +1.Check J10 Pin2.

Check signal (U23 to P6) 3.Is compliant protocol? Yes N0 HDMIDDC Support DDC1/2B 1.Check signal (U26 to P13) 5.Analog cable ok? 2.Is compliant protocol? Yes END CONFIDENTIAL – DO NOT COPY Page 9-6 File No.Analog cable ok? 2.TROUBLE OF DDC READING Start Yes N0 Analog DDC Support DDC1/2B 1.Check signal (U21 to P3) 3. SG-0228 .Check U21 Voltage 4.Check signal (U25 to P7) 4.

Check C200(Ch R) and C201(Ch L) and C271 (Ch CT) Yes N0 U7. Check signal of Audio Board (J1) 3.R271). Check Audio source 2. Check ZD2(Ch R) and ZD3(Ch L) and ZD4 (Ch CT) Yes N0 U7. Check feedback resistor and capacitor. 3.U2 output correct? Yes N0 U7.U8 output correct? 1. AUDIO) IS NOT DISPLAY CORRECTLY Start N0 Input signal good? 1. Check signal of Main Board 2. Check 1/2VCC of U7 and U8 (R202. Check the wire of Main Board to Audio Board Yes N0 1. SG-0228 . Yes END CONFIDENTIAL – DO NOT COPY Page 9-7 File No. U1. Check VCC of U7 and U8. Check the output volt of U1 and U2.R203.U8 signal correct? 1. 2. Check the player of source Yes N0 J1 input correct? 1.(TV_SIDE.U8 Volt correct? 1.

(SUBWOOFER_SIDE. U1~U6output correct? Yes N0 U7. Check the player of source Yes N0 J1 input correct? 1. SG-0228 . Check signal of Audio Board (J1) 3. Check feedback resistor and capacitor. 2. Check VCC of U7 and U8.U8 signal correct? 1. Having TX and RX module or not? Yes N0 1. 3. AUDIO) IS NOT DISPLAY CORRECTLY Start N0 Input signal good? 1. Check ZD2(Ch R) and ZD3(Ch L) and ZD4 (Ch CT) Yes N0 U7.U8 output correct? 1. Check signal of Main Board 2. Check Audio source 2. Check C200(Ch R) and C201(Ch L) and C170 (Ch SW) and C171 (VB) Yes N0 U7. Check 1/2VCC of U7 (R202.R203).U8 Volt correct? 1. Check the output volt of U1 ~ U6. Yes END CONFIDENTIAL – DO NOT COPY Page 9-8 File No.

treble. TV. The analog video signals of YPbPr. surround. the MT5372 Ic process the signals control the various functions of the monitor and outputs control signal. Simultaneously. The main board receives different types of video signal into the MT5372 Ic. all functions in the IC boards are programmable using I2C Bus. pixel on/off and the color displayed on the panel. TV. All functions are controllable by the main board. the digital video signals are processed in the panel and the outcome determines the brightness. and balance.Chapter 10 System Block Diagram Block Diagram LG50” X4 panel Speaker Digital Video bus Power Board AC IN Audio Board J14 TX Connect J9 J7 J10 J12 Main Board U12 J4 P1 P2 P11 Tuner AVX2 P10 P9 □□□□□ Keypad/IR Board P5 P14 P13 P7 P6 P8 P3 P4 YPBPRX2 RCAX2 RJ11 AUX IN HDMIX3 RCA RGB earphone SPDIF out Audio OUT The TV system block diagram is powered by power board that transforms AC source of 100V~240V AC +/. Afterward. SG-0228 . The power send to the panel is first processed by the inverter. PC and A/V is transmitting to the MT8291 processed. The analog audio of YpbPr. The function of the inverter is to step up the voltage supplied by the main board to the power that is needed to light up the lamps in the panel. PC and A/V all video signals are translated from analog signals into MT5372 generates the vertical and horizontal timing signals for display device. bass. Plus. CONFIDENTIAL – DO NOT COPY Page 10-1 File No. The purpose is process the input audio signal to control volume.10% @ 50/60 HZ into DC 5V & 12V& 24Vsource. video signal and power to the LG50” X4 panel to be displayed.

SG-0228 .Main Board Block Diagram CONFIDENTIAL – DO NOT COPY Page 10-2 File No.

TV_AMP Board Block Diagram CONFIDENTIAL – DO NOT COPY Page 10-3 File No. SG-0228 .

RX_AMP Board Block Diagram CONFIDENTIAL – DO NOT COPY Page 10-4 File No. SG-0228 .

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