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Complete Digital Control Method for PWM DCDC Boost Converter

Christian Kranz
Infineon Technologies AG Secure Mobile Solutions Diisseldorf, Germany

Abstruct-A complete digital control method for low noise constant frequency pulse width modulated (PWM) DCDC boost converter is described. The control algorithm is part of the power supply system on a battery driven integrated CMOS circuit. The only analog on chip component needed is a low hysteresis CMOS input pad or a comparator with reference voltage. For that it is best suited for Systems On a Chip (SOC) implementations and features all advantages of digital circuits like easy shrink to new technologies,one time development effort, low chip size, low power dissipation and so on.



I. INTRODUCTION The output voltage control of switching DCDC power supplies is usually implemented as a mixed signal system, using analog control loops and a digital switch signal for the power stage. In contrast the control method described here is complete digital. Of course each digital control of analog systems needs a sort of analog to digital converter. If the IC area consumption andor the development effort for the A/D exceeds that of the analog error and feedback amplifier a digital control algorithm makes no sense in terms of effort and cost minimization. Because of that the concept described here is especially developed to minimize the analog effort. The only analog component needed for the A/D conversion is a comparator or in its simplest implementation a low hysteresis CMOS input pad. The main advantages of the new concept are less chip area compared with an analog control loop implementation low power consumption because of low clock frequency and deep sub micron CMOS technology resulting in higher efficiency constant control loop parameter over production stability guaranteed after digital simulation possibility to go closer to the stability limits no noise influence in control algorithm easy adaptation of non-linear methods like detection and reaction to heavy load changes easy adaptation to dynamic changes in the power stage (CCM DCM) during operation The principle circuit of the DCDC boost converter can be seen from fig 1. It consists of on chip power switches, the digital control circuit, the digital PWh4 modulator, the analog comparator and the external parts like coil (L), capacitance (C) and load (here simply a resistor Rload).

dotted region chip mternal

Fig. 1. Principle of the DCDC boost converter

The control algorithm is designed for a high dynamic output current range - supporting seamless switching between discontinuous conduction mode (DCM) and continuous conduction mode (CCM). It is not needed to design for one particular conduction mode only and lose efficiency because of backward currents if the output load is not high enough. Stability over the whole output current range is given without using current mode control. This paper describes the control algorithm in detail and gives an application example for the practical implementation. It is a single battery cell power supply for a Bluetooth headset with input voltage range from 0.9V to 1.7V, output voltage 3.3V and output current 35pA to 100mA. The performance is demonstrated by simulation and measurement results. 11. HOW TO MEASURE THE OUTPUT ERROR SIGNAL To minimize analog components and effort only a comparator, comparing the output voltage with a reference voltage, is used. That leads normally to a 2 point regulation or pulse frequency modulation (PFM). Performance behavior of a DCDC converter with 2 point regulation is bad. Fast load changes are leading to unacceptable over- and undershoots. The PFM has the disadvantage that its noise spectrum is not fixed (and the switching frequency can not be synchronized to a reference clock) and therefore leads to unacceptable noise folding into the audible frequency range in audio applications. To overcome the problems of a missing A/D a special characteristic of the DCDC boost converter output voltage is used here. Figure 2 shows the idealized output voltage for one pulse

0-7803-7754-0/03/$17.00 02003 IEEE

95 1



coil discharge


Fig. 2. Boost converter output voltage and PWM signal in CCM mode

Fig. 4. Quantizer Characteristics for N - p i even and odd

PWM signal

col1 charge

coil discharge

* t i m e

Fig. 3. Boost converter output voltage and PWM signal in DCM mode

with a higher clock frequency fc = $ than the PWM pulse repetition time T and counting up if the comparator output is high and counting down if it is low, the counter value cnt indicates the control error. If cnt is zero Vo is equal V&. It is N - p i where pi is the discrete pulse width (number of fc clocks the PWh4 signal is high) if 2 V,,f it is - ( N -pi) if VI 5 V,,f. The resulting quantizer characteristic can be seen in fig. 4. It can also be seen that the quantizer characteristic changes depending on ( N - p i ) even or odd. That means for the control error signal:

period T of a fixed frequency PWM driven power stage with pulse width p in continuous conduction mode (CCM). CCM means that the coil current will be greater than zero all the time. Fig. 3 shows the same signals for discontinuous conduction mode (DCM). In DCM the coil current reaches zero in the second part of the PWM pulse. The coil is charged if the PWM signal is high (n-channel FET switches it to ground). Switching the PWM signal to low discharges the coil and the main part of the coil current charges the output capacitance. Because of the capacitance serial resistor Rc (ESR) the output voltage jumps to Vl and follows the coil current time behavior. It decreases until the coil current reaches zero or the PWM signal switches back to high. The output

cnt = { - ( N - p i ) , . . . , ( N - p i ) }
The coil currents difference can be calculated as T iL1 - i L 2 = (1 - P)- (yn- V O - Vdiode)



and with that the voltage difference VI - V 2 as

vl - fi = (1

(h - VO - V d i o d e )


voltage has now reached


V 2 greater than V indicates

CCM mode. In a good approximation the decrease of the coil current is linear in time. The main idea to get a more accurate indication of the output voltage error is using the linear falling edge of the output voltage triangle. For that the target output voltage Vo is chosen to be on the middle of the falling output voltage triangle. That means the comparator should change its output value in the middle of the second half of the PWM pulse. As long as the output voltage will cross the target value in the falling edge of the output voltage triangle a linear relationship between target and output voltage can be obtained for the control algorithm. To get a digital representation of the output error a up- and down counter is used, counting only during the second part of the PWM pulse (PWM signal is low). Running this counter

Equations (1) and (4) are combined to get the transfer function of the output voltage measurement




(Kef - VO) (5) 2 N L ( R l o a d + RC) 1 (6) T &adRC (Vdiode + VO - K n )

Note that equation (6) is independent from the pulse width p. On the other hand it is only valid for CCM mode because only in this mode the counting time is as long as the falling edge of the output voltage triangle. In DCM mode the counting time is longer than the output voltage fall time. This leads to wrong counter results. To overcome this problem an estimation of the coil discharge time is used to correct the counter value. As example the control error measurement resolution is calculated with T = 5p5, N = 64, L = 22pH, & = 10,









Pl 0.993









Fig. 5 .

Small signal model for control loop


>> Rc, vo

= 3.3v,

= 0.3V and AV =

K e f - VOas

4.2mV.cnt for Kn = 1.2V = 238 = 3.3mV. mt for V,, = 1.7V = 303

which corresponds to a AID converter with a resolution greater than 9-bit over the whole output voltage range of 0 . . .3.3V. O f course the error signal will saturate if the output error is greater or less than covered by the output voltage triangle.


A. CCM Power Stage The small signal model of the control loop (fig. 5) consists of a digital small signal replacement of the PWM power stage G s ( z ) ,the control algorithm G,(z), the A/D gain stage /CAD and the subtractor for building the error signal. This linearized model represents the ac behavior at a given operating point of the power stage. The power stage transfer function is calculated with help of the methods described in [l] or [2]. In a first step the analog model is calculated. Than it is transferred into the digital domain by using the bilinear In addition the sample&hold transformation s 4 function has to be added to reflect the sampling of the analog output signal. This results in the ac transfer function, pulse width p ( z ) against output voltage V ( z )


Fig. 6. CCM Transfer Function of the Power Stage for 1.2V, p = 0.8


function is to keep the digital circuit as simple as possible. The gain kCl will be implemented using shift and add technique instead of a real multiplication. The closed loop transfer function of the system is now given

and an example closed loop transfer function for Vin = 1.2V,p = 0 . 8 , k ~ =~ 238,k,1 = 0.125 and the application power stage components is depictured in figure 7.

Example coefficients for the used power stage components in CCM mode are given in table I. The dynamic depends mainly on the DC point of the pulse width P and on the input supply & . voltage I A PI (proportional integral) type control function is used.

B. DCM Power Stage I ) Switching point between DCM and CCM mode: The control circuit as considered until now is only valid in CCM of the power stage. For DCM the small signal behavior changes totally so that a different control function is needed here. An important task of the control algorithm is now to detect whether the power stage is in CCM or DCM mode. The decision has to be made out of the calculated pulse width. To calculate the pulse width limit where to switch from DCM to CCM the time t d for discharging the coil from current ILO to zero can be calculated as

Here the advantage of exact determined parameter in a digital implementation is used for choosing a transfer function with limited stability. G, ( z )has limited stability because it's pole is on the unit circle. This ensures high speed control although a integra1 control function is used. There is no risk that the pole will move outside the unit circle as in analog systems. In the closed loop transfer function there will be no pole on the unit circle any more. Another reason for using this simple control

with coil current assumed to be linear in time and the coil



Closed Loop Transfer Funcuon G(z)









Fig. 8. Block Figure of the Complete Digital Control Function

Fig. 7. Closed Loop Transfer Function 1.2V, p = 0.8, CCM

with pcnt the counter value of the second up only counter and pcnttarget the estimated value for p c n t from the pulse width from the previous period p ( k - 1)

voltage constant. Using the coil charge time t,

T t , = pv,,(1 1) Once in the digital domain it is possible to implement L more complex signal processing normally not done in the the pulse width p,, can be calculated, where switching analog domain. E.g. it is possible to implement a digital between DCM and CCM occurs at tc + td = T . Combining reference system, adapted to the external components. Using (10) and (1 1) finally results in the mode switching pulse width this reference system estimations of the load current and/or PSW. input voltage can be made and used to improve the control behavior further or to detect overload situations. It is also possible to change the control behavior (e.g. by software) From (12) it can be seen that pSw depends on the input voltage depending on the state of the complete system (TX active, I/zn, not known from explicit measurements by the control low power, idle .. .). In this implementation a pulse width algorithm. Of course it is possible to estimate the input voltage. boost function is added. This function increases or decreases E.g. if the state and the corresponding load current of the the pulse width much faster as usual if a heavy load change system is known (e.g. idle, transmitter active) the input voltage is detected. Such load changes can be easy detected if the can be easily calculated from the pulse width chosen by the error signal is at its limit for some pulse periods. Large signal control algorithm. behavior (not covered properly by the ac models) is improved On the other hand it has been seen that the control system significantly using this feature. behavior is not very sensitive concerning a wrong estimated Finally the pulse width is limited to a suitable range. Here pa,. It can be shown using simulations and practical mea- it is allowed to be between 0 . . .54, ( N = 64). Figure 8 is a surements, considering all circuit component tolerances, that block figure of the complete digital control circuit. a precalculation of p,, for typically parameter is sufficient IV. COMPONENT SPECIFICATION for a proper system behavior. Thus (12) is used with the d i o & and K, to precalculate p , , for the A. Output Capacitor typical values for V control algorithm. p,, is than not changed any more during The output capacitance will in general be selected to operation. That leads to the most sihple implementation. For the application described here the switching point psw is limit output voltage ripple as required by the output voltage specification. Unfortunately this situation does not hold for calculated with K n = 1.2V as p,, = 0.67. 2 ) Control Function in DCM: As can beseen from fig. 3 an power supplies in high volume production. Because of the high upldown counter running in the second part of the P W M signal pressure on the system costs normally the type of capacity with will not give a sufficient error signal in DCM mode. That is the lowest cost has to be selected. This means on the other because the coil discharge time is shorter than (1 - p ) T and hand that the system has to be designed that it can life with the time the comparator output is low is always greater than the resulting "bad" power supply. In the Bluetooth headset the time it is high if the control system is settled. Therefore an application the system is a one chip solution and the complete estimation of the coil discharge time is used. The estimation power supply concept and resulting effects are in the hand is simplified by using a second up only counter, counting only of the IC architect. Here the system is designed to accept a in the second part of the PWM signal if the comparator output 350mV ripple on the DCDC output voltage without influence on the audio and RF performance. That means aluminum is positive. electrolytic capacitors, available for the lowest cost, are chosen The chosen control function for DCM is as the output capacitance here. The parameters of the chosen capacitor are given in table 11.

C. Further Improvement of the Control Circuit





Iv , , , 1 I 6.3V 1

0.09 ... 0.26


Rc ( E W
1.2R ... 3.5R

B. Comparator

1) Comparator Resolution: The comparator must be able to detect the falling edge of the capacitor voltage change caused by the inductor current at its ESR Rc. Most critical is the lowest detection level. It is given for the lowest possible pulse width - that means for p i = $. In this case from (6) the minimum resolution can be calculated as

Fig. 9. Load current 53mA, input voltage 1.2V. CCM mode

For the given application it is 3.3mV. 2) Comparator Speed: The highest comparator speed (slew rate) is needed for the maximum output current. In this case the comparator should settle to the output voltage change in less than one sampling period if the n-channel FET (SWl) is opened. The output voltage change can be calculated using (3) and the lowest V,, = 0.9 as



i ~1 i ~ 2 ) R= c

120mA. 3.5Q = 420mV (16)

For the minimum slew rate follows (with sampling frequency 13hfH.z) SR = 5 . 5 V / p ~ . 3) Comparator Input Offset: The comparator input offset voltage leads directly to an proportional output voltage error. Therefore the input offset requirements are related to the allowed output voltage tolerance. In practical circuits an input offset less than 30mV can be easily achieved without using special techniques for offset reduction. This leads to an output error of less than 1% due to the comparator offset voltage.

DCM mode Fig. 10. Load current lmA, input voltage 1.7V,

The DCDC boost converter is designed to be part of a single chip Bluetooth controller for Bluetooth headsets. Bluetooth headsets are worn directly at the ear - requiring low size and low weight - therefore it is desirable to use only one (primary or rechargeable NiMH) battery cell with 0.9V. . .1.7V supply voltage range. This battery cell has to supply the whole headset system, the RF transceiver, microphone amplifier, audio A/D and D/A, earpiece driver, Bluetooth baseband controller and pC, LEDs . . .. For that a min. supply voltage of 3.0V is required. Because of the noise sensitivity of the RF- and the audio part a simple pulse frequency modulation (PFM) can not be used. Thus a low noise fixed frequency pulse width modulated (PWM) boost converter architecture is chosen. The load current in a Bluetooth headset spans the range of 35pA in idle mode up to lOOmA peak current in full load mode. Because of cost and PCB size reasons all active components of the DCDC converter will be integrated together with the bluetooth and headset functionality on one chip.

Nevertheless the first implementation of the algorithm was done using a discrete power stage with a n-channel FET for SW1 and a Schottky diode for SW2, an external comparator and a FPGA providing the digital circuits. The digital circuit requires in total about 2000 nand gates on the P G A . Unfortunately the power stage was build as flying wire circuit without a well designed PCB. Because of that a lot of ground noise can be found on the measurement results at the switching times in the figures. Nevertheless the proper functionality of the control loop can be proven with this test circuit. The main clock frequency of the Bluetooth system is 1 3 M H t resulting in a pulse repetition rate f = = 203.125kHz with N = 64. The reference voltage was set to 3.3v. In fig. 9 the power stage is in CCM mode. It can be seen that the middle of the falling edge of the output voltage triangle is exactly at the reference voltage. Figure 10 is an example for DCM mode with low load current. In this example the output voltage triangle disappears in the (measurement) noise of the output voltage but the comparator output signal indicates the correct working of the control algorithm. The next measurement fig. (1 1) shows a load change (Ai =


Fig. 11. AI = 30mA lower current in DCM mode, higher current in CCM mode

Fig. 13. Output voltage with running Bluetooth connection

VI. CONCLUSION A digital control loop for DCDC boost converter has been presented. This novel method does not require an A/D converter. Nevertheless it delivers high quality control results sufficient for sensitive applications like Bluetooth headsets with 2.4GHz RF receiver and audio capabilities. The lack of analog parts reduces the noise sensitivity and the risk for subharmonic oscillations because of ground noise. The digital - 2000 nand gates only - implementation does not require rate action because of production variances and allows easily the use of non-linear extensions for better large signal behavior (here implemented as pulse width boost). ACKNOWLEDGMENT
Fig. 12. Line transient response, V d , changed from 1.2Vto 1.7V

The author would like to thank Mazda Sabony and Frank Gorris for doing the digital design and P G A implementation.

30mA) requiring a mode change from DCM to CCM and He would also like to thank Dirk Strotmann for the help and back to DCM. (There is a long-term drift seen in the fig. (11) support during the lab and measurement work. because the scope was used AC coupled). REFERENCES
The line transient response to an input voltage change from

1.2V to 1.7V is shown in fig. 12. From the output signal reaction the good stability properties of the control loop can
be seen. Finally the output voltage for a running Bluetooth connection under worst case condition is shown in fig. 13. The heavy load changes because of switching from idle to transmit active (Ai= 70mA) can be seen as the low frequency output voltage swing.

[l] R.W. Erickson Furuiamenrals o f Power Elecrronics, New York Chapman and Hall, 1997. [2] E. van Dijk, et al. PWM-Swich Modeling of DC-DC Conveners, IEEE Transactions on Power Electronics, Vol. 10, No. 6, pp. 659-665, November 1995. [3] Christian Kranz Fully digiral clocked voltage transformer, Intemational Patent W0200209263, July 2000.