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MOS Capacitor Structure

First electrode- Gate:


Consists oI low-resistivity
material such as
polycrystalline silicon
Second electrode- Substrate
or Body: n- or p-type
semiconductor
Dielectric- Silicon dioxide:
stable high-quality
electrical insulator between
gate and substrate.
Substrate Conditions Ior DiIIerent Biases
Accumulation
J
G
J
TN
05l0tion
J
G
J
TN
nv078ion
J
G
~J
TN
ow-Irequency C-V Characteristics Ior MOS
Capacitor on P-type Substrate
MOS capacitance is non-
linear Iunction oI voltage.
Total capacitance in any
region dictated by the
separation between capacitor
plates.
Total capacitance modeled as
series combination oI Iixed
oxide capacitance and
voltage-dependent depletion
layer capacitance.
MOS Transistor: Structure
4 device terminals:
Gate(G), Drain(D),
Source(S) and Body(B).
Source and drain
regions Iorm pn
junctions with substrate.
v
SB
, v
DS
and v
GS
always
positive during normal
operation.
MOS Transistor: Qualitative I-V
Behavior
J
GS
J
TN
: Only small leakage
current Ilows.
J
GS
J
TN
: Depletion region Iormed
under gate merges with source and
drain depletion regions. o current
Ilows between source and drain.
J
GS
~J
TN
: Channel Iormed between
source and drain. II v
DS
~0,
signiIicant i
D
Ilows Irom drain to
source.
i
B
0 and i
G
0.
MOS Transistor: Triode Region
Characteristics
where,
n

n
W/L

n
n
n
C
ox
(A/V
2
)
C
ox
c
ox
/T
ox
c
ox
oxide permittivity
(F/cm)
T
ox
oxide thickness (cm)
Ior
0 > >
DS
v
TN
J
GS
v
i
D

n
(v
GS
J
TN
v
DS
/2)v
DS
i(x) -i
D
(a constant) Ior all x
MOS Transistor: Triode Region
Characteristics (contd.)
Output characteristics
appear to be linear.
FET behaves like a
gate-source voltage-
controlled resistor
between source and
drain with

=
TN
J
GS
J
L
W
n

on
R

MOS Transistor: Saturation Region


II v
DS
increases above triode region limit,
channel region disappears, also said to be
pinched-oII.
Current saturates at constant value,
independent oI v
DS.
Saturation region operation normally used
Ior analog ampliIication.
MOS Transistor: Saturation Region
(contd.)
Ior
TN
J
GS
v
DS
v >
TN
J
GS
v
DSAT
v =
is also called saturation or pinch-oII
voltage
i
D

n
/2 (v
GS
J
TN
)
2
Transconductance oI a MOS Device
Transconductance relates the change in drain current to a
change in gate-source voltage
Taking derivative oI the expression Ior the drain current in
th0 8atu7ation region,
pt Q
GS
dv
D
di
m
g

=
TN
J
GS
J
D
I
TN
J
GS
J
L
W
n

m
g

= =
2
) (
Channel-ength Modulation
As v
DS
increases above v
DSAT
, length oI
depleted channel beyond pinch-oII
point, , increases and eIIective
decreases.
i
D
increases slightly with v
DS
instead oI
being constant (as predicted by basic
saturation model presented previously).
= channel length modulation
parameter
i
D

n
/2 (v
GS
J
TN
)
2
( v
DS
)
Depletion-Mode MOSFETS
MOS transistors with
Ion implantation process used to Iorm a built-in n-type
channel in device to connect source and drain by a resistive
channel
on-zero drain current Ior v
GS
0, negative v
GS
required to
turn device oII.
0 A
TN
J
TransIer Characteristics oI MOSFETS
Plots drain current versus gate-source voltage Ior a Iixed
drain-source voltage
Body EIIect or Substrate Sensitivity
on-zero v
SB
changes threshold
voltage, causing substrate
sensitivity modeled by
where
J
TO
zero substrate bias Ior J
TN
(V)
= body-eIIect parameter )
21
F
surIace potential parameter (V)

+ + =
SB
v
TO
J
TN
J 2 2
V
Enhancement-Mode PMOS Transistors:
Structure
!-type source and drain regions
in n-type substrate.
v
GS
0 required to create p-type
inversion layer in channel
region
For current Ilow, v
GS
v
T!
To maintain reverse bias on
source-substrate and drain-
substrate junctions, v
SB
0 and
v
DB
0
Positive bulk-source potential
causes J
T!
to become more
negative
Enhancement-Mode PMOS Transistors:
Output Characteristics
For , transistor is
oII.
For more negative v
GS
, drain
current increases in
magnitude.
PMOS is in triode region Ior
small values oI J
DS
and in
saturation Ior larger values.
T!
J
GS
J >
MOSFET Circuit Symbols
(g) and(i) are the
most commonly
used symbols in
VSI logic design.
MOS devices are
symmetric.
In MOS, n

region at higher
voltage is the drain.
In PMOS p

region
at lower voltage is
the drain
Process-deIining Factors
inimum F0atu70 Siz0, F : Width oI smallest line or space that
can be reliably transIerred to waIer surIace using given generation
oI lithographic manuIacturing tools
Alignm0nt Tol07anc0 T: Maximum misalignment that can occur
between two mask levels during Iabrication
Mask Sequence Ior a Polysilicon-Gate
Transistor
Mask : DeIines active area or thin
oxide region oI transistor
Mask 2: DeIines polysilicon gate
oI transistor, aligns to mask
Mask 3: Delineates the contact
window, aligns to mask 2.
Mask 4: Delineates the metal
pattern, aligns to mask 3.
Channel region oI transistor
Iormed by intersection oI Iirst two
mask layers. Source and Drain
regions Iormed wherever mask is
not covered by mask 2
Basic Ground Rules Ior ayout
F2A
TF/2
could be , 0.5,
0.25 m, etc.
Internal Capacitances in Electronic
Devices
imit high-Irequency perIormance oI the electronic device
they are associated with.
imit switching speed oI circuits in logic applications
imit Irequency at which useIul ampliIication can be
obtained in ampliIiers.
MOSFET capacitances depend on operation region and are
non-linear Iunctions oI voltages at device terminals.
MOS Transistor Capacitances: Triode
Region
C
ox
` Gate-channel
capacitance per unit
area(F/m
2
).
C
GC
Total gate channel
capacitance.
C
GS
Gate-source
capacitance.
C
GD
Gate-drain
capacitance.
C
GSO
and C
GDO
overlap
capacitances (F/m).
W
GSO
C
WL
ox
C W
GSO
C
GC
C
GS
C + = + =
2
"
2
C
GD
C
GC
/2 C
GDO
W C
ox
`WL/2 C
GDO
W
MOS Transistor Capacitances: Triode
Region (contd.)
C
SB
Source-bulk capacitance.
C
DB
Drain-bulk capacitance.
A
S
and A
D
Junction bottom area
capacitance oI the source and
drain regions.
!
S
and !
D
Perimeter oI the
source and drain junction
regions.
S
!
SW
C
S
A

C
SB
C + =
D
!
SW
C
D
A

C
DB
C + =
MOS Transistor Capacitances:
Saturation Region
Drain no longer connected to channel
W
GSO
C
GC
C
GS
C + =
3
2
W
GDO
C
GD
C =
MOS Transistor Capacitances: CutoII
Region
Conducting channel
region completely
gone.
C
GB
Gate-bulk
capacitance
C
GBO
gate-bulk
capacitance per unit
width.
W
GDO
C
GD
C =
W
GSO
C
GS
C =
W
GBO
C
GB
C =
SPICE Model Ior MOS Transistor
Typical deIault values used by SPICE:

n
or
p
20 A/V
2
0
2 0
J
TO
V

n
or
p
600 cm
2
/V.s
21

0.6 V
C
GDO
C
GSO
C
GBO
C
SW
0
T
ox
00 nm
Bias Analysis Approach
Assume an operation region (generally the saturation
region)
Use circuit analysis to Iind J
GS
Use J
GS
to calculate I
D
, and I
D
to Iind J
DS
Check validity oI operation region assumptions
Change assumptions and analyze again iI required.
OTE: An enhancement-mode device with J
DS
J
GS
is
always in saturation
Four-Resistor and Two-Resistor Biasing
Provide excellent bias Ior transistors in discrete circuits.
Stabilize bias point with respect to device parameter and
temperature variations using negative Ieedback.
Use single voltage source to supply both gate-bias voltage
and drain current.
Generally used to bias transistors in saturation region.
Two-resistor biasing uses lesser components that Iour-
resistor biasing and also isolates drain and gate terminals
Bias Analysis: Example (Four-Resistor
Biasing)
!7obl0m: Find Q-pt (I
D
, J
DS
)
A557oach: Assume operation
region, Iind Q-point, check to see iI
result is consistent with operation
region
A88um5tion: Transistor is saturated,
I
G
I
B
0
Analy8i8: First, simpliIy circuit, split
J
DD
into two equal-valued sources and
apply Thevenin transIormation to Iind
J
EQ
and R
EQ
Ior gate-bias voltage
Bias Analysis: Example (Four-Resistor
Biasing) (contd.)
S
R
D
I
GS
J
EQ
J + =
Since I
G
0,
2
2

+ =
TN
J
GS
J
S
R
n

GS
J
EQ
J
2

2
4
0 9 . 3
6
0 25
4

-
+ =
GS
J
GS
J
0 2 . 7 05 . 0
2
= +
GS
J
GS
J
V 66 . 2 , V 7 . 2 + =
GS
J
Since J
GS
J
TN
Ior J
GS
-2.71 J
and MOSFET will be cut-oII,
V 66 . 2 + =
GS
J
and I
D
34.4 A
Also,
DS
J
S
R
D
R
D
I
DD
J + + = ) (
V 08 . 6 =
DS
J
J
DS
~J
GS
-J
TN
. Hence
saturation region assumption is
correct.
"5t: (34.4 A 6.08 V) with
J
CS
2.66 V
Bias Analysis: Example 2 (Four-Resistor
Biasing)
Estimate value oI I
D
and use it
to Iind J
GS
and J
SB
Use J
SB
to calculate J
TN
Find I
D
using above 2 steps
II I
D
is not same as original I
D
estimate, start again.
Analy8i8 with body 0110ct u8ing
8am0 a88um5tion8 a8 in 0am5l0 1:
D
I
S
R
D
I
EQ
J
GS
J 000 , 22 6 = =
D
I
S
R
D
I
SB
J 000 , 22 = =
) 2 2 (
SB
J
TO
J
TN
J + + =
) 6 . 0 6 . 0 ( 5 . 0 + + =
SB
J
TN
J
2
2
6
0 25

-
=
TN
J
GS
J
D
I
Iterative solution can be Iound by
Iollowing steps:
Bias Analysis: Example 2 (Four-Resistor
Biasing) (contd.)
The iteration sequence leads to I
D
88.0 A
V 48 . 6 000 , 40 0 ) ( = = + =
D
I
S
R
D
R
D
I
DD
J
DS
J
J
DS
~J
GS
-J
TN
. Hence saturation region assumption is correct.
"5t: (88.0 A 6.48 V)
Bias Analysis: Example 3 (Two-Resistor
Biasing)
A88um5tion: I
G
I
B
0, transistor is
saturated (since J
DS
J
GS
)
Analy8i8:
D
R
D
I
DD
J
DS
J =
2
2

=
TN
J
GS
J
D
R
n

DD
J
GS
J
2

2
4
0
4
0 6 . 2
3 . 3

-
=
GS
J
GS
J
V 00 . 2 , V 769 . 0 + =
GS
J
Since J
GS
J
TN
Ior J
GS
-0.769 V
and MOSFET will be cut-oII,
V 00 . 2 + =
GS
J
and I
D
30 A
J
DS
~J
GS
-J
TN
. Hence saturation
region assumption is correct.
"5t: (130 A 2.00 V)
Bias Analysis: Example 4 ( Biasing in
Triode Region)
A88um5tion: I
G
I
B
0, transistor
is saturated (since J
DS
J
GS
)
Analy8i8: J
GS
J
DD
4 V
mA 3 .
2
) 4 (
2
V
A
2
250
= =
D
I
DS
J
S
R
D
R
D
I
DD
J + + = ) (
Also
V 9 . 2 =
DS
J
But J
DS
J
GS
-J
TN
. Hence, saturation
region assumption is incorrect
Using triode region equation,
DS
J
D
I + = 600 4
V 3 . 2 =
DS
J and I
D
.06 mA
J
DS
J
GS
-J
TN
, transistor is in triode region
"5t:(1.06 mA 2.3 V)
Bias Analysis: Example 5 (Two-Resistor
biasing Ior PMOS Transistor)
A88um5tion: I
G
I
B
0, transistor
is saturated (since J
DS
J
GS
)
Analy8i8:
0 ) kO 470 ( = + +
DS
J
G
I
GS
J
Also
0 ) kO 220 ( V 5 = +
DS
J
D
I
0
2
2
2
V
A
2
50
) kO 220 ( V 5 = + +

GS
J
GS
J
V 45 . 3 , V 369 . 0 =
GS
J
Since J
GS
-0.369 V is less than J
T!
-2
V, J
GS
-3.45 V
I
D
52.5 A and J
GS
-3.45 V
Hence saturation assumption is correct.
"5t: (52.5 A 3.45 V)
T!
J
GS
J
DS
J >
MOS Transistor Scaling
Drain current:
Gate Capacitance:
where: is the circuit delay in a logic circuit.
n

L
W
ox
T
ox
n
L
W
ox
T
ox
n n
-
1
-
-
-
-
1
= = =
/
/
/
*
- -
- - -
-
-
-
1

D
i
DS
v
DS
v
TN
v
GS
v
L
W
ox
T
ox
n
D
i = = =

2
/
/
/
*
-
-
-
-
1
GC
C
L
W
ox
T
ox
L W
ox
C
GC
C = = =
/
/
/
* * *
) " (
*
-
:
-
-
-
: =

=
/
/
*
*
* *
D
i
J
GC
C
D
i
J
GC
C
MOS Transistor Scaling (contd.)
Circuit and Power Densities:
Power-Delay Product:
CutoII Frequency:
1
T
improves with square oI channel length reduction
2
*
*
*
-
- -
!
D
i
DD
J
D
i
DD
J ! = = =
A
!
L W
!
L W
!
L W
!
A
!
= = = =
) / )( / (
2
/
* *
*
*
*
- -
-
3 2
* * *
-
-
:
-
:
!D!
!
! !D! = = =

= =
TN
J
GS
J
L
n
GC
C
m
g
T
1
2 2


x x
MOS Transistor Scaling (contd.)
High Field imitations:
High electric Iields arise iI technology is scaled down
with supply voltage constant.
Cause reduction in mobility oI MOS transistor,
breakdown oI linear relationship between mobility and
electric Iield and carrier velocity saturation.
Ultimately results in reduced long-term reliability and
breakdown oI gate oxide or pn junction.
MOS Transistor Scaling (contd.)
Sub-threshold Conduction:
I
D
decreases exponentially Ior
J
GS
J
TN.
Reciprocal oI the slope in
mV/decade gives the turn oII
rate Ior the MOSFET.
J
TN
should be reduced iI
dimensions are scaled down,
but curve in sub-threshold
region shiIts horizontally
instead oI scaling with J
TN..
MOSFET as Current Source
Ideal current source
gives Iixed output
current regardless oI
voltage across it.
MOSFET behaves as
as an ideal current
source iI biased in the
saturation region
(output current
independent oI J
DS
).
MOS Current Mirror
A88um5tion:
1
and
2
have identical J
TN
,
n
, 2
and W/L and are in
saturation.

+ =
DS1
J
TN
J
GS1
J
L
W
n

RE
I 2
2
2

+ =
DS2
J
TN
J
GS2
J
L
W
n

O
I 2
2
2
But J
GS2
J
GS1
)
)
RE
I
DS1
J
DS2
J
RE
I
O
I =
+
+
=
2
2

Thus, output current mirrors reIerence


current iI J
DS1
J
DS2
.
MOS Current Mirror: Example
iv0n data: I
RE
50 A, J
O
2 V, J
TN
V,
n
50 A/V
2
, 2
0.033 V
-
0t07min0: J
GS1
, J
DS1
, I
O
Analy8i8: J
DS1
J
GS1
J
TN
b2I
RE
/
n
(J
DS1
)|
Using numerical solution oI
)

V
033 . 0
(
2
V
A
50
) A 50 ( 2
V

DS
J
DS
J
+
+ =
J
DS1
.8 V. Since J
DS2
J
O
2 V:
A 6 . 56
V) 8 . (
V
033 . 0

V) 2 (
V
033 . 0

) A 50 ( =
+
+
=

O
I
I
O
is very close to I
RE
even
though J
DS1
and J
DS2
are
very diIIerent.
MOS Current Mirror Ratio
2

L
W
n

n
= =

0
2

2
n

L
W
n

n
= =

)
)
)
)
)
)
DS1
J
DS2
J
RE
I
DS1
J
DS2
J
L W
L W
RE
I
O
I
2
2
2
2
+
+
=
+
+
=

/
2
/
RE
I
O
I 5 =
Thus, ratio between I
O
and I
RE
can
be modiIied by changing W/ ratios
oI the current mirror transistors
(ignoring diIIerences due to J
DS
mismatch)
MOS Current Mirror Output Resistance
Output current changes with v
DS
due to channel length
modulation (this is undesirable, but unavoidable).
Output resistance is given by
In the current mirror, v
O
v
DS2

pt Q
O
v
O
i
O
R

+ =
O
v
TN
J
GS2
v
L
W
n

O
i 2
2
2
!
O
I
O
I
O
J
O
J
O
I
O
R
2 2
2
2
2

=
+
=

+
=

Current Mirror ayout


Two possible layouts oI a current mirror
More compact uses same
Source region Ior two transistors
Design oI Multiple Current Mirrors:
Example
)
)
A 50

/
2
/
2
= =
L W
L W
RE
I
D
I
)
)
A 25

/
3
/
3
= =
L W
L W
RE
I
D
I
)
)
A 25
4
/
5
/
5
= =
L W
L W
RE
I
D
I
Choose R to set I
RE
25 A
RE
I
GSN
J
GS!
J
R
+
=
0
We can simulate resistance R
using another transistors.
Design oI Multiple Current Mirrors
(continued)
kO 274
A
V
25
45 . 7 . 0
=
+
= R
V 7 .
2
= =
p

D
I
T!
J
GS!
J
V 45 .
2
= + =
n

D
I
TN
J
GSN
J
and
R can be replaced by transistor

Ior better integration.


We know that J
GS
-.84 V and I
D
25 A and

is
in saturation
2
2

=
T!
J
GS
J
L
W p

D
I
6 . 3

L
W
AmpliIier Using Four Resistor Bias
II v
in
J
in
is constant, capacitor
charges to J
in
J
G
, where
J
G
is the DC gate bias (the capacitor
is a DC open, so it is as iI it
was not there).
II v
in
is a high Irequency signal with
no DC component, the capacitor
Has no time to charge or discharge.
The two capacitor terminals Iollow
Each other and the gate voltage
Becomes v
G
J
G
v
in
.
When v
G
rises, i
D
rises since
(v
GS
J
TN
) rises. This causes
J
out
to Iall, since i
D
R
D
rises.
MOS ogic (Inverter)
J
in
0V causes MOS transistor to be
on (in triode). ow eIIective resistance oI
transistor causes voltage divider with J
out
near 0V.
J
in
0V causes MOS transistor to be
oII (cutoII). High eIIective resistance oI
transistor causes voltage divider with J
out
near 0V.
Jin Jout
0 (0V) (0V)
(0V) 0 (0V)
MOS ogic (AD)
J
1
J
2
0V causes both MOS transistors
to be on (in triode). ow eIIective resistance
oI transistors causes voltage divider with J
out
near 0V.
J
1
0V or J
2
0V (or both) cause one or
both MOS transistors to be oII (cutoII).
High eIIective resistance oI series
transistors cause voltage divider with J
out
near 0V.
J
1
J
2
J
out
0 0
0
0
0
MOS ogic (General)
Any combination oI inputs J
1
J
2
. J
n
that should result in an output oI 0
should produce a low-resistance path Irom
J
out
to ground in the pull-down network.
Any combination oI inputs that does not
pull the output J
out
to ground through
the network will result in the output pulled
high through the pull-up resistor R
D
.
MOS logic draws current continuously when J
out
is low.
PMOS ogic (Inverter)
J
in
0V causes PMOS transistor to be
on (triode, J
GS
-0V). ow eIIective
resistance oI transistor causes voltage
divider with J
out
near 0V.
J
in
0V causes PMOS transistor to be
oII (cutoII). High eIIective resistance oI
transistor causes voltage divider with J
out
near 0V.
Jin Jout
0 (0V) (0V)
(0V) 0 (0V)
PMOS ogic (AD)
J
1
J
2
0V causes both PMOS transistors
to be oII (cutoII). High eIIective resistance
oI transistors causes voltage divider with J
out
near 0V.
J
1
0V or J
2
0V (or both) cause one or
both PMOS transistors to be on (triode).
ow eIIective resistance oI parallel
transistors cause voltage divider with J
out
near 0V.
J
1
J
2
J
out
0 0
0
0
0
PMOS ogic (General)
Any combination oI inputs J
1
J
2
. J
n
that should result in an output oI
should produce a low-resistance path Irom
J
out
to J
DD
in the pull-up network.
Any combination oI inputs that does not
pull the output J
out
to J
DD
through
the network will result in the output pulled
low through the pull-down resistor R
D
.
PMOS logic draws current continuously when J
out
is high.
CMOS ogic (Inverter)
J
in
0V causes MOS transistor to be
oII (cutoII) and PMOS to be on (triode).
ow eIIective resistance oI PMOS and
high eIIective resistance oI MOS results
in voltage divider with J
out
near 0V.
J
in
0V causes PMOS transistor to be
oII (cutoII) and MOS transistor to be on
(triode). High eIIective resistance oI
PMOS and low eIIective resistance oI MOS
results in voltage divider with J
out
near 0V.
Jin Jout
0 (0V) (0V)
(0V) 0 (0V)
CMOS ogic (AD)
J
1
J
2
0V causes both MOS transistors
to be on and both PMOS transistors to be oII.
High eIIective resistance oI parallel PMOS
And low eIIective resistance oI series MOS
causes voltage divider with J
out
near 0V.
J
1
0V or J
2
0V (or both) cause one or
both MOS transistors to be oII and one or
both PMOS transistors to be on. ow eIIective
resistance oI parallel PMOS and high eIIective
resistance oI series MOS cause voltage
divider with J
out
near 0V.
J
1
J
2
J
out
0 0
0
0
0
CMOS ogic (General)
Any combination oI inputs J
1
J
2
. J
n
that should result in an output oI
should produce a low-resistance path Irom
J
out
to J
DD
in the pull-up network (otherwise,
PMOS network should be high-resistance).
CMOS logic draws little current when J
out
is a constant high or low
(it does draw current when the output switches).
Any combination oI inputs J
1
J
2
. J
n
that should result in an output oI 0
should produce a low-resistance path Irom
J
out
to GND in the pull-down network (otherwise,
MOS network should be low-resistance).
CMOS ogic (Complex Function)
Z AB C
A B C Z
0 0 0
0 0 0
0 0
0 0
0 0
0 0
0 0
0
Output 0 iI C
Output 0 iI A and B
Output iI C 0
and (A 0 or B 0)