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Q:-Define and classify types of simulation. Explain in detail static timing analysis.

ANS:Types Of Simulation ( simulation models):1) Behavioral Simulation 2) RTL Simulation 3) Static Timing Analysis 4) Gate Level Simulation(pre-layout) 5) Gate Level Simulation(post-layout) 1)Behavioral Simulation:-Design is initially described at behavioral Level to verify concept and basic functionality. Design can be specified in HDL or VHDL. Behavioral HDL description is different from conventional RTL code. Behavioral Synthesis is performed on the design to optimize the design at architectural level with constraints for clock, latency, throughput. Output of behavioral synthesis is an RTL level design with clocks, registers and buses. 2) RTL Simulation:-Most designs are described in an ASCII format using the synthesizable subset of VHDL and Verilog language.This synthesizable subset is referred as Register Transfer Level(RTL).RTL design is simulated to verify functionality. Once the RTL code has been simulated and analyzed, it is ready for logic synthesis. 3)Static Timing Analysis:-Once the gate level netlist has been generated the next step is verify timing of the design. Static Timing Analysis is a a technique used to verify the timing characteristics of a design.Static Timing Analysis does not require any test vectors. The inputs to static timing analysis include netlist,library models of the cells in the technology library and constraints like clock period,waveform,skews,false path,input and output delays.Using this information STA tool calculates the delay through the combinational logic,set up and hold up time and slack for each path. 4)Gate Level Simulation(pre-layout):-Gate level simulation is performed at module level and at chip level depending on the verification environment used for the design.Simulation is performed on the synthesized gate level design prior to placement and routing for two purposes. :-a)to ensure that the functionality before and after synthesis is identical.b) to dynamically verify the timing of the design with the cell delays from the target technology library and estimated wire delays for interconnects. 5)Gate Level Simulation(Post-layout):- Interconnect delays are extracted and back annotated on the design.After back annotation data is available, static timing analysis and gate level simulation is done to verify the design still meets timing.The design is simulated after layout to ensure that timing is met with accurate interconnect delays from layout.

STATIC TIMING ANALYSIS:As the gate level netlist has been generated,the next step is to check the timing of the design.Static timing analysis technique is used to check the timing characteristics of the design i.e.delay,set up and hold time,slack,skew etc.Static timing analysis does not check functionality of the design,it verify only timing characteristics without use of the test vectors.The entire design and the application of static timing analysis at different stages is as follows:1)STA is performed on the synthesized gate level netlist to perform all possible timing checks of the design.If time violations are detected during STA, resynthesis of the design is done. 2)Floor planning and placement are performed using floor planning tools and parasitics(net capacitances and interconnect delays) are estimated.Pre-layout STA is performed using these estimated parasitics. 3) Clock trees are not synthesized during logic synthesis tools.Clock tree synthesis is done during place and route to balance the clock skews.clock tree synthesis is done to achieve minimal clock skews.STA is performed on the design after inserting the clock tree to calculate actual skews based on back annotation information. 4)Parasitics are extracted after placement and routing to obtain accurate net capacitances and resistances.The interconnect pin tio pin delays are also obtained based on actual routing lengths and technology in the Standard Delay Format (SDF) file.This data is used to perform post layout static timing analysis. 5)A new netlist which includes the pre layout netlist with the addition of clock tree is generated.then STA is re-run on this netlist with actual propagation delay through clock tree buffers and actual net and cell delays based on extracted parasitics.Any set up and hold violations detected at this stage,is fixed in-place optimization. Logic Synthesis
Constraints (Clock, Input Drive, Output Load


Place & Route Static Timing Analysis (Estimated parasitics)

Parasitic Extraction

Static Timing Analysis (Extracted parasitics)

SDF (extracted parasitics)

Set up time:-the amount of time the synchronous input must be stable before the active edge the clock. Hold time:- the amount of time the synchronous input must be stable after the active edge Slack:-Time difference Between required time and arrival time. False path:-The path which is never travelled by the signal. Skew:-The skew time specifies the maximum allowable time delay between two signals,which if exceeded causes devices to behave unreliably.