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Introduction to Digital Electronics, Module 8: Flip Flops

LABORATORY EXPERIMENT 8 Designing a "D" Flip Flop from Conventional Gates OVERVIEW: A Flip Flop is a memory cell capable of having an output in a logical "1" state or a logical "0" state. The output state is initiated by input conditions, and then the state is held until new input conditions cause it to switch or the power to the devices is interrupted. Such a "memory" cell can be generated using two NAND gate with the output of one connected to the input of the other and visa versa, with the unused inputs as state controls. If the unused input on either NAND gate is pulled low or to a logical "0", the corresponding output goes high forcing the opposite NAND whose control input is high to a low state. This configuration of toggling NAND gates is called a "SET/RESET" Flip Flop. Two additional NAND gates can be added to turn the SET/RESET Flip Flop stage into an Enabled SET/RESET Flip Flop. The addition is significant because the device now can be turned on an off without losing the state history or changing the output. When the Set input is inverted and tied to the Reset input, the device becomes a gated "D" Flip Flop. Simply stated, what ever state is present on the "D" input is transferred to the output when the enable input is pulled high. The only problem is that if the "D" input changes anytime the enable input is high, the output follows the change. The device would be more useful if it saved what was on the "D" input at the instant the enable signal went high. This can be accomplished by adding the little pulse generator circuit shown below in figure 1 coming in from the clock switch. An AND gate has an inverter input and a direct input from the "Enable" or now the "Clock" input signal. If the inverter passed the signal instantly, this circuit would not work but the inverter has about a 10 ns delay. When a logical "0" is present on the input to the AND gate and the INVERTER at the same time, the AND gate has a "1" and a "0" on its inputs. At the instant that the "0" on the input to the INVERTER goes to a "1", the "0" on the input to the AND gate goes to a "1" also. This puts a "1" on both of the AND inputs for 10 ns while the "1" propagates through the INVERTER and goes to a "0". The net result is a 10 ns pulse output from the AND gate. If this circuit is connected to the ENABLE on our enabled "D" Flip Flop, the result is a "D" Flip Flop which is clock on the rising edge of an applied clock signal. The delay can be made longer by adding more inverters. There must however, be an odd number of inverters.

Introduction to Digital Electronics, Module 8: Flip Flops

If you have difficulty with the clock, disconnect that part of the circuit and tie it directly to the Pulse Generator on your Circuit Design Trainer. This circuit does almost exactly the same thing and will give you a strong pulse to trigger your "D" Flip Flop. One additional modification can be added to the circuit to give the user the ability to SET or RESET the "D" output. If the dual input AND gates in the enable stage are replaced with two three input NAND gates, the extra inputs become /SET and /RESET inputs. (/ means active low). This completes the design. To verify that this works, in this laboratory experiment, you will build the "D" Flip Flop using conventional gates. The circuit has been designed for you and is shown in figure 8.1 below. MATERIALS: 1. Qty. 1 - 74LS00 Quad Dual Input NAND gate 2. Qty. 1 - 74LS10 Tri Three Input NAND gate 3. Qty. 1 - 74LS04 Hex Inverter gate 4. Circuit Design Trainer with +5VDC Power Supply, Solderless Bread Board, Data Switches, Debounced Switch or Pulse Injecter Circuit, 555 clock, and Indicator LED's. PROCEDURE: 1. Find the above gates in your digital laboratory parts kit. 2. Build up the circuit shown in Figure 8.1 below. 3. Verify that the "Q" output of the "D" Flip Flop changes to be the same as the "D" input when a rising edge of the clock is input. This is accomplished by changing the "D" input Data Switch and then clocking the Flip Flop by toggling the Debounce Switch at the Clock input. The "Q" LED will change to agree with the "D" LED at the instant the Clock edge rises. 4. Connect a wire from the "/Q" output to the "D" input and connect the Clock to the Trainer 555 Clock and set the frequency to 10 Hz. Connect the 10 Hz signal to and LED and the "Q" to and LED. The "Q" LED should flash at 5 Hz or half of the 555 clock 10 Hz rate. With the "D" input tied to the "/Q" output, the "D" Flip Flop toggles or switches state at every Clock rising edge. This effectively divides the clock input frequency in half. 5. Write up your laboratory and include a "Master Map" of the "D" Flip Flop. This is just a state next state table that shows what happens to the outputs for every possible input and clock condition.

Introduction to Digital Electronics, Module 8: Flip Flops

FIGURE 1: THE GATE REALIZATION OF A "D" FLIP FLOP