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Code No: 09A60502

R09

Set No. 2

III B.Tech II Semester Examinations,April/May 2012 VLSI DESIGN Computer Science And Engineering Time: 3 hours Max Marks: 75 Answer any FIVE Questions All Questions carry equal marks

1. (a) Draw and explain the architecture of a 4 word by 6 bit pseudo nMOS NAND ROM. (b) Design and explain 4 stage serial in parallel out memory. [8+7]

2. (a) Explain the various factors that inuence the power dissipation in CMOS VLSI circuits. (b) Suggest design methodologies for power reduction. 3. Explain the following terms: (a) Yield (b) Reject rate (c) Failure (d) Error (e) Fault (f) Defect level. [7+8]

4. (a) Derive the expressions for rise time and fall time of CMOS inverter. Comment on the expressions derived. (b) State the problem that arise when comparatively large capacitive loads are driven by inverters. Explain how super buers can solve the problem. [8+7] 5. (a) Derive an expression for the transconductance of a MOS transistor. (b) Draw the pass transistor arrangement for the logic X=ABC. 6. (a) Explain the various types of IC packages. (b) Write notes on Rents rule. 7. Write notes on the following: (a) Chip tape out (b) Yield (c) Parasitic Extraction. 8. Design and explain a 6-bit Wallace tree multiplier. [5+5+5] [15] [10+5] [9+6]

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[15]

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Code No: 09A60502

R09

Set No. 4

III B.Tech II Semester Examinations,April/May 2012 VLSI DESIGN Computer Science And Engineering Time: 3 hours Max Marks: 75 Answer any FIVE Questions All Questions carry equal marks

1. (a) Write down the truth table for P channel MOS switch with gate and source as inputs. (b) Write a short note on photoresists. (c) What are the advantages of CMOS over BiCMOS Technology.

2. (a) Explain the various design strategies of testing a VLSI circuit. (b) Explain the challenges in VLSI testing.

3. (a) Design and explain last - in - rst - out queues.

(b) Design and explain a row and column decoder for NAND ROM array. [7+8] 4. (a) Explain CMOS static logic with an example.

(b) Explain the working of a Clocked CMOS, three input NAND gate. Discuss the merits and demerits of Clocked CMOS logic. [8+7]

5. (a) Explain the architecture of complex programmable logic devices. (b) Explain the macrocell architecture of a CPLD. [7+8]

6. (a) Design, implement and explain a comparator using XNOR. Use pseudo nMOS transistors.

(b) Design a 4-bit asynchronous up counter using transmission gates and explain its working. [8+7] 7. Using the measured data given below, determine the device parameters VT O , k, , (channel length modulation coecient) assuming 2 F = - 0.6 V. [15] VGS (V) 2 5 5 5 VDS (V) 5 5 5 8 VBS (V) ID (A) 0 10 0 400 -3 280 0 480

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[4+6+5]

[7+8]

8. Write notes on: (a) ASIC library (b) Test bench programs
(c) Back annotation

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Code No: 09A60502

R09

Set No. 4
[5x3=15]

(d) Architecture specications and design constraints of an IC. (e) Design rule check.

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Code No: 09A60502

R09

Set No. 1

III B.Tech II Semester Examinations,April/May 2012 VLSI DESIGN Computer Science And Engineering Time: 3 hours Max Marks: 75 Answer any FIVE Questions All Questions carry equal marks

1. Realise the function f= AB + C D using (a) CMOS static logic (b) Pseudo-nMOS logic. Use only NAND gates.

2. (a) Draw and explain the Read/Write operation of 4T SRAM cell. (b) Explain the divided word line architecture of RAM. 3. (a) Explain semicustom design approach of an IC.

(b) Compare full custom and semicustom designs of an IC.

4. (a) Explain the various kinds of integrated resistors and their characteristics. (b) Explain the working of a CMOS switch with appropriate characteristic curves. [8+7] 5. (a) Implement and explain the working of a ripple carry adder using transmission gates. (b) Design and explain the working of a Manchester Carry Chain adder. Give an expression for its propagation delay and discuss on it. [8+7] 6. (a) Explain the working of nMOS inverter with resistive load. Discuss the voltage transfer characteristics of the inverter for dierent values of the parameter Kn RL . (b) Derive the current equation for a p-channel MOS transistor operating in the linear region, i.e., for VSG + VT P > VSD . [8+7] 7. (a) Explain in detail static timing analysis of integrated circuits. (b) Explain the design integrity issues to be taken care in the design process. [8+7] 8. What is fault simulation? Explain briey fault models. Explain the various stuck at fault models with suitable examples. [15]

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[7+8]

[8+7]

[10+5]

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Code No: 09A60502

R09

Set No. 3

III B.Tech II Semester Examinations,April/May 2012 VLSI DESIGN Computer Science And Engineering Time: 3 hours Max Marks: 75 Answer any FIVE Questions All Questions carry equal marks

1. (a) What is a zero/one detector? Give two applications of it. (b) Design, implement and explain a tree based zero/one detector circuit. Implement using pass gates. [7+8] 2. (a) Compare FPGA and CPLD. (b) Explain the I/O control block of CPLD. 3. Explain the following: (a) Threshold voltage (b) Pinch o voltage (c) Channel length modulation (e) Figure of merit. (d) Subthreshold leakage current.

4. (a) Design and explain a counter using SRAM cells. (b) Design and explain tapped delay line using appropriate memory cells. [8+7] 5. (a) Explain the latch-up susceptibility of BiCMOS circuits. (b) Explain the fabrication of NMOS transistor. 6. (a) Dierentiate Switch logic and Gate logic. (b) Write notes on i. NOR CMOS logic. ii. Dierential cascade voltage switch logic. [7+8] [7+8]

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[5+10]

[5x3=15]

7. (a) Explain the terms controllability and observability with a suitable example. (b) Explain the various categories of manufacturing tests. [8+7]

8. (a) Description of a digital circuit at register transfer level is preferred compared to other levels. Why? (b) Write notes on the optimization targets for logic synthesis of a digital circuit. [7+8]

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