Vlsi Technology

Digital systems are highly complex at their most detailed level. They may consist of millions of elements i.e., transistors or logic gates. For many decades, logic schematics served as thengua franca of logic design, but not any more. Today, hardware complexity has grown to such a degree that a schematic with logic gates is almost useless as it shows only a web of connectivity and not functionality of design. Since the 1970s, computer engineers, electrical engineers and electronics engineers have moved toward Hardware description language (HDLs). Digital circuit has rapidly evolved over the last twenty five years .The earliest digital circuits were designed with vaccum tubes and transistors. Integrated circuits were then invented where logic gates were placed on a single chip. The first IC chip were small scale integration (SSI) chips where the gate count is small. When technology became sophisticated ,designers were able to place circuits with hundreds of gates on a chip. These chips were called MSI chips with advent of LSI, designers could put thousands of gates on a single chip. At this point, design process is getting complicated and designers felt the need to automate these processes. With the advent of VLSI technology, designers could design single chip with more than hundred thousand gates. Because of the complexity of these circuits computer aided techniques became critical for verification and for designing these digital circuits. One way to lead with increasing complexity of electronic systems and the increasing time to market is to design at high levels of abstraction. Traditional paper and pencil and capture and simulate methods have largely given way to the described unsynthesized approach.

For these reasons, hardware description languages have played an important role in describe and synthesis design methodology. They are used for specification, simulation and synthesis of an electronic system. This helps to reduce the complexity in designing and products are made to be available in market quickly. The components of a digital system can be classified as being specific to an application or as being standard circuits. Standard components are taken from a set that has been used in other systems. MSI components are standard circuits and their use results in a significant reduction in the total cost as compared to the cost of using SSI Circuits. In contrasts, specific components are particular to the system being implemented and are not commonly found among the standard components. The implementation of specific circuits with LSI chips can be done by means of IC that can be programmed to provide the required logic. EMERGENCE OF HARDWARE DESCRIPTION LANGUAGE As designs got larger and complex, logic simulation assumed an important role in design process. For a long time, programming languages such as fortran, pascal & c were been used to describe the computer programs that were been used to describe the computer programs that were sequential in nature. Similarly in digital design field, designers felt the need for a standard language to describe digital circuits. Thus HDL is came in to exitance. HDLs allowed the designers to model the concurrency of processes found in hardware elements. HDLs such as VERILOG HDL & VHDL( Very high speed integrated circuit hardware description language). became popular.

Dou bles

DESIGN FLOW
system specification

Functional design

Logic design

X=(ABCD+A+D+A(B+C)) Y=(A(B+C)+AC+D+A(BC+D))

Circuit design

Physical design

Fabrication

Packaging and testing

POPULARITY OF VERILOG HDL

Verilog hdl has evolved as a standard hardware descriptional language.Verilog offers many useful features for hadware design. Verilog is a general purpose hardware description language that is easy to learn and to use.It has thus become user friendly. Verilog allows different levels of abstraction to be mixed in the same model.Thus a designer can design a hardware model in terms of switches,gates,RTL or behavioural codes. Verilog is one language for simulation and design.Most popular logic synthesis tools support verilog HDL.This makes it the language of choice of designers .

TYPICAL DESIGN FLOW Typical design flow for designing VLSI circuits is shown in the tool flow diagram. This design flow is typically used by designers who use HDLs.In any design,specification are first.Specification describe the functionality,interface and overall architecture of the digital circuit to be designed.At this point,architects need not think about how they will implement their circuit. A behavioural description is then created to analyse the design in terms of functionality,performances and other high level issues. The behavioural description is manually converted to an RTL (Register Transfer Level) description in an HDL.The designer has to describe the data flow that will implement the desired digital circuit.From this point onward the design process is done with assistance of CAD tools.

Logic synthesis tools convert the RTL description to a gate level netlist.A gate level netlist is a description of the circuit in terms of gates and connections between them. The gate level netlist is input to an automatic place and route tool, which creates a layout. The layout is verified and then fabricated on a chip.Thus most digital design activity is concentrated on manually optimizing the RTL description of the circuit.After the RTL description is frozen,CAD tools are available to assist the designer in further proceeese.Designing at RTL level has shrunk design cycle times from years to a few months. TYPICAL DESIGN FLOW OF VLSI

DESIGN SPECIFICATION

BEHAVIORAL DESCRIPTION RTL DESCRIPTION (HDL)

FUNCTIONAL VERIFICATION AND TESTING LOGIC SYNTHESIS

GATE LEVEL NETLIST

LOGICAL VERIFICATION AND TESTING

FLOOR PLANNING AUTOMATIC PLACE&ROUTE

PHYSICAL LAYOUT

LAYOUT VERIFICATION

IMPLEMENTATION

OVERVIEW OF DIGITAL DESIGN WITH VERILOG HDL 1.HELLO VERILOG HDL: From a modest beginning of early 1985 at GATEWAY DESIGN SYSTEM CORPORATION,now a part of CADENCE DESIGN SYSTEMS,the verilog hardware descriptional language has become an industry standard in digital circuit designing.Verilog came in to being as a language that was the first to support mixed levels of design representations Comprising switches,gates,register transfer level and higher levels of abstractions. We have three types of levels 1.GATE LEVEL it might describe the logical gates and flip flops in a digital systems. 2.SWITCH LEVEL an HDL might describe the layout of the wires,resistors & transistors on INTEGRATED CIRCUIT (IC) chip. 3.REGISTER TRANSFER LEVEL is an even higher level describes the registers and transfers of vectors of information between registers.

2.

MODELLING LEVELS IN VERILOG: Verilog is both structural and behavioural intervals of each module can be divided in to four levels depending on the needs of the design. MODELLING TECHNIQUES

BEHAVIOURAL MODELLING . DATA FLOW MODELLING GATE LEVEL MODELLING SWITCH LEVEL MODELLING BEHAVIOURAL MODELLING: This is the highest level of abstraction provided by verilog.A module can be implemented interms of the desired design algorithm without concern for hardware implementation details.We cover assignments for all kinds,control constructs,time and event controls, tasks and functions. DATA FLOW MODELLING: At this module is designed specifying the data flow.Designers should be aware of how data flows between hardware registers and how data is processed in the designs.Data flow description of a circuit is more concise than a gate level description. GATE LEVEL MODELLING:

The module is implemented interms of logic gates and interconnections between the gates.Design at this level is similar to describing a design interms of a gate level logic diagram. SWITCH LEVEL: This is the lowest level of abstraction provided by verilog.A module can be implemented interms of switches,storage node and the interconnections between them.Verilog allows the designers to mix and match all four levels of abstraction in a design.In a digital design community,the term RTL is frequently used for a verilog description that uses a combination of two behavioural and data flow constructs and is acceptable to logic synthesis tools.If a design contains four modules,verilog allows each of the modules to be written at a different level of abstraction,the more flexible and technology dependent and inflexible.A small modification can cause a significant number of changes in the design. Before we discuss the details of verilog language,we must first understand basic hierarchial modeling concepts in digital design.The designer must use a good design methodology to do efficient Verilog HDL based design. Now we discuss the typical design methodological and illustrate how these concepts are translated to verilog. 3. DESIGN METHODOLGY: There are two basic types of digital design methodologies. 1.Top down methodology 2.Bottom up methodology In Top down design method ,we define the top level block and identify the sub blocks necessary to build the top level block. We further subdivide the cells that cannot be further divided.The top down methodology is shown . In Bottom up methodology,we first identify the building blocks that are available to us.We build bigger cells using these building blocks.These cells are then used for higher level blocks until we

build the top level block in the design.The bottom up design methodology is shown. Consider an example of designing a ripple carry counter.In top down design method,we first have to specify the functionality of the ripple carry counter which is the top level block.Then we implement the counter with T flipflop.We build the T flipflop from the D flipflop. We build the T flipflop from the D flipflop and additional inverter gates. Thus we break bigger blocks in to smaller sub blocks until we decide that we cannot break up the blocks any further.A bottom up method flows in the opposite direction.We combine small building blocks and build bigger blocks. TOP DOWN DESIGN MACRO CELLS LEAF CELL LEAF CELL MACRO CELLS LEAF CELL LEAF CELL

BOTTOM UP DESIGN MACRO CELLS LEAF CELL USE OF VERIWELL: Veriwell is a comprehensive implementaion of verilog HDL originally developed by WELLSPRING SOLUTIONS ,Inc. Veriwell supports the verilog language as specified by the OVI language preference manual veriwell was first introduced in December 1992 and was written to be compatible with both the OVI standard with cadence verilog-xl. USE OF VERILOG HDL: The verilog language provides the digital designer with a means of describing a digital system a wide range of levels LEAF CELL MACRO CELLS LEAF CELL LEAF CELL

of abstraction and at the same time,provides access to computer aided design tools to aid in the design process at these levels. Verilog allows hardware designers to express their design with behavioural constructs deterring the details of implementation to a later stage of design in the design .An abstact representation helps the designer explore architectural alternatives through simulations and to detect using bottle necks before detailed design begins. Though the behavioural level of verilog is a high level description of a digital system,it is still a precise notation.Computeraided-design tools I,e., programs,exist which will compile programs in the verilog notation to the level of circuits consisting of logic gates and flipflops.One could then go to the lab and wire up the logical circuits and have a functioning system.And other tools can compile programs in verilog notation to a description of the integrated circuit masks for very scale integration circuit (VLSI). Therefore,with the proper automated tools,one can create a VLSI description of a design in verilog and send the VLSI description via electronic mail to asilicon foundry in california and receive the integrated chip in a few weeks by way of snail mail.Verilog also allows the designer to specific designs at the logical gate level using gate constructs and the transistor level using switch constructs. Our goal in the course is not ot create VLSI chips but to use verilog to precisely describe the functionality of any digital system.For example,a computer .However,a VLSI chip designed by way of verilogs behavioural constructs will be rather slow and be wastefull of chiparea.The lower levels in verilog allow engineers to optimize the logical circuits and VLSI layouts to maximize speed and minimize area bof the VLSI Chip. TRENDS IN HDL: The speed and complexity of digital circuits has increased rapidly.Designers have responded by designing at higher level of abstraction. The most popular trend currently is to design in HDL at an RTL level,because logic synthesis tools can create gate-level netlists from RTL level designs.Behavioural synthesis has recently emerged.As these tools improve,designers will be able to design directly interms of algorithms and the behaviour of the circuit and then use CAD tools to do translation and optimization in each phase of the design. Behaviour modeling will be used more and more as behavioural synthesis matures.Until then,RTL design will remain very popular.

A trend that is emerging for system level design is a mixed bottom-up methodology where the designers use either existing verilog HDL modules,basic buildings, or vendor-supplied core blocks to quickly bring up their system simulation.This is to done to reduce development costs and compress design schedules.For example ,consider a system that has a cpu.graphics chip,i/o chip and a system bus.The cpu designers would build the next generation cpu themselves at an RTL level.But they would use behavioural models for the graphics chip and the i/o chip and would buy a vendor-supplied model for the system bus.Thus,the system-level simulation For the cpu could be up and running very quickly and along before the RTL description for the graphics chip and the i/o chip are completed.

CONSTRUCTS & CONVENTIONS IN VERILOG We are now to discuss the constructs and conventions in verilog.These conventions provide the necessary framework for verilog hdl .The basic lexical conventions used by verilog hdl are very similar to the C language. Verilog is a case sensitive language.All keywords are written in the lowercase. BASIC CONCEPTS: Comments Comments can be inserted in the code for readability and documentation.There are two ways to write comments.A one line line comment starts with //.Verilog skips from that point to the end of that line.A multiple line comment starts with /* and ends with */. Example // This is a one line comment. // *This is a mutiple line comment*/ Operators

Operators are of three types:(1) (2) (3) Unary Binary Ternary

Unary operators precede the operand. Example A=~b;//~is a unary operator. Binary operators appear between two operands. Example A=b&&c;// is a binary operator. Ternary operators are two separate operators that separate two operands. Example A=b?c:d;//?: is a ternary operator. Number specification There are two types of number specification in verilog they are Sized Unsized

Sized numbers are represented as <size><base format><number> <size> is written only in decimal and specifies the number of bits in the number.Legal base formats are decimal (d), hexadecimal (h), binary(b) and octal (o).

Example 4b1001 - This is a 4 bit binary number. 12habc - This is a 12 bit hexadecimal number. 16d255 - This is a 16 bit decimal number. Unsized numbers are numbers that are specified a base format specification and are decimal numbers by default.Numbers that are written without a size specification have a default number of bits that is machine specific. X or Z Values Verilog has two symbols for unknown and high impedence values.There values are very important for modeling real circuits.An unknown value is denoted by x.A high impedence value is denoted by z. Example 1bx - This is one bit unknown number. 8hz - This is a eight bit high impedence number. IDENTIFIERS AND KEYWORDS Keywords are identifiers reserved to define the language constructs.Keywords are written in lower case. Identifiers are made up of alpha numeric characters, the underscore(_) and the dollar sign ($) and are case sensitive .Identifier start with an alphabet or an underscore and cannot start with a number or $.

Example

Reg a;//reg is a keyword, a is an identifier. Input clk;/*input is a keyword,clk is an identifier.*/ DATA TYPES IN VERILOG Verilog supports four values and eight strengths to model the functionality of real hardware.There 4 levels are: 0 1 X Z Logic zero Logic one Unknown value High False condition True condition -

In addition to logic values,strengths levels are often used to resolve conflicts between drivers of different strength in digital circuits.Value levels 0 or 1 can have strength levels as listed below:supply strong pull large weak medium small high impedence. NETS Nets represent connection between hardware elements.Just as in real circuits,nets have continuously driven on them by the outputs of the devices that they are connected to. Example Wire a;

In the above figure,net a is connected to the output of AND gate.Nets are primarily declared with keyword wire.Nets are one bit value by default unless they are declared explicitly as vectors. REGISTER

Registers represent data storage elements.Registers retain value until another value is placed on to them. Register data types declared by keywords reg. Example Reg a,b; VECTORS Nets are register data types can be declared as vectors .Vectors have multiple bit widths. Example Wire[7:0]a,b; Reg[3:0]a,b; INTEGERS It is a general data types used for manipulating quantities.Integers are declared by the keyword integer. Example: integer counter; /* general purpose variable used as counter */ initial counter = 1;// one is stored in counter.

REALS Real number constants and real data types are declared with keyword real.When a real value is assigned to an integer the real number is rounded off to the nearest integer. Example Real a; initial a=4.23 TIME

Verilog simulation is done with respect to simulation time.A special time register data types is used in verilog to store simulation.The keyword is time.The system function $time is invoked to get the current simulation time. Example Time t; //define a time variable t. Initial T=$time; // save the current simulation time. PARAMETER Verilog allows constants to be defined in the module by the keyword parameter.Parameters cannot be used as variables. Example Parameter a=5; //defines a constant SYSTEM TASKS Verilog provides standard system tasks to do certain routine operations.All system tasks appear in the form $<keyword>.Operations such as displaying on the screen, monitoring values of nets,stopping and finishing are done by system tasks.

Displaying information $display is a main system task for displaying values of variables or strings or expressions. Example $display(p1,p2,.pn);

where p1,p2,..pn are variables or expressions. Monitoring information Verilog provides a mechanism to monitor a signal when its value changes.This facility is provided by $monitor task. Example $monitor(p1,p2,..pn); where p1,p2,pn can be variables or quoted strings. $monitor continuously monitors the values of the variables or signals specified in the parameter list and displays all parameters in the list whenever the value of any one variable or signal changes Hence $monitor needs to be invoked only once. Stopping and finishing in a simulation 1. The task $stop is provided to stop during a simulation. Example $stop The $stop tasks puts the simulation in an interactive mode.The designer can then debug a design from interactive mode. The $stop task is used whenever the designer wants to suspend a simulation and examine the values of simulation in the design. 2.The task $finish terminates the simulation. Example $finish; COMPILER DIRECTIVES

Compiler directives are provided in verilog.All compiler directives are defined by using the <keyword> constuct.We deal with the two most useful compiler directives. 1. define 2. include The define is used to define text macros in verilog .The verilog compiler substitutes the text of the macro where ever it encounters a<macro_name>. The include directive allows you to include entire contents of a verilog source file in another verilog file during compilation. Two other directives are available they are ifdef timescale are frequently used.

COMPONENTS OF VERILOG
MODULE Verilog provides the concepts of a module.A module is the basic building block in verilog.A module can have an element or a collection of low level design blocks.Typically,elements are grouped in to modules to provide common functionality that is used at many places in the higher level block through its port interface (inputs or ouputs), but hides the internal implementation.This allows the designer to modify module internals without affecting the rest of the design. A module definition always begins with the keyword module.The module name,port list declarations and optional parameters must first come in a module definition.The syntax of module with module name and module terminal list is shown below: Module<module name>(<module terminal list>);

. . <module internals> . endmodule. The five components of within a module declaration,data flow statements,instantiation of lower level modules,behaviour blocks and tasks or functions.An endmodule must always come in module definition. COMPONENTS OF SIMULATION Once a design block is completed,it must be tested.The functionality of the design blocks can be tested by applying stimulus and checking results.We call such a block the stimulus block.The stimulus block is also commonly called a testbench. Ports Ports provide the interface by which the module can communicate with its environment.For example, the input or output pins of an IC chip are its ports. The environment can interavt with its module only through its ports.The internals of the module are not visible to the environment.This provides a power flexibility to the designer.The internals of a module can be changed without affecting the environment as long as the interface is not modified.Ports are also reffered to as terminals.Ports can be declared as input port or output port or bi-directional port based on the direction of the direction of the port signal. The respective keywords are: Keyword Input Output Inout GATE LEVEL INSTRUCTIONS Type of port Input port Output port Bi-directional port

In gate level description,the circuit is described in terms of gates like and,nand,or,xor,nor etc.Hardware design at this level is intuitive to the other user with the basic knowledge of digital logic design.Since it is possible to see a one to one correspondence between the logic circuit diagram and the verilog description.

Gate types All logic circuits can be designed using basic gates.Verilog supports basic logic gates as predefined primitives.There are two classes of basic gates: 1. and/or gate 2. buf/not gate and/or gates have one scalar output and multiple scalar inputs.The first terminal in the list of gate terminal is an output and the other terminals are inputs.The and/or gates available in verilog are: and or xor nand nor xnor Example And a1(z,x,y); Where x,y are inputs and z is the output of the and gate a1. Buf/not gates have one or more scalar outputs and only one scalar input.The last terminal in the portlist is the input.Two basic buf/not gate primitives are provided in verilog namely buf gate and not gate. DATA FLOW INSTRUCTIONS In a complex design where the number of gates are very large,design at a high level of abstraction is necessary.Data flow modeling provides a provides a powerful way for this purpose.Verilog allows a circuit to be in terms of data flow between registers rather than

between individual gates.Data flow modeling describes a design interms of expressions of primitive gates. Assignment statement Assignment statement is used to drive a value on to a net.Assignment statement starts with a keyword assign. Example Assign <list of assignments> Assign out =i1 & i2; Assign {carry,sum} =a+b; Expressions Expressions are constructs that combine operators and operands to produce a result. Example A& b A+ b Operands Operands can be any of the data types defined previously.They can be constants,integers,real,numbers,nets,registers or time. Example C = a-b; // a and b are operands Operators Operators act on the operands to produce desired results.Verilog provides various types of operators.Operators can

be arithmetic,logical,relational,equality,bitwise, reduction,shift, concatenation or conditional.Some of these operators are similar to the operators used in C language.Each operator type is denoted by a symbol.Let us discuss each of the operator types in detail:

Arithmetic operators Arithmetic operators can be unary and binary.Binary arithmetic operators are:

* / + % Examples

Multiply Divide Add Subtract modulus

A*b -This operator multiplies a and b. A%b-This operator gives the remainder. The operators + and also work as unary operators.They are used to specify the positive or negative sign of the operand. Logical operators Logical operators available in verilog are: Logical and (&&) Logical or (||) Logical not (!) The operators && and || are binary operators, while logical not is an unary operator.Logical operators always evaluate to a one bit value either 0,1 or x.

Examples A && b // Evaluates logical and of a,b A || b // Evaluates logical or of a,b Relational operators Verilog provides 4 relational operators given by:

> < >= <=

Greater than Lesser than Greater than or equal to Lesser than or equal to

If relational operators are used in an expression,the expression returns a logical value of one,if it is true and zero if it is false. Examples A <=b/* Evaluates and returns 1 if true or 0 if false Equality operators Four equality operators are provided by verilog.They are: == != === !== Logical equality Logical inequality Case equality Case inequality

When used in an expression equality operators return a value 1 if true and 0 if false.These operators compare the two operands bit by bit. Example

A==b /* compares logically a and b returns 1 If true and 0 if false */ Bitwise operators Bitwise operators available in verilog are: ~ & | ^ ^~ on two operands. Examples ~x //negation of x x^y // bitwise xor of x and y Reduction operators Reduction operators are nand (-&), and(&), or(|),nor(~|),xor(^) and xnor(~^,^~). Reduction operators take only one operand. They perform a bitwise operation on a single vector operand and yield a one bit result.The difference is that bitwise operations are on bits from two different operands,whereas reduction operations are on the bits of the same operand. They work bit by bit from right to left. Shift operators Shift operators are right shift (>>) and left shift (<<).These operators shift a vector operand to the right or left by a specified number of bits.The operands are the vector and the number of bits to shift. Example Negation And Or xor xnor Bitwise operators perform a bit by bit operation

Y = x>>1; /* shift right 1 bit,0 filled in MSB operation. */ Concatenation operator The concatenation operator ({,}) provides a mechanism to append multiple operands.The operands must be sized.Unsized operands are not allowed because the size of each operand must be known for computation of the size of the result.Operands can be scalar nets or registers,vector nets or registers,bit select or sized constants. Example Y={b,c};// appends b and c to result y Conditional operator The conditional operator (?:) takes three operands. Usage Conditional expr ? true expr: false expr; The conditional expression is first evaluated.If the result is true,then the true expression is evaluated.If the result is false,then the false expression is evaluated. Example Assign out = control ? in1 : in0; If the expression is true in1 is assigned to out and if the expression is false in0 is assigned to out.

Operator type Arithmetic

Operator symbol * / + % ! && || > < >= <=

Logical Relational

Equality

Bitwise

Reduction

Shift Concatenation Replication Conditional

== != === !== ~ & | ^ ^~ or ~^ & ~& | -| ^ ^~ or ~^ >> << {} {{}} ?:

Operation performed Mutiply Divide Add Subtract Modulus Logical negation Logical and Logical or Greater than Less than Greater than or equal Less than or equal Equality Inequality Case equality Case inequality Bitwise negation Bitwise and Bitwise or Bitwise xor Bitwise xnor Reduction and Reduction nand Reduction or Reduction nor Reduction xor Reduction xnor Right shift Left shift Concatenation Replication Conditional

Number of operands Two Two Two Two Two One Two Two Two Two Two Two Two Two Two Two One Two Two Two Two One One One One One One Two Two Any number Any number three

BEHAVIOURAL INSTRUCTIONS

Verilog provides designers the ability to describe the design functionality in an algorithmic manner.In other words,the designer describes the behaviour of the circuit.Thus behavioral modeling represents the circuit at a very high level of abstraction.Design at this level resembles C programming more than than it resembles digital circuit designing. Structured procedures There are two structured procedure statements in verilog . Always Initial

These statements are the two most basic statements in behavioural modeling.All other behaviour statements can appear only inside these structured statements. initial statement all statement inside an initial statement constitute an initial block.An initial block starts at time zero,executes once during a simulation and then does not execute again.Multiple behavioural statements must be grouped typically using the keywords begin and end. The initial block is typically used for initialization,monitoring waveforms and other processes that must be executed only once during the entire simulation time. Example The following module illustrates the use of initial statement. Module stimulus; Begin #5 a= 1b1; #5 b=1b0; end endmodule

In the above module,a will be assigned a value of 1 at time 5 and b will be assigned value of 0 at time 10. always statement All statements inside an always statement constitute an always block.The always statement starts at zero time and executes the statements in the block continuously in a digital circuit. Example A clock generator module that toggles the clock signal every half cycle is shown.In real circuits,the clock generator is active from time zero to the time as long as the circuit is powered on. module clock; reg clk; initial clk=1'b0; always #10 clk=~clk; initial #100 $finish; endmodule In the above module,the always statement starts at time zero and executes the statement clk=~clk for every 10 time units. The simulation must be halted inside an initial statement by the use of $finish or $stop statements. Timing control Various behavioural timing control constructs are available in verilog.Timing controls provide a way to specify,the simulation time at which procedural statements will execute. There are three methods of timing control:

1. Delay based timing control. 2. Event based timing control. 3. Level sensitive timing control. Delay based timing control This can be specified by a number,identifier or a mintypmax expression.There are three types of delay control.They are: 1. Regular delay control 2. Intra-assignment delay control 3. Zero delay control Regular delay control It is used when a non zero delay is specified to the left of a procedural assignment. Example Initial Begin X=0; //no delay control #10 y=1; /* delay control with the nuber delay execution of y=1 by 10 units*/ end Intra-assignment delay control Instead of specifying delay control to the left of the assignment,it is possible a delay to the right of the assignment operator. Zero delay control It is a method that the statement is executed, last after all other statements in that simulation time are executed.

Event based timing control An event is the change in the value of a register or a net.There are four types of event based timing control namely,Regular event,Named event,Event OR control and Level sensitive timing control. Event OR timing control Sometimes atransition of any one of multiple signals or events can trigger the execution of the statement or the block of statements.This is expressed as an OR of events or signals.The list of events or signals expressed as an OR is also known as a sensitivity list.The keyword or is used to specify multiple triggers. Example always@(reset or clk or d); /* wait for reset or clk or d to change */ begin if(reset) //if reset is high,set q to zero q=1b0; else if(clk) // if clk is high,set q to d q=d; end Level sensitive timing control Verilog provides level sensitive timing control that is the ability to wait for a certain condition to be true before a statement is executed. Conditional statement Conditional statements are used for making decisions.These conditions decide whether or not a statement should be executed.Keywords if and else are used. Case statement The keywords case,endcase and default are used in the case statement.

Example //Execute statements based on timer ic 8253-control signal reg [1:0] timer ic 8253; . . case (timer ic 8253) 2d0: y=x+z; 2d1: y=x-z; 2d2:y=x*z; default: $display(invalid signal); endcase For loop The keyword for is used to specify this loop. The for loop contains three parts. 1. initial condition. 2. a check to see if the terminating cognition is true. 3. a procedural assignment to change the value of the control variable. Example Integer count; Initial For (count =0;count<128; count= count+1) $display (count=%b,count);

Synthesis and Technology dependence

Algorithm - 0% technology dependent
For i = 0 ; i = 15 sum = sum + data[I]

Architecture - 10% technology dependent i

Data[0]

Data[0]

0]
Data[15]

Data[15]

sum Behavioral synthesis

Summ

- 20% technology dependent

Clear address Clock

Register level

MEM
Clear

sum Logic synthesis

Gate level 100% technology dependent

Important Considerations
You need your network identification card (NIC) ID for licensing the Quartus II software. Your NIC number is a 12-digit hexadecimal number that identifies the Windows NT workstation that serves Quartus II licenses. Networked (or floating node) licensing requires an NIC number or server host ID. When obtaining a license file for network licensing, you should use the NIC number from the PC that will issue the Quartus II licenses to distributed users over a network. You can find the NIC number for your card by typing ipconfig /all at a command prompt. Your NIC number is the number on the physical address line, without the dashes.

Installing the Quartus II Software You need administrative privileges to install the software .
Refer to Installing the Quartus II Software in the Quartus II Installation & Licensing Manual for PCs, which is included on the CD-ROM (in DOC Folder), for the software installation instructions. After the software finishes installing, you must request and install a license to enable it.

Setting Up Licensing
Before using the Quartus II software, you must request a license file from the Altera web site at www.altera.com/licensing and install it on your PC. When you request a license file, Altera e-mails you a license.dat file that enables the software. To obtain a license, perform the following steps: 1. Log on to the Altera web site at www.altera.com/licensing. 2. Click Quartus II Web Edition Software. 3. Follow the on-line instructions to request your license. A license file will be E-mailed to you. 4. To install your license, refer to Specifying the License File in the Quartus II Installation & Licensing Manual for PCs, included on the CD-ROM (in DOC Folder).

A field programmable gate array (FPGA) is a semiconductor device containing programmable logic components and programmable interconnects. The programmable logic components can be programmed to duplicate the functionality of basic logic gates such as AND, OR, XOR, NOT or more complex combinational functions such as decoders or simple math functions. In most FPGAs, these programmable logic components (or logic blocks, in FPGA parlance) also include memory elements, which may be simple flip-flops or more complete blocks of memories. Features in common with FPGAs: Large number of gates available. CPLDs typically have the equivalent of thousands to tens of thousands of logic gates, allowing implementation of moderately complicated data processing devices. PALs typically have a few hundred gate equivalents at most, while FPGAs typically range from tens of thousands to several million. CPLD stands for Complex Programmable Logic Device. It is a programmable logic device with complexity between that of FPGAs and PALs, and architectural features from both. The building block of a CPLD is the macro cell, which contains logic implementing disjunctive normal form expressions and more specialized logic operations Complex Programmable Logic Devices (CPLD) utilize a matrix of "Sum-ofProducts" logic function with a global interconnection