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SASTRA syllabus

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SASTRA syllabus

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SASTRA

Subject Code BICCMA 301 BICCIC 302 BICCIC 303 BICCIC 304 BICCEI 305 BICDIC XXX BICCIC 306 BICCIC 307

Subject Title Engineering Mathematics III Theory of Computation Digital Electronics Data Structures Control Systems DE - 1 Digital Electronics Lab Data Structures Lab TOTAL

Periods of Instruction L T P 3 3 3 3 3 3 0 0 18 1 1 1 1 1 0 0 0 5 0 0 0 0 0 0 3 3 6

Credits 4 4 4 4 4 3 2 2 27

DEPARTMENTAL ELECTIVES: BICDIC 301 BICDIC 302 Linux Programming Electronic Circuits 2 3 0 0 2 3 3 3

BICCMA 301 - MATHEMATICS III (Common for CSE, IT and ICT)

SASTRA

L T P CREDITS 3 1 0 4 UNIT - I (15 Periods) Laplace Transforms Laplace Transform definition Conditions for existence Transform of standard functions Properties Transform of derivatives and integrals Derivatives and integrals of transforms. Inverse Laplace transforms Convolution theorem Transform of periodic functions, unit step function and unit impulse (or dirac delta) function. Applications to solve higher order ordinary differential equations and Simultaneous differential equations with constant coefficients and integro-differential equations. Simple Engineering Applications: Bending of Beams, Whirling of Shafts and Electric Circuits.

UNIT - II (15 Periods) Complex Differentiation Analytic functions Necessary conditions for analyticity Cauchy- Riemann equations in cartesian and polar coordinates Sufficient conditions for analyticity (without proof) Properties of analytic functions: Harmonic functions Orthogonal system Construction of an analytic function when its real or imaginary part is given Conformal mappings - e z , sin z, cos z, z

1 z

and sinh z only Bilinear Transformation. Simple Engineering applications: Complex potential functions, Stream lines, equipotential , velocity potential and stream functions. UNIT - III: (15 Periods) Complex Integration Complex integration Line and Surface Integrals- Cauchys integral theorem Integral formula Taylors and Laurents series (without proof) Singularities Zeros Poles and residues Cauchys residue theorem Contour integration evaluation of integrals of the type

2

f sin , cos d

0

and

g x dx

f x

only.

Unit - IV (15 Periods) Fourier Transforms The infinite Fourier transforms Sine and cosine transforms properties Inversion theorem problems Convolution theorem Parsevals identity Problems Finite Fourier transforms Sine and cosine transforms Evaluation of definite Integrals-problems Solving boundary value problems using finite Fourier sine and cosine transforms.

Text Books:

SASTRA

1. Dr. M.K.Venkataraman, Engineering Mathematics, Part A, National Publishing Company, 2004. 2. P.Kandasamy and K.Thilagavathy, Engineering Mathematics, Vol. III, S.Chand & Co,, 2009. References: 1. B.S.Grewal, Higher Engineering Mathematics, Khanna publishers, 2006. 2. J.Erwin Kreyszig, Advanced Engineering Mathematics, 8 th edition, Wiley eastern Ltd., 2007. 3. Jain R.K and S.R.K. Iyengar, Advanced Engineering Mathematics, Narosa publications, 2006.

BICCIC 302 - THEORY OF COMPUTATION (Common for CSE, IT and ICT)

SASTRA

Introduction: Preliminaries and notations-basic concepts-applications. Finite Automata: Deterministic FA non deterministic FA- Equivalence-minimization. Regular languages and regular grammars: Relation between regular languages and regular expressions-regular grammars-construction of automata using JFLAP. Lex in syntaxical analysis: Declarationsregular expressions-productions-additional code-examples. Properties of Regular Languages: Closure properties-identifying non regular languages. Unit - II (15 Periods)

Context Free Languages: Context free grammars- parsing and ambiguity-left and right recursions and its removal-top down parsing predictive parsers-bottom up parsing using SLR(1). Syntaxical analysis using Yacc: Declaration and additional code-examples. Simplification and Normal Forms: Transformations two important normal forms-membership algorithm for CFG. Unit - III (15 Periods)

Push Down Automata: Non Deterministic PDA-PDA and CFL-Deterministic PDA and determinsitic CFL-Grammars for deterministic CFL. Properties of CFL: Closure properties and decision algorithm for CFL. Turing Machines: Standard TM-TM for complicated tasks-Turing thesis. Other models of TM: Minor variations on TM-TM with complex storage-non deterministic TM-Universal TM-linear bounded automata-construction of PDA and TM using JFLAP. Unit - IV (15 Periods)

A hierarchy of formal languages and automata: Recursive and recursivel enumerable languages-unrestricted grammars-context sensitive grammars and languages-Chomsky Hierarchy. Limits of algorithm computation: unsolvable problems by TM-Undecidable problems for recursively enumerable languages-post correspondence problem-undecidable problems for CFL. Other models of computation: Recursive functions-post systems-rewriting systems. An overview of computational complexity.

Text Books:

SASTRA

1. Peter Linz, An Introduction to Formal Languages and Automata, 5 th Edition, Jones and Bartlet Learning International, United Kingdom, 2011. 2. Alfred V. Aho, Monica S. Lam, Ravi Sethi, Jeffrey D. Ullman, Compilers Principles, Techniques, & Tools, Pearson Education, 2007. 3. John R. Levine, Tony Mason, Doug Brown, Lex and Yacc, Oreilly Media, 1992. References: 1. John E. Hopcroft, Rajeev Motwani, Jeffery D Ullman, Introduction to Automata Theory, Languages and Computation, 3rd Edition, Pearson Education, 2007. 2. Susan H. Rodger and Thomas W. Finley, JFLAP: An Interactive Formal Languages and Automata Package , Jones & Bartlett Publishers, Sudbury, MA, 2006. 3. Michael Sipser, Introduction to the theory of computation, 2 nd Edition, Thomson Course Technology, 2006.

BICCIC 303 - DIGITAL ELECTRONICS (Common for CSE, IT and ICT)

SASTRA

L T P CREDITS 3 1 0 4 UNIT - I Boolean Simplification & Logic Families Boolean Functions: Boolean Laws - Simplifications Using Laws- Minterms Maxterms - Sum of Product and Product of Sum Forms - Karnaugh Map - NAND, NOR Implementation. Digital Logic families: RTL - DTL - ECL - TTL - CMOS Logic Families - Characteristics Comparison of IC Families. UNIT- II Logic Design, PLDS & Memories Combinational Circuits: Adders - Subtractors- Magnitude Comparators - Multiplexer Demultiplexer - Encoder - Decoder. Memories: Semiconductor Memories Types of Memories: RAM, ROM, EPROM, EEPROM, MRAM, CAM, CCD, Flash Memory Programmable Devices: SPLD: PAL, PLA, GAL, PROM, CPLD, FPGA UNIT - III Asynchronous Sequential Machine ASM: Introduction - ASM Charts- Examples of Synchronous Sequential Network Design Using ASM Charts- State Assignment - ASM Tables- ASM Realization for Traffic Control, 2 Bit Synchronous Up/Down Counter, Automatic Bank Teller, Milk Vending Machine, Waveform Generator. UNIT- IV Asynchronous & Synchronous Sequential Circuits Sequential Circuits: Flip Flops: RS- D- JK- T and Master Slave Flip Flops. Registers: Shift Registers- SISO, SIPO, PISO, PIPO and Bi-Directional Registers (15 Periods) (15 Periods) (15 Periods) (15 Periods)

SASTRA

Counters : Design of Synchronous Counters, Design of Asynchronous Counters FSM - Basic Design Procedure - Mealy & Moore Machines - FSM realization Design of Sequential Networks ROM , PLA ,PLDs and PGAs. Text Books: 1. M.Morris Mano - Digital Design, 4th Edition, Pearson Education, 2006. 2. Donald D. Givone , Digital Principles and Designs, Tata McGraw Hill, 2003. 3. Charles H.Roth,Jr, - Fundamentals of Logic Design, 5 th Edition, Thomson. 2007.

References: 1. R.P.Jain - Modern Digital Electronics, 3rd Edition, Tata McGraw Hill, 2006. 2. Bhutiyani. R.S Advanced digital technique & Digital system design, Everest Publishing house, 1993. 3. T.L.Floyd - Digital Fundamentals, 3rd Edition, Pearson Education, 2006.

BICCIC 304 - DATA STRUCTURES (Common for CSE, IT and ICT)

SASTRA

Pseudo code & Recursion: Introduction Pseudo code ADT ADT model, implementations; Recursion Designing recursive algorithms Examples GCD, factorial, fibonnaci, Prefix to Postfix conversion, Tower of Hanoi; General linear lists operations, implementation, algorithms UNIT - II (15 Periods)

Linear Lists: Stacks Basic Operations, Linked stack, Algorithms, Implementation, Applications Infix to Postfix, Evaluation of Postfix - Queues Operations, Linked list design, algorithms, Mazing Problem, Complex implementations circularly linked lists, doubly linked lists Sparse Matrices linked representation, input, output, erase UNIT - III (15 Periods)

Non-Linear Lists: Trees basic concepts, binary trees, traversals, expression trees; General trees insertion, deletion - Conversion of general to binary tree; Binary Search tree basics, operations, ADT, applications Threaded trees; AVL trees basic concepts and implementation UNIT - IV (15 Periods)

Heaps & Trie Structure: Heaps basics, implementation, algorithms; Heap applications Priority Queues; Multi-way Trees B-tree implementation, algorithms, 2-3 tree, Trie structure; Searching sequential and binary search, hashed searches, collision resolution; Graphs Elementary operations BFS DFS - Minimum Cost Spanning Tree - Kruskals & Prims algorithms Text Books: 1. Richard F. Gilberg & Behrouz A. Forouzan, Data Structures: A Pseudocode Approach with C, Thomson Learning, 2nd Edition, 2007. 2. Ellis Horowitz, Sartaj Sahni, & Susan Anderson Freed, Fundamentals of Data Structures in C, University Press, 2nd Edition, 2008 (Sections 3.5, 4.7, 6.1, 6.2.1, 6.2.2, 6.3.1, 6.3.2) References: 1. J.P.Trembley & P.G. Sorenson, "An Introduction to Data Structures with Applications", Tata McGraw Hill, 2nd Edition, 2002. 2. Seymour Lipschutz and G.A.Vijayalakshmi Pai, Data Structures, Tata McGraw Hill, 2005.

BICCIE 305 - CONTROL SYSTEMS (Common for CSE, IT and ICT) L T 3 1

SASTRA

P CREDITS 0 4

UNIT - I (14 periods) Introduction: Definition of control system linear system open loop and closed loop systems block diagrams Transfer function signal flow graph (Masons rule) examples and problems. Control system components: Potentiometers - synchros - A.C. and D.C. tacho generators transfer functions of armature controlled and field controlled D.C. shunt motor A.C. and D.C. servomotors for position control stepper motor gear trains analogy with transformer. UNIT - II (15 periods) Time response of linear systems: First order and second order Systems impulse response and step response of first and second order linear systems time domain specifications like rise time, delay time, overshoot and settling time of a second order system response to ramp input type and order of a system steady state error and error constants generalized error constants examples and problems. UNIT - III (15 periods) Frequency response: correlation between time and frequency response polar plot Bode plots magnitude plot steps for drawing the asymptotic Bode magnitude plot phase angle plot gain and phase cross-over frequencies gain margin and phase margin their definitions and determination from Bode plots-examples and problems. UNIT - IV (16 periods) Stability analysis: concept of stability BIBO criterion characteristic equation stability definitions Routh-Hurwitz stability criterion Nyquist plot Steps for drawing the Nyquist plot Typical Nyquist curves critical point Nyquist stability criterion and its application examples and problems. Root locus technique: Root locus plot rules for construction typical root locus trajectories determination of critical gain. Text Book: 1. I.J. Nagrath & M.Gopal, Control System Engineering, New Age International, 2001. References: 1. Benjamin C.Kuo, Automatic Control Systems, Prentice Hall,India,New Delhi, 7 th Edition 2000. 2. Katsuhiko Ogata, Modern Control Engineering, Prentice Hall,India, New Delhi, 3 rd Edition 2000.

BICCIC 306 - DIGITAL ELECTRONICS LAB (Common for CSE, IT and ICT)

SASTRA

L T P CREDITS 0 0 3 2

1. 4 Bit Adder / Subtractor Sub Modules to be designed / constructed (Prerequisites): Basic gates, Half adder, Half subtractor, Full Adder, Full Subtractor, 2:1 Multiplexer, 2:4 decoder, BCD to Seven Segment Decoder, Understanding of seven segment display. 2. 4-bit Magnitude Comparator Sub Modules to be designed / constructed (Prerequisites) : bit comparator, 4 bit comparator. 3. 4-bit Arithmetic Logic Unit Sub Modules to be designed / constructed (Prerequisites): 8:1 Multiplexer,(4 bit comparator and 4 bit adder have to be used here). 4. 3-bit Asynchronous Ripple Counter Sub Modules to be designed / constructed (Prerequisites): SR Latch, JK, SR, T and D Flip Flops. 5. Register File, Instruction and Data Memories: Sub Modules to be designed / constructed (Prerequisites): PIPO, PISO, SIPO and PIPO Shift Registers, 4: 1 Multiplexer 6. Assembling the Processor: Sub Modules to be designed / constructed (Prerequisites): 3 bit asynchronous counter (PC) , ( combination of all the above experiments).

BICCIC 307 - DATA STRUCTURES LAB (Common for CSE, IT and ICT)

SASTRA

L T P CREDITS 0 0 3 2 1. Create a Stack and do the following operations using arrays. (i) Push (ii) Pop (iii) Peep (iv) Display 2. Create a Queue and do the following operations using arrays (i) Enqueue (ii) Dequeue (iii) Search (iv) Display 3. Implement insertion, deletion and display operations on singly linked list 4. Implement conversion of infix expression to postfix using linked stack. 5. Implement insertion, deletion and display operations on doubly linked list 6. Implement insertion, deletion and display operations on circular doubly linked list. 7. Implement the following operations on a binary search tree: a. Insert a node (ii) Delete a node (iii) Traversals - In-order, Pre order, & Post order 8. General Tree to Binary Tree Conversion 9. Implement the following operations on B-tree: (i) Insert a node (ii) Delete a node (iii) Display using preorder traversal 10. Implement the following operations on trie structure : (i) Insert a node (ii) Delete a node (iii) Search for a node (iv) Display using preorder traversal 11. Sort the list of numbers using Heap sort and Merge Sorting Techniques 12. Implement the following three searching techniques for a set of numbers (i) Linear Search (ii) Binary Search (iii) Hash Search using modulo division method (Chained Hashing) 13. Traverse the nodes of the graph using BFS and DFS. 14. Minimum Cost Spanning Tree using Prims algorithm

BICDIC 301 - LINUX PROGRAMMING (Common for CSE, IT and ICT)

SASTRA

Introduction and Shell Programming: Basic Linux Programming Concepts Man Pages Redirection and Piping Variables Functions Conditionals and Loops Shell utilities. Regular Expressions, Emacs, Linux Data files and scripts: Introducing Regular Expressions Understanding character classes using quantifiers Introducing Alternation and Grouping Supporting Regular Expressions in Linux Emacs modes and Emacs as an IDE. UNIT - II (15 Periods)

File Handling: The File Mode Basic File Operations querying and changing Inode Information Manipulating Directory Entries Manipulating File Descriptors Creating Unnamed Pipes. Advanced File Handling: Input and Output Multiplexing Memory Mapping File Locking Scatter/Gather Reads and Writes. UNIT - III (15 Periods)

Signal Processing: Signal Concepts The Linux and POSIX signal API Available signals Writing Signal Handlers Reopening Log Files. Networking with Sockets: Protocol support Utility Functions Basic Socket Operations Unix Domain Sockets Networking Machines with TCP/IP Socket Errors. UNIT - IV (15 Periods)

The Linux Console, String Matching: Globbing Arbitrary Strings Regular Expressions. Terminal Handling with S-Lang: Input Handling Output Handling. The Database Library: Overview Basic Operations Reading Records Modifying the Database. Text Books: 1. John Goerzen, Linux Programming Bible, IDG Books India (P) Ltd., 2000. (Unit - I) 2. Michael K. Jhonson, Erik W. Troan, Linux Application Development, Addison Wesley, Pearson Education, 2000. (Unit II, III & IV) References: 1. Richard Petersen, Linux: The Complete Reference, Tata McGraw Hill, 2 nd Edition, 2001. 2. Neil Mathew and Richard Stones, Professional Linux Programming, Wrox Press Ltd., 2001.

BICDIC 302 - ELECTRONIC CIRCUITS

SASTRA

L T P CREDITS 3 0 0 3 UNIT - I (11 Periods) Biasing of BJT & FET: BJT Biasing - Operating Point - DC Load Line Types of Biasing - Bias Stabilization Bias compensation FET: Types of Biasing MOSFET: Types of Biasing UNIT - II Small Signal Analysis and Frequency Response of BJT & FET: Small signal analysis Classifications of Amplifier - Common emitter amplifier, Common base amplifier, Emitter follower: re model h parameter hybrid model Multistage amplifier- Cascade connection, Cascode connection. FET: FET small signal model Common source Common drain MOSFET amplifier: Graphical analysis and small signal parameters, small signal equivalent circuit Common Source amplifier Frequency response Frequency analysis of RC coupled amplifier BJT & FET Miller effect capacitance UNIT - III (11 Periods) Feedback Amplifiers and Oscillators Feedback concepts Feedback connection types Feedback amplifiers Merits and demerits Oscillators - Principle of operation Phase shift Wien bridge crystal LC oscillators using BJT-UJT Relaxation Oscillator UNIT - IV (11 Periods) Tuned Amplifiers and Power Amplifiers Tuned Amplifier: Single Tuned - Double Tuned- Stagger tuned. Power amplifiers: Working principle of Class A, Class AB, Class B, Class C, Class D and Class S amplifiers.-efficiency of class A, Band C amplifiers. Text Books: 1. Robert L. Boylestad & Lousis Nashelsky Electronic devices & Circuit Theory Pearson education, 9th edition, 2007. 2. Theodore Bogart. Jr, Jefrey S.Beasely, Guilermo Ricco Electronic Devices and Circuits Pearson, 6th ed, 2004. 3. Donald A Neamen, Electronic Circuit Design and Analysis, Tata McGraw Hill, 2002. Reference: 1. Millman J, Halkias C.C, Electronic Devices and Circuits, Tata McGraw Hill, 2002 (12 Periods)

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