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Fig. 7.

Fixed-bias configuration.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.2

Network for dc analysis.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.3

Plotting Shockleys equation.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.4

Finding the solution for the fixed-bias configuration.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.5

Measuring the quiescent values of ID and VGS.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.6

Example 7.1.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.7

Graphical solution for the network of Fig. 7.6.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.8

JFET self-bias configuration.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.9

DC analysis of the self-bias configuration.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.10

Defining a point on the self-bias line.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.11

Sketching the self-bias line.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.12

Example 7.2.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.13

Sketching the self-bias line for the network of Fig. 7.12.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.14

Sketching the device characteristics for the JFET of Fig. 7.12.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.15

Determining the Q-point for the network of Fig. 7.12.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.16

Determining the quiescient point of operation for the network of Example 7.2.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.17

Example 7.3.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.18

Example 7.4.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.19

Sketching the dc equivalent of the network of Fig. 7.18.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.20

Determining the Q-point for the network of Fig. 7.18.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.21

Voltage-divider bias arrangement.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.22

Redrawn network of Fig. 7.21 for dc analysis.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.23

Sketching the network equation for the voltage-divider configuration.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.24

Effect of RS on the resulting Q-point.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.25

Example 7.5.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.26

Determining the Q-point for the network of Fig. 7.25.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.27

Example 7.6.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.28

Determining the network equation for the configuration of Fig. 7.27.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.29

Determining the Q-point for the network of Fig. 7.27.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.30

Example 7.7.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.31

Determining the Q-point for the network of Fig. 7.30.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.32

Example 7.8.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.33

Example 7.9.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.34

Determining the Q-point for the network of Fig. 7.33.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.35

Example 7.10.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.36

Transfer characteristics of an n-channel enhancement-type MOSFET.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.37

Feedback biasing arrangement.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.38

DC equivalent of the network of Fig. 7.37.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.39

Determining the Q-point for the network of Fig. 7.37.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.40

Example 7.11.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.41

Plotting the transfer curve for the MOSFET of Fig. 7.40.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.42

Determining the Q-point for the network of Fig. 7.40.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.43

Voltage-divider biasing arrangement for an n-channel enhancement MOSFET.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.44

Example 7.12.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.45

Determining the Q-point for the network of Example 7.12.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.46

Example 7.13.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.47

Determining the Q-point for the network of Fig. 7.46.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.48

Example 7.14.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.49

Determining the Q-point for the network of Fig. 7.48.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.50

Self-bias configuration to be designed.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.51

Example 7.15.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.52

Determining VGSQ for the network of Fig. 7.51.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.53

Example 7.16.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.54

Example 7.17.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.55

Checking the dc operation of the JFET self-bias configuration.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.56

p-Channel configurations. (a) JFET; (b) Depletion-type MOSFET; (c) Enhancement-type MOSFET.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.57

Example 7.18.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.58

Determining the Q-point for the JFET configuration of Fig. 7.57.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.59

Universal JFET bias curve.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.60

Example 7.19.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.61

Universal curve for Examples 7.19 and 7.20.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.62

Example 7.20.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.63

JFET characteristics: (a) defining the linear region; (b) expanding the linear region.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.64 V.

JFET voltage-controlled drain resistance: (a) general equivalence; (b) with VGS = 0 V; (c) with VGS = -1.5

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.65 (a) Noninverting op-amp configuration; (b) using the voltage-controlled drain-to-source resistance of a JFET in the noninverting amplifier.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.66

Demonstrating the benefits of dc control: system with (a) ac control; (b) dc control; (c) RF noise pickup.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.67 JFET voltmeter: (a) network; (b) reduced equivalent with an 8-V measurement. (Redrawn from International Rectifier Corporation.)

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.68

JFET timer network.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.69

Basic elements of a fiber optic cable.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.70

Basic components of an optical communication system.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.71 TTL fiber optic communication channel: (a) JFET design; (b) passing on the signal generated across the photodiode.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.72

MOSFET relay driver.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.73

JFET voltage-divider configuration with PSpice Windows results for current and voltage levels.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.74

Verifying the hand-calculated solution of Example 7.13 using PSpice Windows.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.75

Network used to obtain the characteristics of the IRF150 enhancement-type n-channel MOSFET.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.76 7.77.

Characteristics of the IRF500 MOSFET of Figure 7.75 with a load line defined by the network of Figure

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.77

Feedback-biasing arrangement using an IRF150 enhancement-type MOSFET.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.78

Verifying the results of Example 7.2 using Multisim.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.79

Problems 1 and 35.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.80

Problem 2.

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Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.81

Problem 3.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.82

Problem 4.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.83

Problem 5.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.84

Problems 6, 7, and 36.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.85

Problem 8.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.86

Problem 9.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.87

Problem 10.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.88

Problem 11.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.89

Problems 12 and 13.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.90

Problem 14.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.91

Problems 15 and 37.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.92

Problem 16.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.93

Problem 17.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.94

Problem 18.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.95

Problem 19.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.96

Problem 20.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.97

Problem 21.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.98

Problem 22.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.99

Problem 26.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.100

Problem 27.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.101

Problem 28.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.102

Problem 29.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Fig. 7.103

Problem 30.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.