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15.

(a)

(i) (ii) (iii)

Write a Verilog code for the 4-bit adder/subtracter. Design a Verilog module for the master-slave flip flop.

(5) (5)

Write the test bench to verify the gate level modeling of SR Iatches. (6) Or

(b)

(i)

Write the continuous assignment following Boolean functions :

statements

describing

the

F(A,B,C)= Lm(O,1,4,5,6, 7).


(ii) Design a shift register by a synchronous list of procedural assignments. cyclic behaviour

(8)

with the
(8)

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