Analog Calibration of Channel Mismatches in Time-Interleaved ADCs

Pieter Harpe, Hans Hegt, Arthur van Roermund
Mixed-signal Microelectronics Group, Eindhoven University of Technology, Eindhoven, The Netherlands, email:

Abstract— This paper presents a method for the on-chip measurement and correction of gain errors, offsets and time-skew errors in time-interleaved ADC’s. With the proposed method, the errors can be measured and processed in the digital domain. Then, this information is used to optimize several digitally controlled analog parameters of the circuit, that minimize the effect of aforementioned mismatch errors. After optimization, the digital logic can be switched off completely in order to save power. Simulation results on a full-transistor implementation of the time-interleaved sampling structure show that the channel matching errors can be accurately compensated.

I. I NTRODUCTION Time-interleaving multiple analog-to-digital converters (ADCs) [1] is a widely used approach to accommodate the demand for higher sampling rates combined with high accuracy and low power consumption. For example, in fig. 1 p parallel ADCs, each with a separate track-and-hold (T&H) circuit, are combined to compose a p times faster ADC.
fs/p T&H 1 ADC 1 Combine


T&H 2


N-bit @ fs

T&H p


Fig. 1.

N -bit p-channel time-interleaved ADC.

Matching errors (which are mainly offsets, gain errors and time-skew errors [2]) between the ideally identical channels limit the performance of the overall ADC, and should be small enough to achieve the final speed/accuracy target. However, especially for high sampling rates and a large amount of channels p, it is difficult to achieve sufficient matching by design alone. Therefore, solutions were developed that can improve the channel-matching by measuring and correcting the actual errors on-chip (e.g. [3], [4], [5], [6], [7]). Several distinct properties can be found within the currently available techniques, but most of them share one or more of the following disadvantages or limitations:
This work is sponsored by Stichting Technische Wetenschappen.

The method works only for a subset of the three types of mismatch (offsets, gain errors and time-skew errors). • The method puts constraints on the input signal (background techniques), or requires input signals with specific accuracy requirements (foreground techniques). • The method works only for a 2-channel ADC, or the complexity increases strongly (i.e. faster than a linear increase) as a function of the number of channels. • The complexity (and hence the power consumption) of the correction method is such that it becomes unattractive for a power-efficient implementation. • The method is based on stochastics and therefore requires a large amount of observations or iterations to achieve a certain level of accuracy. Because of these drawbacks, a new method is proposed here that measures and corrects for offsets, gain errors and time-skew errors. The presented foreground method uses a deterministic test-signal, of which the accuracy and dynamic performance are unimportant, as long as the signal is periodic. Because of the deterministicity, fast convergence of the algorithm is achieved, while the implementation is simple because of the low constraints. The method is implemented in such a way that it can be applied to any number p of parallel channels, without increasing the complexity. Furthermore, the actual correction is performed by means of analog calibration and does not consume additional power. The paper is composed as follows: section II introduces the time-interleaved ADC system, including the test-signal generator and the algorithms for detection and correction of matching errors, followed by simulation results in section III. Finally, conclusions are drawn in section IV.

II. C HANNEL M ISMATCH C ALIBRATION A. System Overview Fig. 2 shows an overview of the setup used to detect and to correct for the mismatch errors in a time-interleaved ADC. A digital signal generator is used to generate a deterministic and periodic test signal, that is applied to the ADC by means of a DAC. The ADC is a p-channel time-interleaved ADC (as in fig. 1), of which the gain, offset and time-skew can be adjusted by means of digitally controllable analog parameters. A digital processing block is used to estimate the individual mismatches, and to control the analog parameters in order to

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such that the feedback algorithm can optimize the overall performance iteratively. therefore.3 Frequency (relative to Fs) 0. because of several beneficial properties: • An MLS sequence has a wide frequency spectrum (up to the Nyquist frequency). [10]. gain and timeskew error (denoted by Oi . which simplifies the detection algorithm that will be discussed next. a single reference channel is chosen arbitrarily (e. Normalized autocorrelation r[n] s[n] 0 10 20 30 40 Time shift tau 50 60 Fig.4 0. the wide spectrum prevents that the system will be optimized for one specific frequency only.8 0. resulting in a sequence length m of: m = 2M − 1 = 63 (2) When m is chosen relatively prime to the number of channels p. i = 1 is used throughout this paper). This means that Oi . each symbol of the sequence s[n] will have been applied exactly once to each channel of the ADC.2 Normalized power spectrum of r[n] and s[n]. the channelmismatch information now also becomes available for each channel separately.1 0. Nevertheless. correct estimations can be made by comparing the responses ui [n] with each other. Figures 3 and 4 show for both r[n] and s[n] the frequency spectrum and the autocorrelation function. the bits in s[n] are shifted one position. one can write (as u1 [n] is assumed to be the ideal response): ui [n] = Oi + Gi · u1 [n] . s[n] and the exact waveform produced by the DAC (including mismatches and dynamic behaviour) are unknown signals. • The hardware implementation is simple. based on the MLS signal r[n]: each sample moment. presented before in [9]. (3) The shift-register operation influences the frequency spectrum and the autocorrelation of the signal. Detection and correction of channel mismatch errors. absolute accuracy of the estimations is not of extreme importance. 4. it was designed as a 16-bit sub-binary scaled DAC. such that the response will be sensitive to time-skew errors. and a new bit from r[n] is added: s[n]15:1 s[n]0 = = s[n − 1]14:0 r[n] (1) -15 0 0. Because of the iterative procedure. and that for the detection algorithm. Moreover. Gi and ∆i will be determined and calibrated relative to channel 1.minimize these errors iteratively. In the subsequent sections.5 Fig. • An MLS sequence is always periodic. test-signal generation on-chip DAC time-int. Note that the MLS order M equals 6 in these examples. gain-errors and time-skews of the different channels of the ADC. 2. -5 s[n] -10 B. white noise. A 16-bit serial-in parallel-out shift register is used to generate a 16-bit signal s[n] driving the DAC. the error detection and the correction will be discussed. First of all. which is sufficient to minimize the mismatches. respectively. against which the other channels will be compared. after m · p sample moments.2 0 -0. which could be the case with a single sinusoidal input signal. with an intrinsic accuracy of less than 6-bit [11]. etc. As the DAC will be used as well for other correction methods. By reordering the output data. averaging of multiple measurements is possible if necessary. C. 1 0. respectively). Because of this. Gi and ∆i . 0 Normalized power (dB) r[n] Fig. Note that the length of each response equals the period length m of the original input signal s[n]. 3. but the properties mentioned before remain valid. but here a specific choice has been made to base the input signal on a pseudorandom maximum-length sequence (MLS) [8]. Normalized autocorrelation function for r[n] and s[n]. By observing the resulting digital response of the ADC. the detection algorithm is able to determine estimations of the offsets.) could be used as an input signal within the given setup. Then. Considering the static errors (offset and gain error) first.6 0. based on the measured output responses ui [n]. an on-chip signal generator is used to provide the ADC with a test-signal.2 0.g. the test-signal generation. an on-chip DAC is used to convert the sequence to the analog domain. Various input signals (sinusoids. the response ui [n] of each individual channel i of the ADC to the digital input signal s[n] 237 .4 0. Test-Signal Generation In the presented setup. ADC processing can be determined separately. Channel Mismatch Detection The goal of the mismatch detection algorithm is to find for each ADC channel i estimations for the offset.

The time-skew ∆i is estimated by a partial summation of D2 [τ ]: 15 ∆i = C ∆ · Di [τ ] τ =0 .i [τ ] − R1. Analog Mismatch Correction For the actual correction of the offsets. c2 and c3 are constants. because of the iterative error-optimization procedure. relative to channel 1. ±10ps and ±100ps) were added to channel 2 of the T&H. For correction of offset and gain. As for any MLS-generated sequence the DC component tends to go to zero (see fig. Nevertheless. D. D[τ ] for various time-skews (±1ps.   δ [k ] = δi [k − 1] + c3 · ∆i [k ] i (9) where c1 .i [k − 1] − c1 · Gi [k ] − c2 · Oi [k ] IB.01 +100ps +10ps +1ps -1ps -10ps -100ps ui [n] − m−1 n=0 0 u1 [n] . and averaging over the m samples: 1 Gi = m m−1 n=0 -0.i [k ] = IB. two programmable current sources (IA. (4) based on which the gain can be estimated by substituting Oi = Oi in (3).01 ui [n] − Oi u1 [n] 0 10 20 (5) 30 40 Time shift tau 50 60 Fig. 6. 5 shows the results for D2 [τ ]. the difference Di [τ ] will be related to the time-skew error ∆i : Di [τ ] = R1.i [k ] = IA. and various time-skews (±1ps.i [k − 1] − c1 · Gi [k ] + c2 · Oi [k ] . 100 80 For the estimation of the time-skew error. a clock-buffer with programmable delay (δi ) is included in the chain driving the sampling switch of the T&H. the parameter-update functions are simple linear combinations of the error estimations:    IA.i [τ ] is defined as the crosscorrelation between channel 1 and channel i. For the timing correction. based on the simulated responses ui [n]. III. the offset can be estimated by the average difference between u1 [n] and ui [n]: 1 Oi = m m−1 n=0 0. (5) and (8) is not of extreme importance. where the offset and gain of channel i are already corrected by means of the previously estimated values: R1. The resolutions of the three controllable parameters were chosen such that the post-correction accuracy of the system can achieve 10-bit accuracy for a 2-channel timeinterleaved ADC operating at fs = 1GSPS. ±10ps and ±100ps). offset and timing of each channel can be adjusted. it is to be expected that in any case. Estimated time-skew as a function of the actual time-skew. It appears indeed that the magnitude of D2 [τ ] and hence also ∆i are approximately linear functions of the actual time-skew.18µm technology) of a 2-channel The behaviour of Di [τ ] as a function of the time-skew ∆i will be dependent on the actual DAC. Because of this.i [τ ] will be equal to the autocorrelation of channel 1: R1. and k indicates the iteration of the feedback algorithm.i [τ ] = m−1 n=0 Estimated time-skew error (ps) 60 40 20 0 -20 -40 -60 -80 -100 -100 u1 [n] · ui [n + τ ] − Oi Gi (6) -50 0 50 Actual time-skew error (ps) 100 In case channel i is perfectly matched.i and IB. Di [τ ] will have a linear relation with the time-skew as long as the time-skew is small enough. gain errors and timeskew errors. 3). a slight time-skew error ∆i of an ADC channel results in a change of the measured response ui [n]. (8) where C∆ is a constant chosen based on simulated results. 238 . the absolute accuracy of the estimations (4).1 [τ ] (7) Fig. simulations were carried out on a transistor-level implementation (in a CMOS0. 5. As in [10]. The sample frequency of the DAC and the T&H was set to fs = 100MSPS. 6 shows the resulting estimation ∆i as a function of ∆i .1 [τ ]. With these three parameters gain. Note that. To detect this change in ui [n]. Fig. This was verified by means of a realistic transistor-level simulation of a DAC and a 2-channel T&H system. R1. we use the property that the output signal of the DAC is a time-continuous signal.D [tau] where Oi denotes the actual offset and Gi the actual gain of channel i. each T&H contains three digitally controllable analog components. S IMULATION R ESULTS To verify the presented channel-mismatch calibration method. with a certain settling behaviour around the code transitions.i ) are implemented in the T&H as presented in [10]. Fig. crosscorrelation is used: R1. Hence. as mentioned before. its transition behaviour and the T&H used in the system.

A 2-channel system was selected to minimize simulation time. 0 -20 Relative power (dB) -40 -60 -80 -100 -120 -Gain/Time-skew 62. “Spectral shaping of timing mismatches in time-interleaved analog-to-digital converters. Vogel. limiting the overall linearity of the ADC to 29. It can be seen that the distortion components HD3 and HD5 of the T&H remain almost constant. 50. during this calibration phase the time-interleaved ADC was also set to operate at fs = 100MSPS. L¨ owenborg. Hodges. J. Vogel and H. “Calibration of sample-time error in a two-channel time-interleaved analog-to-digital converter. 2005. H.. [11] P. Hegt. 1394 – 1397. “Compensation of timing mismatches in time-interleaved analog-to-digital converters through transfer characteristics tuning. Draxelmayr. I.” in proc. 8. Draxelmayr. [5] S.5 Fig. the complexity of the error detection algorithm remains constant for any number of channels. Harpe. [6] C. G2 = 1. IEEE ISCAS 2006. 2006. Circuits Syst. IEEE ISCAS 2007. M. and A. C.4 0. Inc.9dB -HD3 64. a method was presented to measure and correct for offset. 0 -20 Relative power (dB) -40 -60 -80 -100 -120 -Gain/Time-skew 29. pp. and G. 8. [8] S.” IEEE J. J. G2 = 1. The THD of a single T&H is around -62dB. 1967. Golomb. Harpe. 341 – 344. 7. limiting the overall performance to 10-bit at most. [9] P. Kubin. Zanikopoulos. By measuring the response of each individual channel as opposed to measuring the combined response of all channels. Vogel. Dec. “Novel digital pre-correction method for mismatch in DACs with built-in self-measurement.8dB. “An analog background calibration technique for timeinterleaved analog-to-digital converters. “Digital post-correction of front-end track-and-hold circuits in ADCs.1 0. vol. Nov. H. and F. [4] H.” in proc. Holden-Day. [10] P. The achieved post-correction accuracy is limited by the resolution of the analog parameters. 2002.4 0. 2004. Jamal et al.” IEEE J.8dB -HD3 62. 25 – 30. operating at fs = 1GSPS. Solid-State Circuits. [2] C. 15. The distortion components of the T&H (HD3 and HD5) can be seen as well as the tones due to channel mismatch: a tone at DC due to the offset mismatch. C ONCLUSION In this paper. “Time interleaved converter arrays. van Roermund. IEEE ISCAS 2005. no. 12. pp. yielding O2 = 0. 7.6dB Fundamental signal of the parameters. R EFERENCES [1] W.6dB -HD5 64. Johansson and P. fs was set back to the original value of 1GSPS. 2007. 11. The quantizers were implemented with ideal 12-bit ADCs. 1980. de Meulmeester. which should be the case. M. IV.2 0. the overall linearity of the ADC improves from 29. IEE ADDA 2005. A. Hegt. 1998. as they are not influenced by the channel mismatch correction. After 11 iterations of the algorithm.5 Fig. W. As the sample frequency of the DAC was limited to 100MSPS. van Roermund. and a second tone due to gain and time-skew mismatch.6mV. 1503 – 1506. “Reconstruction of nonuniformly sampled bandlimited signals by means of digital fractional delay filters.0064 and ∆2 = 30ps.7dB -Offset 49. As a result. pp. according to the theory presented in this paper. Black and D. 12. pp. A. Jan. A.1 0. May 27 – 30. vol. no.time-interleaved T&H structure. [7] C. Harpe. J. the performance of the ADC was verified again.3 Frequency (GHz) 0. 51. Shift Register Sequences. respectively. 2006.0012 and ∆2 = 0. 1912 – 1919. For this purpose. IEEE MWSCAS 2004. M.” in proc. van Roermund... pp. July 25 – 27. 130 – 139. 3386 – 3389. no. but the method could have been applied equally well to an ADC with more than 2 channels. Based on the final performance.5dB. Kuttner.6dB Fundamental signal 0 0. First of all. By increasing the resolution 239 . IEEE ISCAS 2006. [3] K. Hegt. “Analog calibration of mismatches in an open-loop track-and-hold circuit for time-interleaved ADCs. 0 0. no. Next. Signal Processing.08mV. Output power spectrum for the uncorrected 2-channel ADC. 2757 – 2767. D. vol.” in proc. it will be possible to further reduce the distortion components arising from channel mismatch. the following combination of mismatch errors was applied to one channel of the ADC: O2 = 1. Dyer et al. vol. Zanikopoulos.8dB and -62. Solid-State Circuits.2 0. 1022 – 1029. Applying a sinusoid with frequency 1024 fs yields the output spectrum of fig. gain and time-skew errors in time-interleaved ADCs using a single integrated algorithm.7dB to 57. The distortion components due to offset and gain/time-skew were reduced to -71. the post-correction matching accuracy can be derived.4ps. A. In this case.5dB -Offset 71. 33. pp.3 Frequency (GHz) 0. May 21 – 24. “Time-interleaved analog-to-digital converters: Status and future directions.” in proc. the self-measurement and self-correction algorithms were applied to the ADC. a transistor-level implementation of a DAC (with an intrinsic accuracy of only 6-bit) was used as a test-signal generator. the time-skew mismatch is dominant. Johansson.7dB.” in proc.” IEEE Trans. A. Output power spectrum for the corrected 2-channel ADC. which is a realistic performance for an intrinsic circuit without 347 correction. Simulations on a transistor-level implementation working at 1GSPS show that the SFDR improves by almost 30dB within 11 iterations of the algorithm. pp. H. and A. The actual correction is performed in the analog domain in such a way that no additional power is consumed. The output power spectrum after correction is visualized in fig. D. pp. 2005. and A. pp. May 21 – 24. For this purpose.2dB -HD5 64. 1. C. with a full-scale range of Vpp = 1V. Dec.” IEEE Trans. This set of errors was chosen as they correspond to 8-bit performance while operating at fs = 100MSPS.