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Microcontroller

8051 Architecture
8051 specific features 1. Eight-bit CPU with registers A and B

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2. Sixteen-bit program counter (PC) and data pointer (DPTR) 3. Eight-bit program status word (PSW) 4. Eight-bit stack pointer (SP) 5. Internal ROM or EPROM 6. Internal RAM of 128 bytes 7. Thirty-two input/output pins arranged as four 8-bit ports: P0 - P3 8. Two 16-bit timer/counters: T0 and T1 9. Full duplex serial data receiver/transmitter: SBUF 10. Control registers: TCON, TMOD, SCON, PCON, IP and IE 11. Two external and three internal interrupt sources 12. Oscillator and clock circuits See 8051 hardware 8051 programming model 8051 programming model comprised of 8 and 16 bit registers with 8 bit memory locations. We used these registers with memory and software instructions working together to control any device. The addition of special registers makes 8051 architecture really a microcontroller. Most registers have specific functions with symbolic name such as A, THO and PC. Some registers has byte addressable while others bit addressable. The programming model wants that the entire byte or each bit to be read or altered. The programming model are generally able to specify a register by its address, symbolic name or both. 8051 oscillator clock All operations in a microcontroller are synchronized by the help of an oscillator clock. The oscillator clock generates the clock pulses by which all internal operations are synchronized. A resonant network connected through pins XTAL1 and XTAL2 forms up an oscillator. For this purpose a quartz crystal and capacitors are employed. The crystal run at specified maximum and minimum frequencies typically at 1 MHz to 16 MHz. When you read the spec a minimum frequencies would imply that some internal memories must always operate above a minimum frequency or data will be lost.

Standard communication frequency A standard communication frequency is needed when you connect your microcontroller to a serial data communication device. Internal counters must divide the basic clock rate so that standard communication bit per second rates or baud can be produced. The basic clock frequency should be divisible for resulting communication frequency to be standard. Machine cycle Crystal oscillator, capacitor and on-chip inverter generates a pulse train at the frequency of the crystal. Smallest time called P time are being established by the clock frequency. The machine cycle is the time needed to accomplish any simple instruction. The machine cycle is made up of six states. A state is the basic time interval for microcontroller 8051 architecture to fetch an op-code byte, decoding an op-code, executing an op-code or writing data byte. See 8051 hardware. Program instructions One, two or more machine cycles are needed to run program instructions. The program instruction begin with instruction located at ROM memory address 0000h. It is important to calculate the time taken to execute one program instruction. Execution time The time needed to execute any particular instruction is determined by the formula

C is the number of cycles to execute the program F is the frequency of the crystal Hold address byte Both program counter (PC) and data pointer (DPTR) are 16-bit registers for holding address of a byte in a memory of 8051 architecture. Program Counter (PC) A program counter fetches bytes from locations in memory that are addressed by the program counter. Program ROM is at addresses 0000h until 0FFFh. PC is automatically incremented after every instruction byte is fetched. PC does not have an internal address.

Data Pointer (DPTR) DPTR or data pointer is made up of two 8-bit registers namely DPH and DPL needed for filling memory addresses internal and external code access. DPTR is specified by each individual byte name, DPH and DPL. A B CPU registers 8051 architecture has 34 general purpose or working registers. The logical and math operations are being hold by A and B registers. The other 32 registers hold the mathematical core operation. A register holds addition, subtraction, multiplication and division and Boolean bits manipulations. B register works together with A as storing data during multiplication and division. Flags Flags is the 1-bit registers that stores results of certain program instructions. The flag make states that decisions can be made upon them. Flags are grouped inside program status word (PSW) and the power control (PCON) registers. 8051 architecture has four math flags function as a responder to the math operations results and three general purpose flags for setting or clearing 1 or 0 as the programmer desired. General purpose flags are named F0, GF0 and GF1 used to record some event. Math flags include 1. Carry (C) 2. Auxiliary Carry (AC) 3. Overflow (OV) 4. Parity (P) Program status word Program status word or PSW contains math flags, user program flag F0 and register selected bits used to identify the four general-purpose register banks that are currently in used. GF0 and GF1 are stored in PCON. See 8051 hardware. Internal Memory ROM and RAM have memory for program code bytes for variable data that can be altered when you run the program. You can provide external memory to internal memory by using suitable circuits. Von Neumann Harvard architecture Von Neumann architecture has a single memory address for either program code but cannot hold two addresses from the same memory. The Harvard architecture can has sam addresses in different memories. The 8051 architecture is following Harvard architecture design. Internal RAM Internal RAM has memory 128-byte. See 8051 hardware for further internal RAM design. Internal RAM is organized into three distinct areas: 1. 32 bytes working registers from address 00h to 1Fh 2. 16 bytes bit addressable occupies RAM byte address 20h to 2Fh, altogether 128

addressable bits 3. General purpose RAM from 30h to 7Fh Stack Pointer There is an area inside internal RAM called stack that deals with certain op-codes for storing and retrieving data quickly. 8-bit Stack Pointer or SP is used by 8051 architecture for holding internal RAM address called top of stack. The stack operation stored last byte of data in the top of stack. When data send to stack, it will be incremented before data is stored. However SP will be decremented if data is retrieved from the stack. Operation of the stack is shown in 8051 hardware. Special Function Registers (SFR) Any 8051 architecture that do not use the internal 128-byte RAM addressees from 00h to 7Fh are being taken care of by Special Function register or SFR by using addresses from 80h to FFh. SFRs that has asterisk symbol shown are bit addressable that allows programming to change that needs to be changed and leave the remaining bits unchanged. SFR names and equivalent internal RAM addresses are given in 8051 hardware. SFRs are named in certain op-codes by their functional names such as A while referenced by other op-codes by addresses such as 0E0h. Internal ROM Data memory and program code memory both are in different physical memory but both have the same addresses. An internal ROM occupied addresses from 0000h to 0FFFh. PC addresses program codes from 0000h to 0FFFh. Program addresses higher than 0FFFh that exceed the internal ROM capacity will cause 8051 architecture to fetch codes bytes from external program memory.
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Questions
Execution time 1. Find execution time of a single cycle instruction for a 6 MHz crystal. Addressing registers 2. Find the 16-bit data addressing registers and their functions. Division 3. Find registers that can do divisions. Program status word (PSW) 4. Find flags that are stored in the PSW.

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