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A Low Voltage Current-Bleeding Down-Conversion

Folded Mixer

Nona Messhenas
* Kerman Graduate University of Technology
kerman, Iran
Nona.messhenas@gmail.com
Ahmad Hakimi
Kerman Shahid Bahonar University
kerman, Iran
Hakimi@uk.ac.ir
AbstractThis paper presents an ultra low voltage down
conversion CMOS mixer. To facilitate low-voltage operation, the
mixer employs a folded Gilbert cell topology with PMOS devices
for LO switches. The folded topology allows the
transconductance and LO stages to have different bias current.
Current bleeding technique has been used to improve the
conversion gain, NF and the linearity due to the higher RF stage
bias current without varying the switching transistors current.
Inductive peaking technique is also used to succeed extension
bandwide. A comparison with conventional down-conversion
mixers shows that this mixer has advantages of simultaneous low-
voltage and high performance. The mixer is simulated using 0.13-
m CMOS process model by advanced design system (ADS) tool
and results show that under 0.7V supply, a flatness conversion
gain 7.9_1 dB, a single-sideband (SSB) noise figure (NF) of 5-14.1
dB, an input third-order intercept point (IIP3) of 6.8dBm and 1-
dB compression point of -1.9dBm between 0.5-10GHz.
Keywords-CMOS; current bleeding; folded; low voltage; mixer.
I. INTRODUCTION
The revolution of portable wireless communications
devices enables individuals around the world access to
information with ease regardless of their physical location. As
these portable devices become part of our everyday lives, the
need for higher performance and lower cost become more and
more important [1]. The wireless phone has evolved following
the trends of low cost, low-power dissipation and small form
factor to meet consumer needs [2]. The tremendous reduction
in size and weight and the increased talk time requires a high
level of integration, low-power consumption and low cost in
the transceiver design.
These demands make CMOS (Complementary Metal-
Oxide-Semiconductor) an attractive technology for
implementation. It is quite beneficial for the low voltage and
low power radio frequency (RF) analog circuits. These
characteristics are especially critical in mobile wireless
communication systems due to the limitation of battery
capacity. A few low-voltage and low-power topologies that
utilized the CMOS technologies have been proposed in [3]-[5]
for the RF mixer circuits. The single stacked or folded
topology is a popular method that can successfully handle low
supply voltages [6], [7]. Another low voltage approach, which
uses bulk-injection switching, suffers from limited gain and
relatively poor noise performance [8], [9].
The main challenge lies in maintaining moderate gain,
noise figure, and linearity at minimum current consumption
across a wide frequency spectrum with the abating supply
voltage. Several techniques have been proposed in order to
increase simultaneously gain and linearity; like current-
bleeding and charge injection. The current-bleeding technique,
firstly proposed in [10], allows improving gain and linearity in
the case of narrow band single balanced mixers. Usually this
technique limited to narrow-band operation.
Here, we propose a novel down-conversion current
bleeding folded mixer featuring ultra low voltage using the
CMOS 0.13-m process parameters. With the folded structure,
this mixer can achieve high performance. Also, Series
Inductive peaking is used for bandwidth extension.
This paper is organized as follows: design considerations of
the low voltage folded mixer is present in Section II. In Section
III, analysis of mixer performance is present. Section IV shows
the simulated results and a performance comparison with
existing CMOS down-conversion mixers of the proposed
mixer. Finally, conclusions are stated in Section V.
II. CIRCUIT DESCRIPTION
The schematic of the proposed mixer is shown in Fig. 1.
The major parts of the mixer are the RF transconductance stage
(M
1
M
4
), the LO switching stage (M
11
M
14
), the IF differential
outputs through resistors R
L1
and R
L2
and current bleeding
circuit. A detailed design description of each block is presented
in this Section.
A. Low Voltage Folded Mixer Design
In this folded structure, the RF stage is moved out from
cascode structure of conventional Gilbert-cell mixer. This
approach offers several advantages over conventional Gilbert
cell mixer. The supply voltage can be reduced and also
provides easy access to adjust the bias current in the
transconductance stage without affecting the current
commuting stage.
A CMOS inverter configuration is used as the
transconductor to amplify the input signals. The RF signal
amplification by the PMOS transistor is a result of current
reuse principle. This is an efficient way to have a high gain and
a low noise figure [6]. The single-ended mixer core is shown in
Fig. 2. The transconductance stage is composed of inverting
buffer M
1
and M
3
. The bias current for the mixer core is
regulated by the current mirror through M
5
and M
6
. The
111
6'th International Symposium on Telecommunications (IST'2012)
978-1-4673-2073-3/12/$31.00 2012 IEEE
Fig. 1. Schematic of the proposed mixer.

transistor M
5
is essentially biased in the
achieve minimum V
dd
due to the smaller vo
the transistor M
5
(V
DS,M5
= 52mV). C
d
is the t
isolator capacitor in order to minimize voltag
For above statement agument, we survey
voltage that can be applied. It is determined
voltage (V
t
) and the overdrive voltages of
and M
3
. The overdrive voltages of M
1
(V
ov
can be calculated using
V
ovdn
=V
rfdcn
V
DSmin
V
t

V
ovdp
= V
dd
V
rfdcp
V
t

where V
rfdcn
and V
rfdcp
are the biasing volta
gates of the transistors M
1
and M
3
. With assu
the minimal supply voltage (V
dd,min
) can be ex
V
dd,min
= V
ovdn
+ V
ovdp
+ 2V
Typical value of V
t
in 0.13-m CMOS is
450mV. From (3), it is clear that the minimum
Fig. 2. Schematic of single-ended mixer core.
triode region to
oltage drop across
transistors biasing
ge source.
y the lowest supply
d by the threshold
the transistors M
1

vdn
) and M
3
(V
ovdp
)
(1)
(2)
age applied at the
uming V
rfdcn
=V
rfdcp
,
xpressed as
V
t
+ V
DSmin
(3)
s in the range of
m supply voltage

must be higher than 0.9V. T
CMOS inverter. By rep
complementary transconductor
V
rfdcn
V
rfdcp
, (3) becomes:
V
dd,min
= V
ovdn
+ V
ovdp
+
Choosing V
rfdcn
to be greater th
We set transistors M
1
and M
3

V
rfdcn
to 0.1V and 0.62V, respe
voltage (0.7V). The transecond
a voltage-to-current converter
the saturation region to ach
transistors of LO switch qua
region and near cut off.
B. Current Bleeding by MOS C
Increasing the bias curren
stage can provide higher amoun
linearity, but a larger LO swi
and voltage headroom issue. T
often adopted to reduce thi
conversion gain, linearity
simultaneously [12], [13]. T
technique is that different curre
and the switching stage. In this
optimized separately, which,
performance improvement in
mixers.
For the proposed circuit sh
generating bias currents is to u
circuit, the PMOS mirror i
transconductor stage. The NM

This is the disadvantage of the
placing C
d
an ac-coupled
r is obtained [6]. With assuming
2V
t
+ V
DSmin
+ V
rfdcp
V
rfdcn
(4)
han V
rfdcp
, V
dd,min
can be reduced.
DC biasing voltage, V
rfdcp
and
ectively to achive lowest supply
ductance transistors performs as
which is essentially biased in
hieve high performance. The
ad are biased in the saturation
Current Mirrors
nt of the RF transconductance
nts of conversion gain and better
itching current causes 1/f noise
The current bleeding technique is
is issue by further increasing
and minimize noise figure,
The main characteristic of the
ents appear at the transconductor
s way, each of the stages may be
in turn, results in an overall
comparison with conventional
hown in Fig. 1, the strategy for
use MOS current mirrors. In this
s used to inject current into
MOS mirror (M
5
, M
6
) under the
112
RF transistors control the total bias current
The transistor M
6
is a diode connected.
The four transistors in the top of the RF
used for current bleeding. The drain current
and M
10
are 0.4 time the total bias current co
mirrors which inject into transconductor sta
of bias parameter compensate by transistors
fixed common mode feedback circuit (CMF
the current drawn by transistor M
9
and M
transconductance stage keeps large while
control of the DC currents for the switchin
that of the RF stage. The transistors w
regulated to achive different currents through
C. Resonated Inductors
By using the current injection te
transconductance stage, The parasitic capacit
of the switching stage becomes larger, w
effects on mixer bandwidth [14]. The b
extensioned by placing two series inductor
between the RF input stage and the swit
analysis of the resonated inductors can be ex
3. When one of the switches is on, th
approximated by a voltage-control current
the total parasitic capacitance at the source
stage. The series resonated inductors chang
and falling time of the parasitic capacitance
resistor from the capacitor. Which means al
into charging the capacitor. Therefore, the ri
and hence, the bandwidth enhancement.
technique provide high impedance so as
conversion gain and linearity.
III. PERFORMANCE ANALYSIS OF T
In general, conversion gain, noise figure
the most important parameters to deter
performance. However, there are always tr
these parameters to meet certain specifica
applications. This makes it difficult to com
performance between different mixers. In
frequency band has been pushed to a higher f
recent wireless communication system. T
frequency should be considered as a contrib
mixer performance. A detailed explanation o
is given below focuses on conversion gain,
to-port isolations.
Fig. 3. Resonated inductors network analysis.
of this mixer core.
F stage M
7
-M
10
are
ts of transistors M
9

ontroled by NMOS
age. Any variation
s M
6
and M
7
of the
FB) via controlling
M
10
. The current in
e bleeding allows
ng transistors from
width have to be
h the transistors.
echnique in the
tance at the source
which significantly
bandwidth can be
rs (0.22 nH each)
tching stage. The
xplained with Fig.
he mixer can be
source. C
out
is the
e of the switching
ges the rising time
by decoupling the
ll the current goes
ise time decreases,
Furthermore, the
s to improve the
THE MIXER
e and linearity are
rmine the mixer
rade offs between
ations in different
mpare the overall
n addition, radio
frequency range in
Therefore, the RF
bution factor to the
f the circuit design
linearity and port-

A. Conversion Gain
Conversion gain is a key pa
mixers, since the signal rec
amplification. The small signa
Fig. 4. It is composed of a CM
an efficient way to max
g
mRF
=g
mn
+g
mp
. Assuming that
wave, the voltage gain of the p
as
CG=
2

(g
mn
+g
m
where g
mn
is the transconduct
transconductance of M
3
and M
From this expression it can
depends on transconductance o
R
L
. Therefore, higher gain can
value of the load or the t
Increasing the bias current o
However, the bias current thro
minimized to suppress DC off
This can be achieved using f
bleeding technique. The small
also allows the usage of large l
increase the CG without con
limited voltage headroom. It is
also leads to the reduction of
stage.
B. Linearity
As a evaluation of the de
mixing behaviour, one can plo
intermodulation output as a fun
3rd order intercept point is th
these two curves, can be expres
IIP3 =
where K= 2C
ox
w I is a pr
carrier mobility , the gate-- -ox
the width W and the length L
current of the RF input
demonstrates that linearity a
increases, which naturally cau
power. Another parameter d
compression point. It is the va
Fig. 4. Small-signal equivalent circuit o
arameter in down- conversion
ceived by the antenna needs
al equivalent circuit is shown in
MOS-inverter amplifier which is
ximize the transconductance
LO voltage is an ideal square
roposed mixer can be expressed
mp
)|R
L
| r
on
| r
op
] (5)
tance of M
1
and M
2
, g
mp
is the
M
4
and R
L
is the output resistor.
be seen that conversion gain
of RF stage and the load resistor
n be provided if the achievable
transconductance is increased.
of the RF stage enhances g
mn
.
ough the LO switches should be
fset, thermal and 1/f noise [11].
folded topology and the current
bias current in the LO switches
load resistances (R
L
= 450 ) to
nsuming large drop from the
s found that the increase of gm1
f noise from the transconductor
egree of departure from linear
ot the desired output and the 3rd
nction of the input RF level. The
he extrapolated intersection of
ssed as follows [15]:
4 _
2 I
DC,RF
3 K
RF
(6)
rocess parameter including the
xide capacitance C
ox
, as well as
of a transistor. I
DS,RF
is the bias
stage. The above equation
also increases as bias current
use an increase in consumed
denoting linearity is the 1dB
alue of the RF signal at which a

of the CMOS-inverter amplifier.
113
calibrated departure from the ideal linear c
1dB compression point is an estimate of the
can be processed by the receiver, and hen
bound on the dynamic range of the mixer.
C. Port to Port Isolation
Isolation represents the amount of Le
through between the mixer ports. It is gen
minimize interaction among the RF, IF
especially at the high operating frequenci
Since the LO signal power is quite large co
signal power, any LO leakage to the mix
subsequently to the stages preceding it (L
deteriorate the overall receiver performance
RF isolation plays a significant role in mixe
feed through to the RF port depends on ca
between the LO and the RF ports. Balanced
switching will help greatly cancel out any
from the LO+ and LO- inputs. The LO to IF
significant matter since the LO and IF frequ
in down conversion. The values of the port-to
presented in section IV.
IV. SIMULATION RESULT
The presented mixer is simulated using
process model by an Agilent Advanced Desi
tool. The mixer is designed to operate betw
with a local oscillator (LO) power of
simulation results, the IF is always kept at a
while the RF and LO frequencies are being
with the LO being 10 MHz lower than the R
gain of the mixer is simulated across the
ranging from 0.5 to 10 GHz. The input RF p
-40 dBm. Fig. 5 shows the simulated resu
includes the simulated result without the p
The importance of the peaking inductors can
this plot, where the conversion gain is increa
flatness when the resonated inductors a
simulated gain varies from 8.9 dB at 0.5 GH
GHz. Fig. 6 shows the simulated single-side
the mixer for RF frequency of 5 GHz. Th
reveals a minimum value of 5 dB and is be
simulated third-order inter modulation of th
in Fig. 7, which features a simulated input
and the simulated input 1-dB compression p
(Fig. 8). The proposed design for the mixe
degree of LO to IF isolation and is facilit
requirements at the output. The isolations of
to RF are both more than 64dB, but the isola
more than 28dB in Fig. 9.
V. CONCLUSION
Due to the importance of the mixers in th
paper, a broadband low voltage down conv
designed and simulated using a 0.13-m
model. A folded topology with a current b
was proposed to achieve the low-voltage a
good linearity performance with competitive
curve occurs. The
largest signal that
nce sets the upper
eakage or Feed
erally desirable to
F and LO ports,
ies of the mixer.
ompared to the RF
xer input port and
LNA, filter), may
e. Thus the LO to
er design. The LO
apacitive coupling
d non-overlapping
LO feed through
F isolation is a less
uency are far apart
o-port isolation are
TS
0.13-m CMOS
ign System (ADS)
ween 0.5-- -10 GHz
5 dBm. For all
constant 10 MHz,
g changed together
RF. The conversion
e input frequency
power was kept at
ults. This plot also
peaking inductors.
n be clearly seen in
ased and more gain
are adopted. The
Hz to 6.9 dB at 10
eband (SSB) NF of
e SSB NF at 0.7V
elow 14.1dB. The
he mixer is plotted
t IIP3 of 6.8 dBm
point of -1.9 dBm
er provides a high
tating the filtering
f LO to IF and LO
ation of RF to IF is
he receivers, in this
version mixer was
m CMOS process
bleeding technique
and high gain and
e noise figure and
Fig. 5. Simulated conversion gain agai
Fig. 6. Simulated noise figure against R

Fig. 7 Simulated IIP3 whit a RF input
voltage of 0.7V.

inst RF frequency.

RF frequency.

frequency spacing of 10 MHz and a DC
114

Fig. 8. Simulated 1-dB compression point.

Fig. 9. simulated LO-RF and RF-IF port and LO-IF isolation versus RF

Table 1. Comparisons of previously reported mixers and this work
Reference Process Approach RF frequency,
GHz
VDD,
V
NF,
dB
Gain,
dB
IIP3,
dBm
P1dB,
dBm
[6]
0.18 m CMOS Folded-switching 2.4 1.8 12.9 15.7 1
__
[7]
0.18 m CMOS Folded cascode 1.58 1.2 12 (DSB) 14.5
__
-13
[8]
0.18 m CMOS Bulk-injection 0.5-7.5 0.77 15 5.7 -5.7
__
[14]
0.13m CMOS Low Noise Mixer 1-5.5 1.5 3.9 (DSB) 17.5 0.84 -10.5
[15]
65 nm CMOS Folded topology 1-10.5 1 7.6 (DSB) 12.8
__
-10.4
This work 0.13 m CMOS Folded current
bleeding
0.5-10 0.7 5-14.1 (SSB) 6.9-8.9 6.8 -1.9

good port-to-port isolations, This trade off with higher power
consumption. This topology allows the designer to easily
adjust the bias current of the input transistors while
maintaining the bias currents in other parts of the circuit. The
models for conversion gain and IIP3 used in this methodology
were discussed. A PMOS LO switches are folded with respect
to the gm-stage as a current steering device. Peaking inductors
are also used to increase the bandwidth and other performance
of the mixer simultaneously.
By optimizing device size and bias conditions of the
different blocks, it was possible to achieve a good operation in
the desired band. In order to evaluate the performance of the
proposed mixer, the previously reported CMOS mixers and
this work are compared in Table 1. As the simulation results
illustrated the total mixer performance, all these techniques
caused a better performance for the proposed mixer in terms
of the linearity, conversion gain, port to port isolation and
noise figure. The disadvantage of the folded mixer with
current bleeding is bad power supply rejection ratio. The
circuit consumes 24mW under 0.7V supply voltage.
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