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Features

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Fully Integrated Low IF Receiver Fully Integrated GFSK Modulator for 72, 144, 288, 576 and 1152 Kbits/s High Sensitivity of Typically –93 dBm Due to Integrated LNA High Output Power of Typically +4 dBm Multi-channel Operation – 95 Channels – Support Frequency Hopping (ETSI) and Digital Modulation (FCC) Supply-voltage Range 2.9V to 3.6V (Unregulated) Auxiliary Voltage Regulator on Chip (3.2V to 4.6V) Low Current Consumption Few Low-cost External Components Integrated Ramp-signal Generator and Power Control for an Additional Power Amplifier Low Profile Lead-free Plastic Package QFN32 (5 mm × 5 mm × 0.9 mm) RoHs Compliant

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Low-IF 2.4-GHz ISM Transceiver ATR2406

Applications
• • • • • • •
High-tech Multi-user Toys Wireless Game Controllers Telemetry Wireless Audio/Video Electronic Point of Sales Wireless Head Set FCC CFR47, Part 15, ETSI EN 300 328, EN 300 440 and ARIB STD-T-66 Compliant Radio Links

1. Description
The ATR2406 is a single chip RF transceiver intended for applications in the 2.4-GHz ISM band. The QFN32-packaged IC is a complete transceiver including image rejection mixer, low IF filter, FM demodulator, RSSI, TX preamplifier, power-ramping generator for external power amplifier, integrated synthesizer, and a fully integrated VCO and TX filter. No mechanical adjustment is necessary in production. The RF transceiver offers a clock recovery function on-chip.

4779M–ISM–02/07

Figure 1-1.

Block Diagram
REG_DEC VREG REG_CTRL VS_REG IREF VS_SYN

VREG_VCO

VCO REG

AUX REG

AUX REG

VS_IFD VS_IFA VS_RX/TX LIMITER RSSI DEMOD RX_DATA

LNA RX_IN

IR-Mixer

BP

RSSI PA TX_OUT Divider by 2 VCO BUS CLOCK DATA ENABLE TEST1 TEST2 RAMP_OUT RAMP GEN PLL GAUSSIAN FILTER PU_REG CTRL LOGIC PU_TRX RX_ON TX_ON nOLE

CP

REF_CLK TX_DATA

VTUNE

2. Pin Configuration
Figure 2-1. Pinning QFN32 - 5 × 5
ENABLE DATA CLOCK TX_DATA RX_DATA PU_TRX nOLE TX_ON PU_REG REF_CLK RSSI VS_IFD VS_IFA RX-CLOCK IC IREF

1 2 3 4 5 6 7 8

32 31 30 29 28 27 26 25 24 23 22 ATR2406 21 20 19 18 17 9 10 11 12 13 14 15 16
REG_CTRL VREG VS_REG REG_DEC VREG_VCO VTUNE CP VS_SYN

RX_ON IC IC RAMP_OUT TX_OUT RX_IN1 RX_IN2 VS_TRX

2

ATR2406
4779M–ISM–02/07

do not connect on PCB Internally connected. if RX mode with clock recovery is active Internally connected. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Paddle Pin Description Symbol PU_REG REF_CLK RSSI VS_IFD VS_IFA RX-CLOCK IC IREF REG_CTRL VREG VS_REG REG_DEC VREG_VCO VTUNE CP VS_SYN VS_TRX RX_IN2 RX_IN1 TX_OUT RAMP_OUT IC IC RX_ON TX_ON nOLE PU_TRX RX_DATA TX_DATA CLOCK DATA ENABLE GND Function Power-up input for auxiliary regulator Reference frequency input Received signal strength indicator output Digital supply voltage Analog supply voltage for IF circuits RX-CLOCK. do not connect on PCB RX control input TX control input Open loop enable input RX/TX/PLL/VCO power-up input RX data output TX data input 3-wire-bus: Clock input 3-wire-bus: Data input 3-wire-bus: Enable input Ground 3 4779M–ISM–02/07 . Connect to VS if internal AUX regulator is not used External resistor for band-gap reference Auxiliary voltage regulator control output Auxiliary voltage regulator output Auxiliary voltage regulator supply voltage Decoupling pin for VCO_REG VCO voltage regulator VCO tuning voltage input Charge-pump output Synchronous supply voltage Transmitter receiver supply voltage Differential receiver input 2 Differential receiver input 1 TX driver amplifier output Ramp generator output for PA power ramping Internally connected.ATR2406 Table 2-1.

the signal is frequency divided by 2 and fed to the internal preamplifier PA. The recovered clock is available at pin 6. The advantage is that this recovered clock is synchronous to the clock of the transmitting device (and thus to the transmitted data). the PA. the receiver has a clock recovery function on-chip.728 MHz). The output signal is frequency divided to supply the desired frequency to the TX_DRIVER.5 Power Supply An integrated band-gap–stabilized voltage regulator for use with an external low-cost PNP transistor is implemented. Data slicing is handled internally. which significantly reduces the load of the processing microcontroller. 3. and to be used by the PC for the phase detector (PD) (fPD = 1. The falling edge of the clock is the optimal sampling position for the RX_Data signal. the 0/90 degree phase shifter for the IR_MIXER. This preamplifier supplies typically +4 dBm output power at TX_OUT. so at this event the data must be sampled by the microcontroller.1 Receiver The RF signal at RF_IN is differentially fed through the LNA to the image rejection mixer IR_MIXER. No tuning is required.4 Synthesizer The IR_MIXER. The limiting IF_AMP with an integrated RSSI function feeds the signal to the digital demodulator DEMOD. 4 ATR2406 4779M–ISM–02/07 . After modulation. is integrated. The IF frequency is 864 kHz. Multiple power-down and current saving modes are provided. A ramp-signal generator RAMP_GEN.3. 3. driving the integrated low-IF band-pass filter. and the programmable counter (PC) are driven by the fully integrated VCO. Open loop modulation is supported. 3. providing a ramp signal at RAMP_OUT for the external power amplifier. 3. Functional Description 3. using on-chip inductors and varactors. The slope of the ramp signal is controlled internally so that spurious requirements are fulfilled.2 Clock Recovery For a 1152-kBit/s data rate. The receiver includes a clock recovery circuit which regenerates the clock out of the received data.3 Transmitter The transmit data at TX_DATA is filtered by an integrated Gaussian filter (GF) and fed to the fully integrated VCO operating at twice the output frequency.

6 VS +125 +10 TBD TBD Unit V V V °C dBm V V Electrostatic sensitive device.3 –40 Max. +4. Observe precautions for handling. Parameters Supply voltage auxiliary regulator Supply voltage Control voltages Storage temperature Input RF level ESD protection Symbol VS VS Vcontr Tstg PRF VESD_ana VESD_dig Min. –0.2 –10 2400 Max.3 –0.6 4.7 +3. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied.6 +60 2483 Unit V V °C MHz 5 4779M–ISM–02/07 . Operating Range Parameters Supply voltage Auxiliary regulator supply voltage Temperature ambient Input frequency range Symbol VS VS_BATT Tamb fRX Min. 5.ATR2406 4. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. 2. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.3 –0. 3.9 3.

4 3.9 3. 2. ”Appendix: Current Calculations for a Remote Control” on page 20 With AUX regulator PU_TRX = 0.2 3 3. balun. Max.6.0 2.2 4.4 Parameters Supply Supply voltage Supply voltage RX supply current TX supply current Battery lifetime of a remote control application using an AVR® Supply current in power-down mode Supply current in power-down mode Voltage Regulator AUX regulator VCO regulator Transmitter Part TX data rate Output power TX data filter clock Frequency deviation Frequency deviation scaling(3) 9 taps in filter To be tuned by GFCS bits GFFM = GFFM_nom × GFCS (Refer to bus protocol D9 to D11) With standard loop filter and slot length of 1400 µs (Refer to the application note “ATR2406 Loop Filter and Data Rates”) BW = 100 kHz(1) PTX fTXFCLK GFFM_nom GFCS 60 72/144/288/576/1152 4 10.9% duty cycle 6 ATR2406 4779M–ISM–02/07 .1 4. Conducted measured. Typ.1 3.1 5 5 1.6 V V mA µA mA µA Test Conditions Symbol Min.6V with AUX regulator.8 – 1. For further information refer to the application notes.2 1.6 1.4 Notes: TX_ON = low Refer to bus protocol D12 to D13 Vmin Vmax tr tf ® 0. PU_REG = 0 IS IS <1 <1 µA µA VS VS IS IS IS IS 3.9 GHz 5.6 3. Faster timing can be achieved by modification of the loop filter. Electrical Characteristics VS = 3. The Gaussian filter control setting (GFCS) is used to compensate production tolerances by tuning the modulation deviation in production to the nominal value of 400 kHz.2 3.1 1.1 2.824 ±400 130 kBits/s dBm MHz kHz % VREG VREG_VCO 3. 4.368/13. 3.8 BW = 100 kHz(1) 4 4. Measured and guaranteed only on the Atmel evaluation board.7 V V With AUX regulator Without AUX regulator CW mode (peak current) Burst mode at 10 Kbits/s(4) CW mode (peak current) Burst mode at 10 Kbits/s(4) See Section 10.3 3.3 1.2 2.2 –57 –57 –57 –57 kHz dBm dBm dBm dBm dBm V 3. including microstrip filter. Timing is determined by external loop filter characteristics. and Smart Radio Frequency (Smart RF) firmware. unless otherwise specified No.3 4.5 3.0 57 625 42 500 4.6 3. Pin 21 Minimum output voltage Maximum output voltage Rise time Fall time ∆fo (drift) ±40 –41.7 2 2.7 1.6 3.5 1. PU_REG = 0 Without AUX regulator PU_TRX = 0. 1 1. Tamb = 25°C.15 – 5.9 V µs µs 1. Unit 1.75 GHz 1.7 Frequency drift Harmonics Spurious emissions 30 – 1000 MHz 1 – 12.3 GHz Ramp Generator. Burst mode with 0.

1 V V V RSSI output voltage.5 MHz V MHz/V 1. Conducted measured. wanted at –76 dBm. wanted at –83 dBm at 2.7 Ri (N – 2) 30 dBc 5. Timing is determined by external loop filter characteristics. For further information refer to the application notes.9% duty cycle 7 4779M–ISM–02/07 .8 5. 170 + j0 –93 Max.11 30 MHz to 2300 MHz 2600 MHz to 6 GHz 6 6. Tamb = 25°C.1 5. Measured and guaranteed only on the Atmel® evaluation board. wanted at –76 dBm. balun.3 Notes: RSSI Part Maximum RSSI output voltage Blfar 57 dBc Under high RX input signal level VRSSImax VRSSI 2.728 MHz Bi-adjacent channel rejection ±3.3 5. adjacent level referred to wanted channel level(1) BER < 10-3.2 5. 4.1 6. wanted at –76 dBm. wanted at -83 dBm.9 0.1 7.2 7 7. 5 5.5 5.456 MHz Rejection with ≥ 3 channels separation ≥ ±5.45 GHz(1) BER < 10-3.5 240 2483 VCC – 0.6V with AUX regulator.45 GHz(1) BER < 10-3.ATR2406 6.2 7. Typ. unless otherwise specified No. Burst mode with 0. Faster timing can be achieved by modification of the loop filter. including microstrip filter.1 1. wanted at –83 dBm at 2. Unit Ω dBm dBm dBc dBc dBc IIP3 IM3 RCO Ri (N – 1) 32 –11 14 –15 5. n ≥ 3 adjacent level referred to wanted channel level(1) BER < 10-3.4 5. and Smart Radio Frequency (Smart RF) firmware. 2.128 MHz Out of band rejection > 6 MHz BER < 10-3.6 Parameters Receiver Part RX input impedance Sensitivity Third order input intercept point Intermodulation rejection Co-channel rejection Adjacent channel rejection ±1. The Gaussian filter control setting (GFCS) is used to compensate production tolerances by tuning the modulation deviation in production to the nominal value of 400 kHz. wanted at –76 dBm(1) BER < 10 . wanted at –83 dBm at 2.10 2300 MHz to 2394 MHz 2506 MHz to 2600 GHz Out of band rejection 5. monotonic With –33 dBm at RF input over range –96 dBm to –36 dBm With –96 dBm at RF input VCO Oscillator frequency defined at TX output Frequency control voltage range VCO tuning input gain defined at TX output Over full temperature range(1) 2400 VVTUNE GVCO 0. Electrical Characteristics (Continued) VS = 3.45 GHz(1) -3 Test Conditions Differential At input for BER ≤ 10-3 at 1152 kBits/s(1) Symbol Zin Min. bi-adjacent level referred to wanted channel level(1) BER < 10-3.9 Ri (n ≥ 3) Bldf>6MHz Blnear 40 38 47 dBc dBc dBc Out of band rejection 5. level of interferers in channels N + 2 and N + 4(1) BER < 10-3. 3.

and Smart Radio Frequency (Smart RF) firmware.1 +5 10 1000 mA pA µs µs µs µs µs µs µs V V V V µA MHz Reference clock stable Reference clock stable Reference clock stable Reference clock stable Reference clock stable Reference clock stable Reference clock stable Logic 1 Logic 0 Logic 1 Logic 0 Logic 1 or logic 0 Interface Logic Input and Output Signal Levels. For further information refer to the application notes.3 ±2 ±100 200 200 200 250 200 3 200 3. Faster timing can be achieved by modification of the loop filter.4 LOW-level output voltage 12.1 Charge-pump output current 10.1 HIGH-level input voltage 12.7 PLL settling time 12 12.2 Leakage current 11 Timing Conditions 11.1 +0. Pin DATA.2 Receive to transmit time 11.4 8. Tamb = 25°C.3 Channel switch time 11. Burst mode with 0. 8 8. Electrical Characteristics (Continued) VS = 3. Timing is determined by external loop filter characteristics. Typ. balun.1 Transmit to receive time 11. ENABLE 1.6.2 LOW-level input voltage 12. Measured and guaranteed only on the Atmel® evaluation board.1 8.3 8. including microstrip filter.2 8.824 Max. 10.368 13. Unit MHz MHz REF_CLK REF_CLK SPSC SMC SSC 0 500 1000 32/33 86/87/88/89 31 mVPP - fPD 1728 kHz 10. The Gaussian filter control setting (GFCS) is used to compensate production tolerances by tuning the modulation deviation in production to the nominal value of 400 kHz.1 10 Parameters Synthesizer External reference input frequency Sinusoidal input signal level (peak-to-peak value) Scaling factor prescaler Scaling factor main counter Scaling factor swallow counter Phase Detector Phase detector comparison frequency Charge-pump Output VCP = 1/2 VCC VCP = 1/2 VCC (1)(2) Test Conditions D7 = 0 D7 = 1 AC-coupled sine wave Symbol Min. 4. 2.5 9 9.9% duty cycle 8 ATR2406 4779M–ISM–02/07 . unless otherwise specified No. 3.3 HIGH-level output voltage 12.4 –0.5 Power down to receive 11.4 Power down to transmit 11.4 3. Conducted measured.6 3-wire bus clock frequency Notes: ICP IL TX → RX time RX → TX time CS time PD → TR time PD → RX time PRR time PLL set time VIH VIL VOH VOL Ibias fCLKmax 0 –5 1.6V with AUX regulator. CLOCK.6 Programming register 11.5 Input bias current 12.

PLL Principle Programable counter PC ".Swallow counter SC fVCO = 1728 kHz × (SMC × 32 + SSC) External loop filter Phase frequency detector PD fPD = 1728 kHz PA driver Charge pump VCO Divider by 2 Mixer Gaussian filter GF Reference counter RC REF_CLK 10.368 MHz 13.ATR2406 7.Main counter MC ".824 MHz D7 0 1 PLL reference Frequency REF_CLK Baseband controller TXDAT 9 4779M–ISM–02/07 . PLL Principle Figure 7-1.

... 2482.272 fVCO / MHz divided by 2 2401.408 2482. 2873 2874 TX ..4V 1.35V 1. 24 25 28 29 ..920 .. otherwise it can be programmed 0 or 1.784 .920 .75V The VRAMP voltage is used to control the output power of an external power amplifier. 89 89 86 86 .920 2402....056 2401.. 2872 2873 2780 2781 .. Since the ATR2406 supports wideband modulation with 400-kHz deviation. 10 ATR2406 4779M–ISM–02/07 .. Table 7-1.. 25 26 N 2779 2780 .272 2483. 2481. There are 95 channels available. 2481.Table 7-1 shows the LO frequencies for RX and TX in the 2..056 2401.136 SMC 86 86 . Output Power Settings with Bits D12 .. The voltage ramp is started with the TX_ON signal. every second channel can be used without overlap in the spectrum.. These bits are only relevant in TX mode. C93 C94 7.920 . MSB Data bits D15 0 D14 1 D13 PA D12 D11 D10 GFCS D9 D8 1 D7 RC D6 MC D5 D4 D3 D2 SC D1 LSB D0 Note: D12 and D13 are only relevant if ramping generator in conjunction with external PA is used.272 2401. C93 C94 C0 C1 RX 864 .1 TX Register Setting The following 16-bit word has to be programmed for TX.056 2401..D13 PA (Output Power Settings) D13 0 0 1 1 D12 0 1 0 1 RAMP_OUT (Pin 21) 1...... Table 7-2. Mode LO Frequencies fIF / kHz Channel C0 C1 fANT / MHz 2401..408 2482.272 2401.3V 1.4-GHz ISM band..408 2482. 2481. 89 89 SSC 27 28 .

Table 7-4 on page 12 and Table 7-5 on page 12. Formula for calculating the frequency: TX frequency: fANT = 864 kHz × (32 × SMC + SSC) RX frequency: fANT = 864 kHz × (32 × SMC + SSC – 1) Table 7-3.4 RX Register Setting with Internal Clock Recovery Recommended for 1.ATR2406 7.2 RX Register Setting There are two RX settings possible.152-Mbit/s data rate. MSB Data bits D24 1 D23 0 D22 1 D21 0 D20 0 D19 0 D18 0 D17 0 D16 0 LSB Data bits D15 0 D14 0 D13 X D12 X D11 X D10 X D9 X D8 0 D7 RC D6 MC D5 D4 D3 D2 SC D1 D0 Note: X values are not relevant and can be set to 0 or 1. 7. The falling edge of the recovered clock signal samples the data signal.368 MHz 13.824 MHz 11 4779M–ISM–02/07 . an internal clock recovery function is implemented. The output pin of the recovered clock is pin 6. PLL Settings of the Reference Counter Bit D7 RC (Reference Counter) D7 0 1 CLK Reference 10. 7. MSB Data bits D15 0 D14 1 D13 X D12 X D11 X D10 X D9 X D8 0 D7 RC D6 MC D5 D4 D3 D2 SC D1 LSB D0 Note: X values are not relevant and can be set to 0 or 1.5 PLL Settings RC. 7.3 Register Setting Without Clock Recovery Must be used for data rates below 1.152 Mbits/s. For a data rate of 1152 kBits/s. MC and SC bits control the synthesizer frequency as shown in Table 7-3.

.6 GFCS Adjustment The Gaussian filter control setting (GFCS) is used to compensate for production tolerances by tuning the modulation deviation in production to the nominal value of 400 kHz. PLL Settings of the Main Counter Bits D5 to D6 MC (Main Counter) D6 0 0 1 1 D5 0 1 0 1 SMC 86 87 88 89 Table 7-5...D11 GFCS D11 0 0 0 0 1 1 1 1 D10 0 0 1 1 0 0 1 1 D9 0 1 0 1 0 1 0 1 GFCS 60% 70% 80% 90% 100% 110% 120% 130% 12 ATR2406 4779M–ISM–02/07 . These bits are only relevant in TX mode.. 29 30 31 7... PLL Settings of the Swallow Counter Bits D0 to D4 SC (Swallow Counter) D4 0 0 0 ... GFCS Adjustment of Bits D9 . 1 1 1 D3 0 0 0 . Table 7-6. 1 0 1 SSC 0 1 2 .Table 7-4.... 0 1 1 D0 0 1 0 .. 1 1 1 D2 0 0 0 . 1 1 1 D1 0 0 1 .

ATR2406 7. DATA and ENABLE). starting with the MSBit.8 Serial Programming Bus The transceiver is programmed by the SPI (CLOCK. 7. After setting the enable signal to low. the data is transferred bit by bit into the shift register on the rising edge of the clock signal. Additional leading bits are ignored and there is no check made of how many clock pulses arrived during enable low. Description Clock period 3-wire Bus Protocol Table Symbol TPER TS TH TC TL TEC TT Minimum Value 100 20 20 60 100 0 250 Unit ns ns ns ns ns ns ns Set time data to clock Hold time data to clock Clock pulse width Set time enable to clock Hold time enable to data Time between two protocols 13 4779M–ISM–02/07 . the programmed information is active.9 3-wire Bus Timing 3-wire Bus Protocol Timing Diagram DATA CLOCK ENABLE TPER TL TS TC TH Figure 7-2. TEC TT Table 7-8. Starts RAMP SIGNAL at RAMP_OUT Disables open loop mode of the PLL Signal PU_REG PU_TRX RX_ON TX_ON nOLE 7. IR MIXER Activates TX circuits: PA. Control Signals and Functions Functions Activates AUX voltage regulator and the VCO voltage regulator supplying the complete transceiver Activates RX/TX blocks Activates RX circuits: DEMOD. RAMP GEN. The programming of the transceiver is done by a 16-bit or 25-bit data word (for the RX clock recovery mode).7 Control Signals The various transceiver functions are activated by the following control signals. When the enable signal has returned to high. IF AMP. A timing proposal is shown in Figure 7-3 on page 14 Table 7-7.

Keep input signals on low level during power-down state of TRX 4779M–ISM–02/07 .Figure 7-3. 3W_ENA Pin 32 nOLE Pin 26 REF_CLK > 50 µs Signals to TRX (Input) Signals from TRX (Output) 14 C2 Programming Active RX-slot Programming Active TX-slot Power-down C3 C4 C1 C2 C3 C5 C1 Power-down optional Power-up optional > 40 µs > 50 µs C1 MODE ATR2406 Data Pin Name Power-down Power-up PU_REG Pin 1 PU_TRX Pin 27 > 40 µs TX_DATA Pin 29 Preamble (1-0-1-0) Example TX and RX Timing Diagram 3W_CLK Pin 30 16/25 bits > 200 µs 16 bits > 200 µs 3W_DATA Pin 31 REF_CLK Pin 2 REF_CLK RX_ON Pin 24 TX_ON Pin 25 Data RX_DATA Pin 28 valid signal VS 0V VS 0V RSSI Pin 3 RAMP_OUT Pin 21 connected to RAMP_IN of optional PA Note: 1.

Typical RSSI Value versus Input Power 2. this is just the PLL (transmit channel) and the deviation (Gaussian filter). which is the programming state (C3) and the active slot (C4. A typical plot of the RSSI value is shown in Figure 7-4. The reference clock needs to be applied to ATR2406 for at least the time when the PLL is in operation. if the clock recovery is used.0 0.5 0. several internal signals are also derived. At the start of the three-wire programming. this is just the PLL (receive channel) and. This is the receive slot where the transmit burst is received and data as well as recovered clock are available. When the enable signal rises again to high. if one is used). At TX. the Gaussian filter circuitry and TX_DATA sampling. the enable signal is toggled from high to low to enable clocking the data into the internal register. at the AUX regulator. C2 C3 C4 C5 7. PU_REG enables the external AUX regulator transistor including VCO regulator.5 1. the programmed data is latched.5 2. also the bits to enable this option. It is necessary to wait the settling time of 200 µs so that the VCO frequency is stable. it is necessary to wait at least 40 µs until the different supply voltages have settled.10 Received Signal Strength Indication (RSSI) The RSSI is given as an analog voltage at the RSSI pin. Depending on the value of the external capacitors (for example. PU_TRX enables internal blocks like the PLL and the VCO. C5). the signal nOLE toggles to low which enables modulation in open-loop mode. Condition C1 Description of the Conditions/States Description Power down ATR2406 is switched off and the supply current is lower than 1 µA. At RX.0 RSSI Level (V) 1.0 -130 -110 -90 -70 -50 -30 -10 10 RF Level (dBm) 15 4779M–ISM–02/07 . As soon as TX_DATA is applied to ATR2406. Programming The internal register of the ATR2406 is programmed via the three-wire interface. for example. Figure 7-4. The preamble (1-0-1-0 pattern) should start being sent at the start of TX_ON. This is the active transmit slot. Power up ATR2406 is powered up by toggling PU_REG and PU_TRX to high. Out of the reference clock. This is the time point at which the settling of the PLL starts.ATR2406 Table 7-9.

824 MHz XTAL Note: 1. Microcontroller Interfacing with General Purpose MCU. 8. Taitien Specific No. 10 ppm Order at: Taitien Electronic.8.824 MHz. XRFBCC-NANL.: A009-x-B26-3. Pin Connections between Microcontroller and ATR2406 Microcontroller RF-DATA Interface ATR2406 TX_DATA RX_DATA RX-CLOCK ENABLE CLOCK DATA Ctrl_Lines REF_CLK XTAL (1) XTAL_OUT Example with AVR MCU Figure 8-2. AVR_MCU USART TXD RXD XCK Configuration and control ATR2406 RF_DATA TX_DATA RX_DATA R RX-CLOCK GPIO GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 RF_CTRL ENABLE CLOCK DATA nOLE TX_ON RX_ON PU_REG PU_TRX RSSI REF_CLK 13.1 Typical Application Circuit Figure 8-1. SMD 16 ATR2406 4779M–ISM–02/07 . 13. Application Circuit The ATR2406 requires only a few low-cost external components for operation. XTAL: for example. A typical application is shown in Figure 8-3 on page 17.

C21. TX_DATA RX_DATA PU_TRX nOLE TX_ON RX_ON RAMP_OUT VBATT ENABLE DATA CLOCK J24 R1 NC RX-CLOCK RSSI REF_CLK PU_REG C11 18p 32 31 30 29 28 27 26 25 IC2 C9 24 RX_ON TP1 DATA CLOCK ENABLE PU_TRX C6 C7 2p2 2p2 C3 TX_DATA 4 VS_IFD VS_IFA 19 C10 18 17 1p8 RX-CLOCK IC RX_IN2 RX_IN1 5 TX_OUT 20 ATR2406 RAMP_OUT 21 6 7 VREG_VCO VTUNE REG_DEC CP VREG VS_REG VS_SYN GND Application Circuit for ATR2406-DEV-BOARD C24 REG_CTRL 8 IREF VS_TRX µStrip 3 RSSI TP2 IC 22 RX_DATA REF_CLK IC 1p5 9 11 12 13 14 15 10 16 G C16 4p7 R3 62k 1p8 2 23 TX_ON PU_REG nOLE 1 µStrip 4n7 C23 C4 C17 NC 390p C14 100n NC R6 R4 C19 470n C13 C21 C20 22n 2n2 C18 68p 1k0 100n 1k5 VS J2 GND2 GND7 GND8 GND9 GND4 GND5 GND6 GND1 GND3 4779M–ISM–02/07 RFOUT (Ant) Select integrated F-antenna or SMA connector by setting the 0R resistor ANT2 F-antenna ANT ANT GND GND R2 NC C1 J2 SMASI 5p6 µStrip Lowpassfilter J1 J11 VBATT 4µ7 VBATT TX_ON TX_DATA PU_TRX CLOCK RX_ON J4 J5 J6 J7 J8 J9 C15 J12 J13 J14 J15 J16 J17 RSSI J10 R5 REF_CLK J3 1k5 ENABLE DATA nOLE PU_REG RX-CLOCK RX_DATA C12 BC808 µStrip-balun T1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 2 4 6 8 10 12 14 16 18 20 22 24 26 28 VLSI Connector J18 J19 J20 J21 4µ7 C20.Figure 8-3. COG dielectric Slug RAMP J26 IC2P GND ATR2406 17 .

PCB Layout Design Figure 9-1.9. PCB Layout ATR2406-DEV-BOARD 18 ATR2406 4779M–ISM–02/07 .

gold 1.3 nF 68 pF 470 nF 22 nF. optional(1) BC808-40. C10 C4 C5 C6.0 kΩ 1. Optional(2) FR4. chem. pin 7 of the ATR2406 has to be connected to pin 4 or pin 5 to use the integrated F antenna. ≤ 5% ATR2406 Atmel ® ® Part Number Vendor Package 0402 0402 0402 0402 0402 0402 0402 0402 Comment NC B45196H2475M109 Epcos ® 3216 0402 0402 0402 0402/0603 Optional(2) NC NC Murata Murata 0805 0603 0402 0402 0402 0402 0402 0402 MLF32 SOT-23 COG.8 pF 390 pF 4. tand = 0. ≤ 5% 1k5. C7 C9 C11 C12. that is. COG GRM21B5C1H223JA01 2. important for good RF performance COG.7 nF 4.7 µF 1 nF 3. C16 C14 C17 C18 C19 C20 C21 C23 C24 R3 R4 R5 R6 IC2 T1 MSUB Notes: Bill of Materials Value 5.4 at 2.45 GHz.7 pF 2. Part C1 C3. set jumper R2 (0R resistor 0603) Table 9-2. but it is Vishay .02. ≤ 5% 1k0. T = 35 µm.7 pF 62 kΩ 1.5 kΩ ATR2406 BC808-40 FR4 62k.5 pF 18 pF 100 nF 4. H = 500 µm. e_r = 4. any standard type can be used. If no AUX regulator is used. Parts Count Parts Count Bill of Materials Required (Minimal BOM) 14 2 2 – 1 Optional (Depending on Application) 14 4 2 – 2 Capacitors 0402 Capacitors >0402 Resistors 0402 Inductors 0402 Semiconductors 19 4779M–ISM–02/07 . Philips .ATR2406 Table 9-1. then T1 and C16 can be removed and a jumper is needed from the collector to the emitter pad.2 pF 1.2 nF. surface. ≤ 5% 1k5.5 kΩ 1. Not necessary if supplied RefClk level is within specification range 2.6 pF 1. important for good RF performance GRM1885C1H222JA01 Ref_Clk level. Additionally. COG 4. optional(1) Ref_Clk level. C15 C13. important that be “–40”! etc. tin or chem.

02 µAs (charge for receiving the packet) Q10 = (0.005A + 0.152 Kbits/s 42 mA 57 mA 26 mA 5 mA 1. RX to TX.10. an acknowledge will be returned to the handheld device.93 µAs (charge for configuring the ATR2406) Q3 = (0. The power consumption of the base station device is not power-sensitive.057A) × 50 µs = 3.026A) × 5030 µs = 155 µAs (charge up time ATR2406 + AVR internal calculations) Q2 = (0.152 Kbits/s Peak current ATR2406 with synthesizer running Current ATmega88 active Current ATmega88 power down (no WDT) Current ATmega88 power down (+ WDT) Loop settling time of ATR2406 Configuration of ATR2406 Time needed for exchanging a packet at 1.057A) × 210 µs = 13.005A) × 250 µs = 1.93 µAs (charge for configuring the ATR2406) Q7 = (0.25 µA 5 µA 110 µs 30 µs 210 µs Amount of Current Needed to Transmit One Packet: Q1 = (0.057A) × 50 µs = 3. If an external voltage regulator is used. additional power-down current has to be taken into account The base station will periodically scan all the channels of the used subset.005A + 0. The base station will stay on one channel for 2 seconds.026A) × 30 µs = 0. 24 bytes = 240 bits (USART connection) Tpacket_length = 210 µs at 1.)) Q6 = (0. Appendix: Current Calculations for a Remote Control Assumptions: Protocol A data packet consists of 24 bytes.1 µAs (charge for latency before receiving) 20 ATR2406 4779M–ISM–02/07 . etc. as this part of the application is normally mains powered Channel Loop filter Handheld device Base station device Basic Numbers: Peak current ATR2406 in TX at 1.026A) × 60 µs = 1.005A + 0.005A + 0.10 µAs (charge until valid data can be received) Q9 = (0.005A + 0.25 µAs (charge for turn around (TX to RX.026A) × 30 µs = 0.005A + 0. The AVR power-down current is typically 1.005A + 0.25 µA.042A) × 210 µs = 9.86 µAs (charge for settling the loop filter) Q8 = (0.026A) × 110 µs = 3.152 Kbits/s Peak current ATR2406 in RX at 1.87 µAs (charge for transmitting the packet) Q5 = (0.005A + 0. the handheld device will be in power-down mode with the AVR’s watchdog timer disabled.152 Mbits/s The system will use five predefined channels for frequency hopping spread spectrum (FHSS) which gives improved immunity against interferers Loop filter settling time will be 110 µs If not in use. If the base station receives a correct packet.005A + 0.41 µAs (charge for settling the loop filter) Q4 = (0.

21 4779M–ISM–02/07 . as the cycle will be completed without powering up and down the handheld in order to be as power efficient as possible.75 µA Assumed average power-down current is 5 µA.5 times. → Power-down current is the main factor influencing the battery lifetime. the system has to do this up to five times before the packet is acknowledged by the base station. This is 100.47 µAs As the described system is a FHSS system with 5 different channels. some more retries may be required.ATR2406 A successful packet exchange needs the following charge Q = Q1 + Q2 + Q3 + Q4 + Q5 + Q6 + Q7 + Q8 + Q9 + Q10 = 192.031 µA + 4 µA = 4. → Overall power consumption is 8.031 µA and assuming the power-down current of this device is just 4 µA.1 µA It is assumed the system uses a small battery with a capacity of 100 mAh. it is assumed the factor will be 3. → Iactive = 0. therefore.83 years. → Battery lifetime will be around: 12345 hours = 514 days = 1.5 µAs × 3) = 267.03 µA → Battery lifetime will be around 24807 hours = 1033 days = 2.4 years.0 µA 2. The power-up time is included only once. The most important factor is to get the power-down current as low as possible! Example: Assume a system where the handheld is used just 10 times per day.5 µAs If the device will be used 1000 times a day → 3.25 µA 1. The average will be 2.000 µAh.1 µA Average current in active mode: → System Power Down current: Current ATmega88: Current ATR2406: Current VREG (+ ShutDown): 1. → I = 0. In the case of an interfered environment. Average current needed for a packet exchange: 155 µAs + (37.

Pb-free RF module Complete evaluation kit and reference design ATR2406 + ATmega88 MOQ 4000 1 1 12. Ordering Information Extended Type Number ATR2406-PNQG ATR2406-DEV-BOARD ATR2406-DEV-KIT2 Package QFN32 .5x5 – – Remarks Taped and reeled. Package Information 22 ATR2406 4779M–ISM–02/07 .11.

3 mm 0.ATR2406 13.5 mm 23 4779M–ISM–02/07 . Recommenced Footprint/Landing Pattern Table 13-1.2 mm 0.3 mm 1.2 mm 1. Recommended Footprint/Landing Pattern Figure 13-1.1 mm 0. Recommended Footprint/Landing Pattern Signs Sign A B C a b c d e Size 3.2 mm 0.55 mm 0.

14. not to this document. 4779M-ISM-02/07 History • Put datasheet in a new template • Table 9-1 “Bill of Materials” on page 19 changed • Table “Electrical Characteristics” on pages 6 to 8 changed • Section 10 “Appendix: Current Calculations for a Remote Control” on pages 20 to 21 changed • Table “Ordering Information” on page 22 changed • Minor corrections to grammar and style throughout document • Put datasheet in a new template • Table “Electrical Characteristics” on pages 6 to 8 changed • Section 10 “Appendix: Current Calculations for a Remote Control” on pages 20 to 21 added • Ordering Information on page 22 changed 4779L-ISM-08/06 4779K-ISM-06/06 24 ATR2406 4779M–ISM–02/07 . Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned. Revision No.

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