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Genesys Logic, Inc.

GL850G
USB 2.0 Hub Controller Datasheet

Revision 1.23 Jul. 15, 2011

GL850G Datasheet

Copyright
Copyright © 2011 Genesys Logic, Inc. All rights reserved. No part of the materials shall be reproduced in any form or by any means without prior written consent of Genesys Logic, Inc.

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Genesys Logic, Inc. owns and retains of its right, title and interest in and to all materials provided herein. Genesys Logic, Inc. reserves all rights, including, but not limited to, all patent rights, trademarks, copyrights and any other propriety rights. No license is granted hereunder.

Disclaimer
All Materials are provided “as is”. Genesys Logic, Inc. makes no warranties, express, implied or otherwise, regarding their accuracy, merchantability, fitness for any particular purpose, and non-infringement of intellectual property. In no event shall Genesys Logic, Inc. be liable for any damages, including, without limitation, any direct, indirect, consequential, or incidental damages. The materials may contain errors or omissions. Genesys Logic, Inc. may make changes to the materials or to the products described herein at anytime without notice.

Genesys Logic, Inc.
12F., No. 205, Sec. 3, Beixin Rd., Xindian Dist. 231, New Taipei City, Taiwan Tel : (886-2) 8913-1888 Fax : (886-2) 6629-6168 http://www.genesyslogic.com

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GL850G Datasheet

Revision History
Revision 1.00 1.01 1.02 1.03 1.04 Date 05/10/2006 First formal release 08/30/2006 Update DC supply current, table6.6, P.23 11/03/2006 Modify 93C46 configuration, table 5.1, P.19 01/17/2007 Modify table 6.1-maximum ratings, P.21 08/08/2007 Modify table 6.6-DC Supply Current, P.23 Add SSOP 28 package assignment ,Ch3, P.11~14 Add –low/high-enabled power switches, Ch5.2.7, P.23 03/10/2008 Add built-in 5V to 3.3V power regulator, Ch5.2.5, P.21 Modify power on reset description, Ch5.2.1, P.18 Add description of port configuration, Ch5.2.8 and Ch5.2.9, P.23 Add QFN 28pin:  pinout, p.12  pin List, p.13 01/07/2008  pin descriptions, p.14 ~15  package dimension, p.30  ordering information, p.32 02/19/2009 Modify SSOP 28 pin, QFN 28 pinout, pin list, pin description, p.11~15 03/18/2009 Modify electrical characteristics, Ch6, p.26~27 04//15/2009 Modify table 6.6-DC supply current, p.27 04/27/2009 Modify part number of QFN 28, table8.1- ordering information, p.31 Modify pin name SEL48/SEL27 pinout / pin list/ description, p.10, p.13, p.15 04/29/2009 Modify Fosc 12 MHz  0.05% to 12 MHz  50ppm, maximum ratings, table-6.1, p.26 Modify Fosc 12 MHz  50ppm to 12 MHz  0.05%, maximum ratings, table 06/12/2009 6.1, p.26 Modify power on reset diagram, figure 5.3, p.21 08/12/2009 Modify Ch6.4 power consumption, table 6.6 – DC supply current , p.28 Update table 3.4 – pin description, p.16 Update table 6.2 – operating ranges, p.29 09/02/2009 Update table 6.3 – power dissipation, p.29 Update Ch8 order information, p.35 Update Ch2 features, p.9 Add note to table 3.2, p.14 09/22/2009 Add note to table 3.4, p.15 Add note to table 5.2, p.27 Update table 6.3 – power dissipation, p.30 Modify description of reference clock configuration, Ch5.2.10, p.28 03/15/2010 Modify Ch7 Package Dimension, p.32-33 Modify Ch8 Ordering Information, p.35 10/05/2010 Modify table 6.2 – operating ranges, p.29 10/25/2010 Modify Figure 7.3, p.34 Description

1.05

1.06

1.07 1.08 1.09 1.10 1.11

1.12 1.13 1.14

1.15

1.16 1.17 1.18

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31~32 Add 6. .21 1. p. p.29 1. p. p.22 1.5 EEPROM Setting. p.4 RREF I/O type.1 RESET Setting.1.3.36 07/15/2011 Update Table 3.23 04/26/2011 Modify 5. 3.5 AC Characteristics.GL850G Datasheet Modify Ch2 features. p. 16 ©2011 Genesys Logic.28 Update table 6.2. Inc. p.20 1.15. Page 4 . 3.2.33 03/02/2011 Update table 6.All rights reserved.2.23~24.3 – DC characteristics except USB signals.2 – operating ranges.25 12/24/2010 Add 6.6 On-Chip Power Regulator.9 Modify 5. p. 05/11/2011 Modify SSOP28 package dimension information. 3.19 1. p.

.................3 SELF/BUS Power Setting .........2.....................................................1........11 REPEATER/TT Routing Logic..................1.................................3 Pin Descriptions ..............................................................................................9 REPEATER .............1 RESET Setting . 26 5... 20 5............ 21 5..........................................................................................3 FRTIMER ............... 20 5.......2 PLL (Phase Lock Loop) .9 Reference Clock Configuration (Only Available in LQFP48 Package) ............................ 22 5.10 TT (Transaction Translator) ...................................................................... 23 5......................................................... 28 5......................................................................................................... 19 CHAPTER 5 FUNCTION DESCRIPTION.................. ...........1..................................... 12 3........................1......................2 Configuration and I/O Settings ........................................1 USPORT Transceiver........................ 15 3..6 USPORT Logic ........ 20 5............................... 24 5.........................................................7 SIE (Serial Interface Engine)................................................1............................................... 21 5..................1 General Description.................... 26 5..........4 LED Connections ...5 EEPROM Setting..........................7 Port Number Configuration (Only Available in LQFP48 Package)..............2..2........ 10 CHAPTER 3 PIN ASSIGNMENT ................................2 PGANG/SUSPND Setting .................................................................................... 29 ©2011 Genesys Logic........................................................................................1..........GL850G Datasheet Table of Contents CHAPTER 1 GENERAL DESCRIPTION .....................................................1 Pinouts ..........12 DSPORT Logic .................................2....... 20 5.. 28 CHAPTER 6 ELECTRICAL CHARACTERISTICS.................8 Non-removable Port Configuration (Only Available in LQFP48 Package).........1.........13 DSPORT Transceiver................................................................................ 20 5........................................................................................................................................... 20 5. 23 5....................... 27 5................... 12 3...........5 UTMI (USB 2............4 μC .... 21 5................ 9 CHAPTER 2 FEATURES......2............ 20 5............2................................................................. 20 5...................2...................................... Inc..........1.......................................................................................................................................................................................................................................................................1 Maximum Ratings ........1.................. Page 5 .............2.....................2 Pin List...... 27 5............ 16 CHAPTER 4 BLOCK DIAGRAM ...........................................1.........2.................... 22 5......................... 20 5......All rights reserved............1........................ 20 5..... 29 6............................................0 Transceiver Microcell Interface)...............................1..........................................................................................1................................................. 26 5............................................................................................................................................8 Control/Status Register ...6 Power Switch Enable Polarity (Only Available in LQFP48 Package)............................................

........................................6 On-Chip Power Regulator ..................5 AC Characteristics .............................................5.............. Page 6 .....................................GL850G Datasheet 6................................ 30 6...............2 24C02 EEPROM Interface .................................................................................3 DC Characteristics ...............2 Operating Ranges ..................................................................... ......... 34 CHAPTER 7 PACKAGE DIMENSION ......... 29 6......................... 32 6.......................4 Power Consumption ...................................................... 32 6........ 31 6................................ 38 ©2011 Genesys Logic.............................. Inc............................. 33 6..................................................All rights reserved........ 35 CHAPTER 8 ORDERING INFORMATION ...............................1 93C46 EEPROM IF.........................................................................5.................................................................................

................3 ........GL850G 48 Pin LQFP Package.............All rights reserved................... 14 Figure 4.................................................Individual/GANG Mode Setting..................... 36 Figure 7....................................LED Connection ............GL850G SSOP 28 Pin Pinout Diagram ..............3 .............................6 ........... 23 Figure 5...Vin(V5) vs Vout(V33)*...............................GL850G 28 Pin QFN Package............................GL850G Datasheet List of Figures Figure 3. 27 Figure 6..................................Schematics between GL850G and 93C46............................... 34 Figure 7. 22 Figure 5...................................... 23 Figure 5...............GL850G LQFP 48 Pin Pinout Diagram . 26 Figure 5..... 25 Figure 5..................... 13 Figure 3......................................Power on Sequence of GL850G.............................. 12 Figure 3...... Inc..........1 . Page 7 .........Operating in USB 2............................. ......2 ............................2 .........................Operating in USB 1.. 37 ©2011 Genesys Logic...................................0 Scheme ............................................1 Scheme ...2 .................4 .................. 21 Figure 5......................GL850G 28 Pin SSOP Package .......................................5 ...............1 .SELF/BUS Power Setting ..............1 ................................GL850G Block Diagram (Single TT) ................... 26 Figure 5..Timing of PGANG/SUSPEND Strapping........................GL850G QFN 28 Pin Pinout Diagram......... 19 Figure 5.........1 ......................7 ...................................................Power on Reset Diagram.................................8 ....................... 24 Figure 5.......................3 ........................................................1 ........... 35 Figure 7............................................................................................9 ..............

3 .................Maximum Ratings.....................................GL850G Datasheet List of Tables Table 3....DC Supply Current ....................................................................... 29  Table 6..........Ref.......GL850G SSOP 28 Pin List ..4 ............. 29  Table 6..........1 ........ 30  Table 6..............2 ..........................................................................2 ..............8 ........................................... 16  Table 5..............Pin Descriptions....Operating Ranges.................. 15  Table 3.....DC Characteristics of USB Signals under HS Mode ...............................GL850G QFN 28 Pin List .......................................................................All rights reserved................... 38  ©2011 Genesys Logic.................. 32  Table 6.. 27  Table 5....Port Number Configuration...............................................................DC Characteristics except USB Signals ............7 .............AC Characteristics of EEPROM Interface (93C46) ........ 15  Table 3......Ordering Information.2 .................... 30  Table 6......................... Inc... 24  Table 5............. 27  Table 5.................Reset Timing .... 33  Table 8............ 31  Table 6..................................................3 . Clock Configuration..................................................................................................................................................................................4 ......3 ..........................................Configuration by Power Switch Type ................................................................................................. 30  Table 6........................ ..................1 ...................................... 28  Table 6.......AC Characteristics of EEPROM Interface (24C02) ....6 ........................... 15  Table 3........................DC Characteristics of USB Signals under FS/LS Mode .......... Page 8 ................4 ..........5 ......GL850G LQFP 48 Pin List.........................1 .....1 .....

Also.3V to 1. to Chapter 5). The more complicated settings such as PID. *TT (transaction translator) is the main traffic control engine in an USB 2. like docking station. Inc. Please refer the table in the end of this chapter for more detail. GL850G provides multiple advantages to simplify board level design that help achieve lowest BOM (Bill of Material) for system integrator.0 hub solutions worldwide. Genesys Logic also provides GL852G for multiple TT hub solution to target on systems which require higher performance for full/low-speed devices. The GL850G is a full function solution which supports both Individual/Gang power management modes and the two-color (green/amber) status LEDs. therefore no external LDO required. Please refer to GL852G datasheet for more detailed information. embedded system … etc. Page 9 . VID.All rights reserved. GL850G has proven compatibility. lower power consumption figure and better cost structure above all USB2. and number of downstream ports settings are easily achieved by programming the external EEPROM (Ref. GL850G is a single TT hub solution for the cost requirement.0. .GL850G Datasheet CHAPTER 1 GENERAL DESCRIPTION GL850G is Genesys Logic’s advanced version hub solutions which fully comply with Universal Serial Bus Specification Revision 2. GL850G is designed for customers with much flexibility.0 hub to handle the unbalanced traffic speed between the upstream port and the downstream ports. GL850G’s power enable pin supports both high-enable and low-enable power switch that provides better flexibility on component selection. GL850G also support both Individual and Gang modes (4 ports as a group) for power management. ©2011 Genesys Logic. Each downstream port of GL850G supports two-color (green/amber) status LEDs to indicate normal/abnormal status. to Chapter 5) To fully meet the cost/performance requirement.3V and 3. GL850G integrated both 5V to 3. Firmware of GL850G will control its general purpose I/O (GPIO) to access the external EEPROM and then respond to the host the customized PID and VID configured in the external EEPROM. GL850G embeds an 8-bit RISC processor to manipulate the control/status registers and respond to the requests from USB host.. (Ref. Number of downstream ports setting can be configured by IO setting in absence of EEPROM.8V voltage drop regulator into single chip. Default settings in the internal mask ROM is responded to the host without having external EEPROM. GL850 inherits Genesys Logic’s cutting edge technology on cost and power efficient serial interface design.

This is a performance better choice for USB 2.0  Support 4/3/2 downstream ports by I/O pin configuration  Upstream port supports both high-speed (HS) and full-speed (FS) traffic  Downstream ports support HS. 28 pin QFN and 28 pin SSOP (Full Function only available in 48 pin) Page 10                    ©2011 Genesys Logic. FS. Multiple TT provides individual TT control logics for each downstream port. This is the most cost effective solution for TT.GL850G Datasheet CHAPTER 2  FEATURES Compliant to USB Specification Revision 2. Inc. VID by reading external EEPROM  Support downstream port configuration by reading external EEPROM Single Transaction Translator (STT)  Single TT shares the same TT control logics for all downstream port devices. Please refer to GL852G datasheet for more detailed information. 1-byte data payload) Backward compatible to USB specification Revision 1.0 transceiver Built-in upstream 1. .1  On-chip 8-bit micro-processor  RISC-like architecture  USB optimized instruction set  Performance: 6 MIPS @ 12MHz  With 64-byte RAM and 2K mask ROM  Support customized PID.0 (Not available for SSOP 28 package) Support both individual and gang modes of power management and over-current detection for downstream ports (Individual mode is not supported by SSOP 28 package) Power enable pin supports both low/high-enabled power switches. and low-speed (LS) traffic   1 control pipe (endpoint 0. with automatic and manual modes compliant to USB specification Revision 2. Integrate USB 2.3V regulator Low power consumption Improve output drivers with slew-rate control for EMI reduction Internal power-fail detection for ESD recovery Each downstream port supports two-color status indicator.5KΩ pull-up and downstream 15KΩ pull-down Embed serial resister for USB signals Conform to bus power requirements Automatic switching between self-powered and bus-powered modes Support compound-device (non-removable in downstream ports) by I/O pin configuration Configurable non-removable device support Built-in PLL supports external 12 MHz crystal / Oscillator clock input Built-in 5V to 3.0 hub.All rights reserved. 64-byte data payload) and 1 interrupt pipe (endpoint 1. (Power switch is not supported by GL850G-22 SSOP28 package) Optional 27/48 MHz Oscillator clock input (Not available for QFN28 / SSOP28 package) Number of Downstream port can be configured by GPIO without external EEPROM Available package type: 48 pin LQFP. .

Docking of notebook  Gaming console  LCD monitor hub  Any compound device to support USB hub function ©2011 Genesys Logic. Page 11 . Inc.GL850G Datasheet  Applications:  Stand-alone USB hub  PC motherboard USB hub. .All rights reserved.

.1 Pinouts CHAPTER 3 AVDD 2 3 4 5 6 7 8 9 10 11 12 32 31 30 29 28 27 26 25 33 34 DVDD PAMBER3 PGREEN3 PWREN3# OVCUR3# PWREN4# OVCUR4# TEST RESET# SEL48 35 PGREEN2 1 36 PAMBER2 AGND DM0 ©2011 Genesys Logic.All rights reserved.3.GL850G LQFP 48 Pin Pinout Diagram RREF AVDD GL850G Datasheet Page 12 . Inc. DP0 PIN ASSIGNMENT DM1 DP1 AVDD AGND DM2 DP2 Figure 3.1 .

GL850G Datasheet AVDD DM2 DP2 1 2 3 28 27 26 DP1 DM1 DP0 RREF 4 AVDD X1 5 6 7 8 9 25 DM0 24 V33 23 V5 22 PWREN1# 21 OVCUR1# 20 PWREN2# 19 OVCUR2# X2 DM3 DP3 AVDD 10 DM4 11 SSOP .2 . Inc.All rights reserved.GL850G SSOP 28 Pin Pinout Diagram ©2011 Genesys Logic. Page 13 .28 18 PGANG 17 PSELF 16 DVDD 15 GND DP4 12 RESET# 13 TEST/SCL 14 Figure 3. .

AVDD DM0 DP0 DM1 DP1 DP2 7 15 DM4 DP4 Page 14 . .GL850G QFN 28 Pin Pinout Diagram ©2011 Genesys Logic. Inc.All rights reserved.GL850G Datasheet OVCUR3# OVCUR4# TEST/SCL RESET# DVDD 18 17 16 6 DM2 21 20 19 1 2 3 4 5 Figure 3.3 .

1 .All rights reserved. Page 15 .2 Pin List Table 3.GL850G SSOP 28 Pin List Pin# 1 2 3 4 5 6 7 Pin Name Type Pin# AVDD DM2 DP2 RREF AVDD X1 X2 P B B A P I O 8 9 Pin Name Type Pin# DM3 DP3 B B P B B I/B Pin Name Type Pin# P P B O Pin Name Type O P P B B B B 15 GND 16 DVDD 17 PSELF 18 PGANG 19 OVCUR2# 22 PWREN1# 23 V5 25 DM0 27 DM1 10 AVDD 11 DM4 12 DP4 13 RESET# 14 TEST/SCL I_5V 24 V33 I_5V 26 DP0 I_5V 20 PWREN2#* 21 OVCUR1#* I_5V 28 DP1 * Power switch is not supported in GL850G-22 version.GL850G QFN 28 Pin List Pin# 1 2 3 4 5 6 7 Pin Name Type Pin# DM0 DP0 DM1 DP1 AVDD DM2 DP2 B B B B P B B 8 9 Pin Name Type Pin# RREF AVDD A P I I B B P Pin Name Type Pin# B B I/B Pin Name Type I_5V B I_5V I_5V B P P 15 DM4 16 DP4 17 RESET# 18 TEST/SCL 19 OVCUR4# 20 OVCUR3# 21 DVDD 22 PSELF 23 PGANG 25 OVCUR1# 10 X1 11 X2 12 DM3 13 DP3 14 AVDD I_5V 24 OVCUR2# I_5V 26 SDA I_5V 27 V5 P 28 V33 ©2011 Genesys Logic. Table 3.GL850G LQFP 48 Pin List Pin# 1 2 3 4 5 6 7 8 9 Pin Name Type Pin# AVDD AGND DM0 DP0 DM1 DP1 AVDD AGND DM2 P P B B B B P P B B A P Pin Name Type Pin# P I O P B B P P B B O O Pin Name Type Pin# I I O O O O P O O Pin Name Type I_5V P B I_5V O I_5V O I O O P P 13 AGND 14 X1 15 X2 16 AVDD 17 DM3 18 DP3 19 AVDD 20 AGND 21 DM4 22 DP4 23 PGREEN4 24 PAMBER4 25 SEL48 26 RESET# 27 TEST 28 OVCUR4# 29 PWREN4# 30 OVCUR3# 31 PWREN3# 32 PGREEN3 33 PAMBER3 34 DVDD 35 PGREEN2 36 PAMBER2 37 PSELF 39 PGANG 41 PWREN2# 43 PWREN1# 44 SEL27 45 PGREEN1 46 PAMBER1 47 V5 48 V33 I_5V 38 DVDD I_5V 40 OVCUR2# I_5V 42 OVCUR1# 10 DP2 11 RREF 12 AVDD Table 3.3 .GL850G Datasheet 3. Inc.2 . .

output: 0@normal. 20.3 8. output: 1@normal. After the strapping period. 32. this pin will output low. 1@suspend Individual input:0.26 27.36.DP0 DM1.12 4 QFN 28 Pin 1. Green LED indicator for DSPORT1~4 1. Over current indicator for DSPORT1~4.18 21.16 8 I/O Type B B B B B A Description USB signals for USPORT USB signals for DSPORT1 USB signals for DSPORT2 USB signals for DSPORT3 USB signals for DSPORT4 A 680Ω resister must be connected between RREF and analog ground (AGND) Note: USB signals must be carefully handled in PCB routing.22 11 GL850G SSOP 28 Pin 25. For detailed information. please see Chapter 5 Gang input:1.4 6.DP4 RREF LQFP 48 Pin 3. Page 16 .24.24 37 -- -- PAMBER1~4 PSELF -17 -22 PGANG 39 18 23 Active low.4:O *GREEN[1~2] are also used to access the external 2:B EEPROM (pd) For detailed information.13 15.20 -- PGREEN1~4 45. 30. (pu) OVCUR1# is the only over current flag for GANG mode Active low. Power enable output for DSPORT1~4 PWREN1# is the only power-enable output for GANG O mode * Power switch is not supported in GL850G-22 version. please refer to Chapter 5 Amber LED indicator for DSPORT1~4 *Amber[1~2] are also used to access the external O (pd) EEPROM For detailed information. B When GL850G is suspended.35.GL850G Datasheet 3.23 46.DP2 DM3.Pin Descriptions USB Interface Pin Name DM0. please refer to Chapter 5 0: GL850G is bus-powered I_5V 1: GL850G is self-powered This pin is default put in input mode after power-on reset.19 QFN 28 Pin 25.9 11. 31.All rights reserved. I_5V *Over current flag On when OVCUR= low over 3ms. 33.6 9.28 GL850G SSOP 28 Pin 21.DP1 DM2. . *For detailed explanation. Hub Interface Pin Name LQFP 48 Pin 42. and then output high for normal mode.7 12.19 I/O Type Description OVCUR1~4# PWREN1~4# 43.28 2. 0@suspend ©2011 Genesys Logic.2 3. please refer to GL850G Design Guideline.40. Inc.29 22. Individual/gang mode is strapped during this period.41.4 5. this pin will be set to output mode.3.3 Pin Descriptions Table 3.4 .DP3 DM4.10 17.

default pull high 10KΩ I_5V When RESET# = low. PCB layout must take care the power routing and the ground plane. ©2011 Genesys Logic.3V analog power input for analog circuits Analog ground input for analog circuits 3. or 12/27/48MHz clock input O 12MHz crystal clock output Active low. 16.44 -- -- 12MHz crystal clock input.10 -16 15 23 QFN 28 Pin 5.14 -21 -27 I/O Type P P P Description 3.9. please refer to GL850G Design Guideline.3V regulator Vout & 3.All rights reserved. Inc.8.19 2. .12.5. (Internal pull down) 1: Chip will be put in test mode.38 -47 GL850G SSOP 28 Pin 1. whole chip is reset to the initial state SEL48/SEL27: 0 1: 48MHz OSC-in I 1 0: 27MHz OSC-in 1 1: 12MHz X’tal/OSC-in System Interface Pin Name LQFP 48 Pin 27 -- GL850G SSOP 28 Pin 14 -- QFN 28 Pin 18 26 I/O Type I (pd) B B Description TEST: 0: Normal operation. 20 34. It need be NC if using external regulator 5V-to-3. External reset input.3V power if using external regulator (LQFP48 only) Note: Analog circuits are quite sensitive to power and ground noise.3 input (SSOP28/QFN28) It can be NC or connect to 3.3V digital power input for digital circuitsLL Ground P V33 48 24 28 P 5V Power input.13.7.GL850G Datasheet Clock and Reset Interface Pin Name X1 X2 RESET# LQFP 48 Pin 14 15 26 GL850G SSOP 28 Pin 6 7 13 QFN 28 Pin 10 11 17 I/O Type I Description SEL48/SEL27 25. For detailed information. Page 17 .3V regulator Vout (LQFP48) 5V-to-3. I2C:clock output pin (SSOP 28pin/QFN 28pin only) I2C: data pin TEST/SCL SDA Power / Ground Pin Name AVDD AGND DVDD GND V5 LQFP 48 Pin 1.

Inc.All rights reserved. default input Bi-directional. Page 18 . default output Power / Ground Analog Automatic output low when suspend Internal pull up Internal pull down Open drain with internal pull up ©2011 Genesys Logic.GL850G Datasheet Notation: Type O I I_5V B B/I B/O P A SO pu pd odpu Output Input 5V tolerant input Bi-directional Bi-directional. .

All rights reserved.GL850G Datasheet CHAPTER 4 BLOCK DIAGRAM Figure 4.1 . Inc.GL850G Block Diagram (Single TT) ©2011 Genesys Logic. . Page 19 .

5. The generated clocks are proven quite accurate that help in generating high speed signal without jitter. USPORT transceiver will operate in full-speed electrical signaling when GL850G is plugged into a 1.1. not in SIE.2 PLL (Phase Lock Loop) GL850G contains a 40x PLL. 5. The main functions include the state machines of Receiver and Transmitter. downstream port number setting.0 Transceiver Microcell Interface) UTMI handles the low level USB protocol and signaling. ©2011 Genesys Logic.7 SIE (Serial Interface Engine) SIE handles the USB protocol defined in chapter 8 of USB specification Revision 2. It is an 8-bit RISC processor with 2K ROM and 64 bytes RAM. CRC check. Bit stuffing /de-stuffing. The main functions of SIE include the state machine of USB protocol flow. supporting USB 2. Unlike USB 1.0 host/hub. Through the firmware based architecture.5 UTMI (USB 2. It’s designed based on the Intel’s UTMI specification 1. FRTIMER keeps tracking the host’s SOF such that GL850G is always safely synchronized to the host.0 test modes. and serial/parallel conversion. This register contains the information necessary to control endpoint0 and endpoint1 pipelines. . PID error check. Inc.1 General Description 5.1.01.1. and timeout check. USPORT transceiver will operate in high-speed electrical signaling when GL850G is plugged into a 2.1 USPORT Transceiver USPORT (upstream port) transceiver is the analog circuit that supports both full-speed and high-speed electrical characteristics defined in chapter 7 of USB specification Revision 2.1. bit stuffing/de-stuffing is implemented in UTMI.1. The major functions of UTMI logic are to handle the data and clock recovery. The functionality of FRTIMER is described in section 11.0. and PID/VID setting. NRZI encoding/decoding. and traffic control to/from the REPEATER and TT.1. GL850G possesses higher flexibility to control the USB protocol easily and correctly. individual/gang mode setting. μC can handle GPIO (general purpose I/O) settings and reading content of EEPROM to support high flexibility for customers of different configurations of hub. In addition. It mainly manipulates traffics in the upstream direction.0. 5. 5. The (micro) frame timer is derived from the hub’s local clock and is synchronized to the host (micro)frame period by the host generated Start of (micro)frame (SOF).1. device removable/non-removable setting.0.0.1. 5. It co-works with Μc to play the role of the hub kernel.6 of USB specification Revision 2. interfaces between UTMI and SIE.2 of USB Specification Revision 2. 5. It operates at 6MIPS of 12Mhz clock to decode the USB command issued from host and then prepares the data to respond to the host.All rights reserved.1 host/hub.1.6 USPORT Logic USPORT implements the upstream port logic defined in section 11. Page 20 .3 FRTIMER This module implements hub (micro) frame timer. PLL generates the clock sources for the whole chip.8 Control/Status Register Control/Status register is the interface register between hardware and firmware. 5.GL850G Datasheet CHAPTER 5 FUNCTION DESCRIPTION 5. These configurations include self/bus power mode setting.4 μC μC is the micro-processor unit of GL850G.

the REPEATER/TT routing logic will route the traffic channel to the REPEATER. GL852G adopts multiple TT architecture to provide the most performance effective solution. it will operate in USB 1. Single TT shares the same buffer control module for each downstream port.0 hub is connected to the downstream port of an USB 1.1 Host/Hub If an USB 2. TT basically handles the unbalanced traffic speed between the USPORT (operating in HS) and DSPORTS (operating in FS/LS) of hub.4 and section 11.0 hub. REPEATER/TT routing logic switches the traffic channel to the TT.Operating in USB 1. REPEATER controls the traffic flow when upstream port and downstream port are signaling in the same speed. Multiple TT provides control logics for each downstream port respectively. For an USB 1.9 REPEATER Repeater logic implements the control logic defined in section 11. Under situation that USPORT and DSPORT are signaling in the same speed. both upstream direction traffic and downstream direction traffic are passing through REPEATER. Under situation that USPORT is in the high speed signaling and DSPORT is in the full/low speed signaling. Inc.All rights reserved.1.1.1 HOST/HUB USPORToperating in FS signaling Traffic channel is routed to REPEATER REPEATER TT DSPORT operating in FS/LS signaling Figure 5. That is.14 ~ 11. GL850G adopts the single TT architecture to provide the most cost effective solution. 5.0.1.1 Scheme ©2011 Genesys Logic.7 of USB specification Revision 2.11. In addition.1 Connected to USB 1. USB 1. REPEATER/TT routing logic switches the traffic channel to the REPEATER.1 host/hub.11 REPEATER/TT Routing Logic REPEATER and TT are the major traffic control machines in the USB 2.GL850G Datasheet 5. Page 21 .0. REPEATER will generate internal resume signal whenever a wakeup event is issued under the situation that hub is globally suspended. 5. Please refer to GL852G datasheet for more detailed information.1 .22 of USB specification Revision 2.1 mode.10 TT (Transaction Translator) TT implements the control logic defined in section 11. .1 hub.1. 5.

it also output the control signals to the DSPORT transceiver.0. full-speed.5 of USB specification Revision 2.2 .Operating in USB 2. ©2011 Genesys Logic. each DSPORT transceiver accurately controls its own squelch level to detect the detachment and attachment of devices. FS/LS: Traffic channel is routed to TT DSPORT operating in HS signaling DSPORT operating in FS/LS signaling Figure 5. and low-speed electrical characteristics defined in chapter 7 of USB specification Revision 2. USB 2. . over current detection and power enable control.2 Connected to USB 2. the connection/disconnection detection. HS: Traffic channel is routed to REPEATER REPEATER TT HS vs.12 DSPORT Logic DSPORT (downstream port) logic implements the control logic defined in section 11.1.1.0 hub is connected to an USB 2. It mainly manipulates the state machine. Page 22 .All rights reserved. 5.13 DSPORT Transceiver DSPORT transceiver is the analog circuit that supports high-speed. In addition.0 Scheme 5.11.GL850G Datasheet 5.0. the traffic channel will then be routed to TT when the device connected to the downstream port is signaling in full/low speed. On the other hand. it will operate in USB 2. and the status LED control of the downstream port.0 host/hub. The traffic channel will then be routed to the REPEATER when the device connected to the downstream port is signaling also in high speed.0 HOST/HUB USPORToperating in HS signaling HS vs.1. The upstream port signaling is in high speed with bandwidth of 480 Mbps under this environment. Inc.0 mode. Besides.0 Host/Hub If an USB 2.

Page 23 .2.4 .2 Configuration and I/O Settings 5. The power on sequence will start after the power good voltage has been met. RESETJ.3 .7 uS after power good. .1 RESET Setting GL850G’s power on reset can either be triggered by external reset or internal power good reset circuit.3V) and initiate reset when unstable power event occurs.Power on Sequence of GL850G ©2011 Genesys Logic.All rights reserved. and the reset will be released after approximately 2. GL850G internally contains a power on reset circuit as depicted in the picture above Figure 5. The external reset pin. is connected to upstream port Vbus (5V) to sense the USB plug / unplug or 5V voltage drop. The reset trigger voltage can be set by adjusting the value of resistor R1 and R2 (Suggested value refers to schematics) GL850G’s internal reset is designed to monitor silicon’s internal core power (3. Inc.Power on Reset Diagram Figure 5.GL850G Datasheet 5.

about 50ms later. a pull low resister greater than 100KΩ should be placed.2. we suggest the reset time applied in the external reset circuit should longer than that of the internal reset circuit.7 μs ms Unit μs To fully control the reset process of GL850G. GL850G outputs the suspend flag once it is globally suspended.2 PGANG/SUSPND Setting To save pin count.5mA).5.1 .3 1.Reset Timing Symbol Parameter VDD power up to internal reset (power good) assert (12MHz) TPG VDD power up to internal reset (power good) assert (24MHz) VDD power up to internal reset (power good) assert (27MHz) VDD power up to internal reset (power good) assert (48MHz) T1 T2 VDD power up to external reset (RESETJ) assert RESET assert to respond USB command ready Min. For individual mode. Page 24 . Figure 5. Inc. It should be noticed that the polarity of LED must be followed.5 . this pin is changed to output mode. 3 70 Max. . For gang mode. Then.Timing of PGANG/SUSPEND Strapping ©2011 Genesys Logic. we also depict the suspend LED indicator schematics. otherwise the suspend current will be over spec limitation (2. a pull high resister greater than 100KΩ should be placed. 2.GL850G Datasheet Table 5. In figure 5. The individual/gang mode is decided within 20us after power on reset.2 0. 5.All rights reserved.7 1. GL850G uses the same pin to decide individual/gang mode as well as to output the suspend flag.

GL850G Datasheet GANG Mode DVDD(3. Inc.Individual/GANG Mode Setting ©2011 Genesys Logic. .6 .All rights reserved.3V) "0": Individual Mode "1": GANG Mode 100K ohm Suspend LED Indicator SUSPNDO GANG_CTL 100K ohm Suspend LED Indicator Inside GL850G On PCB Individual Mode Figure 5. Page 25 .3V) DVDD(3.

5 mA. Both manual mode and Automatic mode are supported in GL850G.8 .SELF/BUS Power Setting 5.5.GL850G Datasheet 5. AMBER/GREEN LED DGND Inside GL850G On PCB Figure 5. Page 26 . normal operation current < 100 mA). GL850G also offers the ability to reply to the host according to the settings in the external EEPROM (LQFP48 supports 93C46 and QFN28/SSOP28 only supports 24C02).3 SELF/BUS Power Setting GL850G can operate under bus power and conform to the power consumption limitation completely (suspend current < 2. Inc.7 .LED Connection 5. By setting PSELF.2.2.4 LED Connections GL850G controls the LED lighting according to the flow defined in section 11.All rights reserved.3 of Universal Serial Bus Specification Revision2. GL850G will turn off the LED to save power.0. 1: Power Self PSELF 0: Power Bus Inside GL850G On PCB Figure 5.5 EEPROM Setting GL850G replies to host commands by the default settings in the internal ROM. GL850G can be configured as a bus-power or a self-power hub. The detail setting information please refers to the GL850G AP Note_EEPROM Info document.2. When GL850G is globally suspended. The schematics between GL850G and 93C46 are depicted in the following figures: ©2011 Genesys Logic. .

2 . as the following table: Table 5. based on the state of pin AMBER2.GL850G Datasheet DVDD EE_CS EE_SK EE_DI EE_DO CS SK DI DO VCC NC NC GND 93C46 Figure 5.2.9 . To prevent the content of 93C46 from being over-written. Page 27 . AMBER 4.All rights reserved.Port Number Configuration AMBER3 1 0 0 AMBER 4 0 1 0 Port Number 2 3 4 ©2011 Genesys Logic. as the following table: Table 5.3 .2.Schematics between GL850G and 93C46 GL850G firstly verifies the check sum after power on reset. It is determined by jumper setting. If the check sum is correct.Configuration by Power Switch Type AMBER2 0 1 Power Switch Enable Polarity Low-active High-active Note: When AMBER2=1. 5. . the external resistor of PWREN1~4 need pull down. based on the state of pin AMBER 3.7 Port Number Configuration (Only Available in LQFP48 Package) Number of downstream port can be configured as 2/3/4 ports by pin strapping in addition to EEPROM. 5. GL850G will take the configuration of 93C46 as part of the descriptor contents.6 Power Switch Enable Polarity (Only Available in LQFP48 Package) Both low/high-enabled power switches are supported. Inc. amber LED will be disabled when 93C46 exists.

Ref. system integrator can leverage this feature to further reduce BOM cost by removing external crystal. pin GREEN 1~4. 5.8 Non-removable Port Configuration (Only Available in LQFP48 Package) For compound application or embedded system.2. For some on-board design that 27/48MHz clock source is available. Table 5. Clock Configuration SEL48 0 1 1 SEL27 1 0 1 Clock Source 48MHz OSC-in 27MHz OSC-in 12MHz X’tal/OSC-in ©2011 Genesys Logic. Page 28 . which is selectable through GPIO configurations.GL850G Datasheet 5. Inc.4 .9 Reference Clock Configuration (Only Available in LQFP48 Package) GL850G can support optional 27/48MHz clock source.All rights reserved. such as motherboard or Monitor built-in applications. If the pin is pull high in the initial stage (POR reset). the corresponding port will be set as non-removable.2. downstream ports that always connected inside the system can be set as non-removable based on the state of corresponding status LED. .

3V Power Supply Input Voltage for digital I/O pins Open-drain input pins(Ovcur1~4#.GL850G Datasheet CHAPTER 6 ELECTRICAL CHARACTERISTICS 6.Pself.2 Operating Ranges Table 6.3V Power Supply Input Voltage for digital I/O pins Open-drain input pins(Ovcur1~4#.25 3. Inc. 4.0 +3.5 +3.1 .6 +100 12 MHz  0.5 -55 Max.5 Max.5 63.6 3.3 83.3 34.5 -0. DM) pins Storage Temperature under bias Frequency Parameter Min.5 -0.5 -0.1 Maximum Ratings Table 6.75 3. Page 29 .6 +5.5 0 0 Typ.05% Unit V V V V V o C 6.Operating Ranges Symbol V5 VDD VIN VINOD VINUSB TA TJ θJA 5V Power Supply 3.5 0.2 .5 -0.Maximum Ratings Symbol V5 VDD VIN VINOD VINUSB TS FOSC 5V Power Supply 3.0 -0.All rights reserved.0 3.Reset) Input Voltage for USB signal (DP.Pself. . +6. 5. DM) pins Ambient Temperature Absolute maximum junction temperature Thermal Characteristics 48 LQFP Thermal Characteristics 28 SSOP Thermal Characteristics 28 QFN Parameter Min. -0. 5.6 85 125 o o o Unit V V V V V o o C C C/W C/W C/W ©2011 Genesys Logic.6 +3.5 -0.Reset) Input Voltage for USB signal (DP.6 5.0 3.

5 . Max.4 0.99 0.2 -10 28 Typ.0 HS Min.6V ) Transceiver capacitance Hi-Z state data line leakage Driver output resistance for USB 2. 1.3 .5 0.2 0.8 1.5K to 3.6 0.5 20 +10 44 Unit V V V V V Pf A Ω Table 6.5 2.0 1.8 0. 4 -5 42 Typ.87 2.5 0.4 135 140 Unit mW V V V V V V KΩ KΩ Table 6. Page 30 .4 . 0 2.8 0.All rights reserved.GL850G Datasheet 6. 0.4 29 80 Typ.6 2. 0.3 3. 4.6V ) DP/DM FS static output HIGH (RL of 15K to GND ) Differential input sensitivity Differential common mode range Single-ended receiver threshold Transceiver capacitance Hi-Z state data line leakage Driver output resistance Min.DC Characteristics except USB Signals Symbol PD VIL VIH VTLH VTHL VOL VOH RDN RUP Power Dissipation LOW level input voltage HIGH level input voltage LOW to HIGH threshold voltage HIGH to LOW threshold voltage LOW level output voltage when IOL=8mA HIGH level output voltage when IOH=8mA Pad internal pull down resister Pad internal pull up resister Parameter Min. 366.3 DC Characteristics Table 6.DC Characteristics of USB Signals under FS/LS Mode Symbol VOL VOH VDI VCM VSE CIN ILO ZDRV Parameter DP/DM FS static output LOW(RL of 1.94 59 108 Max. Inc.DC Characteristics of USB Signals under HS Mode Symbol VOL CIN ILO ZDRV Parameter DP/DM HS static output LOW(RL of 1.1 5 +5 48 Unit V Pf A Ω ©2011 Genesys Logic.5K to 3. .5 0 45 Max. 426.

All rights reserved. Inc. Page 31 .4 71 80.3 H H F 3 H H ICC F 2 H H F 1 H H USPORT Config.9 71. .3 82.6 .GL850G Datasheet 6.3 80.2 83.DC Supply Current Symbol ISUSP 4 Condition Active ports Host Suspend F * * Device Typ. H: High-Speed F H Note: Test result represents silicon level operating current.6 73.2 78.9 78.7 75. 753 Unit uA mA mA mA mA mA mA mA mA mA mA mA mA mA mA F H F F H F F H F F H F N/A N/A 85. *: F: Full-Speed. ©2011 Genesys Logic.6 75.3 70. without considering additional power consumption contributed by external over-current protection circuit such as power switch or polyfuse.4 Power Consumption Table 6.3 72.

5 AC Characteristics GL850G LQFP48 package supports 93C46 EEPROM for customized VID/PID.5.2 1. Max. AC characteristics of these two types of EEPROM summarized as below figures and tables.8 1.All rights reserved.0 3.1 93C46 EEPROM IF Table 6.0 1.GL850G Datasheet 6.8 us Typ.7 .AC Characteristics of EEPROM Interface (93C46) Symbol tCSS tCSH tSKH tSKL tDIS tDIH tPD1 tPD0 Parameter CS Setup Time CS Hold Time SK High Time SK Low Time DI Setup Time DI Hold Time Output Delay to “1” Output Delay to “0” Min.0 2. 3. Page 32 . GL850G QFN28 and SSOP28 package supports 24C02 type EEPROM.4 1. 6. .8 2. Inc. Units ©2011 Genesys Logic.

Page 33 .All rights reserved.AC Characteristics of EEPROM Interface (24C02) ©2011 Genesys Logic.2 24C02 EEPROM Interface Table 6. Inc.5.8 .GL850G Datasheet 6. .

3V voltage for silicon power source. The 3.1 .Vin(V5) vs Vout(V33)* *Note: Measured environment: Ambient temperature = 25℃ / Current Loading = 200mA ©2011 Genesys Logic. On-chip Power Regulator Features:     5V to 3. Inc.All rights reserved. The integrated low-drop power regulator converts 5V power input from USB cable (Vbus) to 3.5V Max.3V low-drop power regulator 200mA maximum output driving capability Provide stable 3. The regulator’s maximum current loading is 200mA.4V~5. .3V power output is guaranteed by an internal voltage reference circuit to prevent unstable 5V power compromise USB data integrity.6 On-Chip Power Regulator GL850G requires 3.GL850G Datasheet 6. suspend current:266uA.3V source power for normal operation of internal core logic and USB physical layer (PHY). which provides enough tolerance for normal GL850G operation (below 100mA). Page 34 .3V output when Vin = 4. typical suspend current 187uA Figure 6.

All rights reserved. Inc.GL850G 48 Pin LQFP Package ©2011 Genesys Logic. . Page 35 .GL850G Datasheet CHAPTER 7 PACKAGE DIMENSION GL850G AAAAAAAGAA YWWXXXXXXXX Date Code Lot Code Internal No.1 . Green Package + AU Wire Version No. Figure 7.

. YWWXXXXXXXX Date Code Lot Code Figure 7.All rights reserved. Package GL850G Green + AU Wire AAAAAAAGAA Version No.GL850G Datasheet Internal No. Inc. Page 36 .GL850G 28 Pin SSOP Package ©2011 Genesys Logic.2 .

GL850G 28 Pin QFN Package ©2011 Genesys Logic. Inc. AAAAAAA YWWXXXX Version Date Code Lot Code Figure 7.GL850G Datasheet Internal No. GL850G No. Page 37 .3 . .All rights reserved.

1 .GL850G Datasheet CHAPTER 8 Part Number GL850G-MNGXX GL850G-HHGXX GL850G-OHG*XX ORDERING INFORMATION Table 8. Page 38 . .All rights reserved. ©2011 Genesys Logic.Ordering Information Package LQFP 48 SSOP 28 QFN 28 Green/Wire Material Green Package + AU Wire Green Package + AU Wire Green Package + AU Wire Version XX XX XX Status Available Available Available *The marking of "OHG" will not be shown on the IC due to QFN 28 package size limitation. Inc.