You are on page 1of 57

University of Incheon

A l I Analog Integrated d Ci Circuits i


Types of CMOS Technologies
▶ p-well process ▶n n-well well process ▶ dual-well process ▶ SOI(Silicon-On-Insulator)

P-Well Process
p+ p+ n+ n+

p-well ll n-sub

▶ preferred for balanced NMOS & PMOS ▷ Transistors in the native substrate has better characteristics

University of Incheon


Chong-Gun Yu

Types of CMOS Technologies
N-Well Process
p+ p p+ p n+ n+

n-well p-sub b

ad) d) - lower substrate bias effects on transistor threshold voltage - inherently lower parasitic capacitances associated with source & drain regions disad) - creates nonoptimum p-channel characteristics owing to differences in carrier mobilities - the performance of PMOS is even further degraded
University of Incheon –3– Chong-Gun Yu

Types of CMOS Technologies
Dual-Well Process
p+ p+ n-well n+ n+ p-well epitaxial layer :used for protection g against latchup

lightly doped

n+ or p+ Sub

- Separate optimization of PMOS & NMOS is possible for threshold voltage, body effect & the gain - The aim of expitaxy is to grow high high-purity purity silicon layers of controlled thickness with accurately determined dopant concentrations distributed homogeneously throughout the layer - separately optimized wells, balanced performance
University of Incheon Chong-Gun Yu


Types of CMOS Technologies
gate oxide g field oxide Al (Cu) SiO2 tungsten


p well p-epi n+ p-

n well p+ p


DualDual -Well TrenchTrench-Isolated CMOS Process

University of Incheon


Chong-Gun Yu

Types of CMOS Technologies Silicon-On-Insulator .absence of latchup problems .lower parasitic substrate capacitances University of Incheon –6– Chong-Gun Yu . such as latchup & speed ad) .insulating substrate to improve process char.closer packing of NMOS & PMOS .

rinse. [ ]) photoresist development acid etch process step spin. dry University of Incheon –7– Chong-Gun Yu .Photo-Lithographic Process optical mask oxidation photoresist removal (ashing) photoresist coating stepper exposure Typical operations in a single p photolithographic g p cycle y (from ( [Fullman]).

acid resistant coating material .polymerized by ultraviolet (UV) light .photo-sensitive organic material .negative : unexposed PR is dissolved by the solvent SiO2 sub UV li light ht Glass-mask Mask pattern sub sub University of Incheon –8– Chong-Gun Yu .Photoresist Silicon wafer photoresist .positive : polymerized area may be removed with an organic solvent .

chemical or plasma etch of SiO 2 Hardened resist SiO 2 SiO 2 University of Incheon –9– Chong-Gun Yu .Patterning of SiO2 Chemical or plasma etch Si-substrate (a) Silicon base material Photoresist SiO 2 Si-substrate (b) After oxidation and deposition of negative photoresist UV-light Patterned optical mask Exposed resist Si-substrate (c) Stepper exposure Si-substrate (f) Final result after removal of resist Si-substrate (e) After etching Hardened resist SiO 2 Si-substrate (d) After development and etching of resist.

Oxidation Oxidation : achieved by heating silicon wafer in an oxidizing atmosphere such as oxygen or water vapor ▶ Wet oxidation ▷ Si+2H2O→SiO2 + 2H2 ▷ water vapor ▷ 900℃ ~ 1000℃ ▷ Rapid process ▷ Si+O2→SiO2 ▷ pure oxygen ▷ ~ 1200℃ ▷ slow growth rate ▶ Dry oxidation Since SiO2 has approximately twice the volume of silicon. the SiO2 layer grows almost equally in both vertical directions University of Incheon – 10 – Chong-Gun Yu .Process .

Process – Semiconductor Device Building Epitaxy ▷ growing a single-crystal film on the silicon surface (which is already a single crystal) ▷ by subjecting the silicon wafer surface to elevated temperature and a source of dopant material University of Incheon – 11 – Chong-Gun Yu .

Process – Semiconductor Device Building Deposition ▷ evaporating dopant material onto the silicon surface followed by a thermal cycle (diffusion step) which is used to drive the impurities from the surface of the silicon into the bulk 1. 2. University of Incheon – 12 – Chong-Gun Yu . Pattern masking (photolithography) Deposit material over entire wafer CVD (Si3N4) chemical deposition (polysilicon) sputtering (Al) Etch away unwanted material wet etching dry (plasma) etching 3 3.

Area to be doped is exposed (photolithography) Diffusion or Ion implantation 2. University of Incheon – 13 – Chong-Gun Yu . they travel below the surface of the silicon forming regions with varying doping concentrations 1.Process – Semiconductor Device Building Diffusion & Ion Implantation ▷ subjecting the silicon substrate to highly energized donor or acceptor atoms ▷ when these atoms impinge of the silicon surface.

patterning windows in a mask material .subjecting exposed area to a dopant source .Process ※ The most significant aspect of using polysilicon as the gate electrode is its ability to be used as a further mask to allow precise definition of source and drain electrodes (self-aligned) → minimum gate-to-source/drain overlap ※ Polysilicon is formed when silicon is deposited on SiO2 or other surfaces ※ Materials used as masks .Photoresist .Silicon nitride ※ Selective diffusion .removing g any y unrequired q mask material University of Incheon Chong-Gun Yu – 14 – .Silicon dioxide .Polysilicon .

thick elsewhere Deposit polysilicon Etch thin oxide from active region (poly acts as a mask for the diffusion) Implant dopant 2. Create thin oxide in the “active” regions.Self-Aligned Process 1. University of Incheon – 15 – Chong-Gun Yu . 4. 3.

Simple N-Well CMOS Process N Well VDD 2λ VDD PMOS PMOS In Out In Contacts Out Metal 1 NMOS Polysilicon NMOS GND University of Incheon – 16 – Chong-Gun Yu .

Simple P-Well CMOS Process cut line p well University of Incheon – 17 – Chong-Gun Yu .

P-Well Mask University of Incheon – 18 – Chong-Gun Yu .

Active (Thin-oxide) Maxk University of Incheon – 19 – Chong-Gun Yu .

Poly Mask University of Incheon – 20 – Chong-Gun Yu .

P+ Select Mask University of Incheon – 21 – Chong-Gun Yu .

N+ Select Mask University of Incheon – 22 – Chong-Gun Yu .

Contact Mask University of Incheon – 23 – Chong-Gun Yu .

Metal Mask University of Incheon – 24 – Chong-Gun Yu .

channel-stop diffusion : raise the impurity concentration in the substrate → increase threshold voltage University of Incheon – 25 – Chong-Gun Yu .thick field oxide .Parasitic MOS Transistor (Field Device) metal or poly n+ Thin oxide Thinov Gate-oxide n+ n+ n+ Thick oxide field oxide higher threshold voltage ▶ To ensure higher threshold voltage of field devices .

bird's beak due to oxide encroachment and lateral movement .for channel-stop diffusion and for thick field oxide to prevent parasitic MOS trs .thick field oxide is semirecessed oxide (SROX) .SWAMI (Side WAll Masked Isolation) for reduction of the bird's beak ▶ LDD (Lightly Doped Drain) oxide spacer n+ n- n- n+ University of Incheon – 26 – Chong-Gun Yu .LOCOS & LDD ▶ LOCOS (Local Oxidation of Silicon) .thick field oxide is grown in areas where the SiN layer is absent .

R Oxide P b P-sub 1) N-well a-1> Initial oxidation a-2> Well mask b-1> Oxide etch b 2> Thin oxidation b-2> b-3> Well implantation c-1> Well drive-in <a> P.R P.CMOS Process P.R Oxide P-sub <b> Oxide N-well P-sub <c> University of Incheon – 27 – Chong-Gun Yu .

R Nitride O id Oxide <e> University of Incheon – 28 – Chong-Gun Yu .CMOS Process Nitride 2).R Nitride N-well P-sub P. Active d-1> Buffer oxidation d-2> Nitride(Si3N4) deposition e-1> Active mask e-2> 2 Ni Nitride id etch h N-well P-sub Oxide <d> P.

R Nitride Oxide B+ P-sub <f> Nitride N-well P-sub Nitride Oxide <g> FDOX N N-well ll P-sub <h> University of Incheon – 29 – Chong-Gun Yu .R R etch h-1> Field oxidation h-2> h 2 Nitride strip h-3> Buffer oxide strip P.R Nitride N-well B+ P.CMOS Process B+ 3) Field Implantation & LOCOS 3). f-1> Field VT mask f 2 Field implantation f-2. → channel stopping g-1> P P.

R PR P.R FDOX N-well Ps b P-sub P.R <j> University of Incheon – 30 – Chong-Gun Yu .CMOS Process B+ 4) Channel implantation 4). i-1> NMOS VT mask i 2> NMOS VT implantation i-2> j-1> PMOS VT mask j-2> PMOS VT implantation P.R <i> B+ FDOX N-well P-sub P.

Polysilicon Gate & S/D implantation k-1> Gate oxidation y deposition p k-2> Poly k-3> Poly mask k-4> Poly etch l-1> N+ S/D mask l-2> N+ S/D implantation m-1> S/D mask m-2> P+ S/D implantation n+ P.R BF2 <m> University of Incheon – 31 – Chong-Gun Yu .R FDOX Gate Oxide P-sub <k> As+ P.R P R Poly N-well PR P.CMOS Process 5).R FDOX N well N-well P-sub Gate Oxide As+ As+ P+ <l> BF2 BF2 FDOX N-well n+ P-sub n+ P.

n-1> CVD Oxide deposition o-1> Contact mask o-2> Contact etch p-1> Metal deposition p-2> Metal-1 mask p-3> Metal etch CVD-Oxide n+ p+ p+ FDOX n+ N-well P-sub n+ p+ <n> CVD-Oxide n+ p+ p+ FDOX n+ N-well P-sub n+ p+ <o> Metal1 n+ p+ p+ FDOX n+ N-well P-sub n+ p+ <p> University of Incheon – 32 – Chong-Gun Yu .CMOS Process 6) Contact & metal1 6).

) Metal2 & PAD q-1> IMD deposition q-2> VIA mask q-3> VIA etch q-4> Metal-2 deposition q-5> Metal-2 mask q-6> Metal-2 etch r-1> Passivation oxide r-2> 2> PAD mask k r-3> Pad etch r-4> Alloy Metal2 Metal1 Metal2 M t l1 Metal1 Al Al IMD ILD + + p + FDOX n + ++ n n p p+ FDOX n N-well P-sub Al Al Al Al n+ p+ <q> Passivation layer Al Al Al IMD Al ILD + + FDOX n+ n+ n+ pp p+ FDOX n+ N-well P-sub Al + +p + nn p Al <r> University of Incheon – 33 – Chong-Gun Yu .CMOS Process 7).

Advanced Metallization University of Incheon – 34 – Chong-Gun Yu .

at least system y failure Vin VDD well contact p+ Rsub Vss Vout VDD well contact RweII PNP n+ n+ p+ p+ Rwell n+ NPN npn p pnp p p ` Rsub n-well P-sub University of Incheon – 35 – Chong-Gun Yu .chip self-destruction .Latchup : low resistance conducting paths between VDD & Vss due to parasitic devices such as bipolar transistors & resistors .shorting of the VDD & Vss lines .

Latchup VDD RweII PNP NPN Rsub ` substrate current ↓ if enough voltage across Rsub ↓ turn on NPN ↓ current though Rwell ↓ if enough voltage across Rwell ↓ turn on PNP ↓ self-sustaining low resistance path ▷ Current has to be injected into either npn or pnp emitter to initiate latchup University of Incheon Chong-Gun Yu – 36 – .

Rsub) values ▷ reducing the gain of the parasitic transistors University of Incheon – 37 – Chong-Gun Yu .possibility high ← externally y due to voltage g or current beyond y normal operating p g ranges g ▷ radiation pulses ▶ Latchup p condition ▶ Basis for eliminating latchup ▷ reducing the resistor (Rwell.Latchup ▶ Latchup triggering factors → current injection ▷ transient current or voltage (glitches) on the supply rails .possibility low ← internally during power up (supply voltage transient) .

thin epitaxial layer on top of a highly doped substrate → reduce Rsub .neutron t i di ti and irradiation d gold ld doping d i → reduce τsub (minority carrier lifetime) ▷ Layout techniques .if NMOS source is shorted to the p+ sub contact the Rsub b is reduced .guard ring or band ▶ Internal latchup prevention techniques Rsub = Rsi + Rcontact .substrate contacts .Latchup ▶ Ways to prevent latchup ▷ Latchup resistant CMOS process .designer need not worry about the possibility of latchup occurring in internal circuitry as long as liberal sub contacts are used University of Incheon – 38 – Chong-Gun Yu .retrograde well structure .

Latchup ※ Rules ★ every well must have at least one sub(well) contact ★ every sub contact should be connected to metal directly to a supply pad ★ place sub contact as close as possible to the source of transistors connected to the supply rails → reduce Rsub + Rwell ▷ very conservative rule : one sub contact for every supply connection ▷ less conservative rule : one sub b contact for f every 5-10 5 10 trs or every 25-100 25 100μ University of Incheon – 39 – Chong-Gun Yu .

Latchup ※ I/O latchup prevention ▷ guard ring(band) .act as dummy collectors .collect minority carriers .prevent them from being injected into the respective bases ▷p p+ g guard rings g connected to VSS around n-trs ▷ n+ guard rings connected to VDD around p-trs ▷ double guard ring ▷ easy y way y is to use I/O structures designed g by y experts p ▶ Guard rings ▷ are used to collect injected minority carriers ▷ p+ diffusions in the p-substrate(well) ▷ n+ diffusions in the n-well or(sub) University of Incheon – 40 – Chong-Gun Yu .reduce the gain of the parasitic trs .

Latchup ▶ n+ Guard ring ▶ p+ Guard ring VDD p-plus Vss n-plus p+ n+ n+ guard ring n-well p+ guard ring p-sub University of Incheon – 41 – Chong-Gun Yu .

Layout Design Rules "The g goal of any y set of design g rules should be to optimize yield while keeping the geometry as small as possible without compromising the reliability of the finished circuit" University of Incheon – 42 – Chong-Gun Yu .

symbolic form into act actual al geometry geometr in silicon University of Incheon – 43 – Chong-Gun Yu . usually in stick diagram or s mbolic form.Layout Design Rules ▷ can be considered as a p prescription p for preparing p p g the p photomasks used in the fabrication of integrated circuits ▷ provides a necessary communication link between a circuit designer and a process engineer during the manufacturing phase ▷ represent the best possible compromise between performance and yield ▷ do not represent some hard boundary between correct & incorrect fab. rather a tolerance that ensures very high probability of correct fabrication and subsequent operation ▶ Main objective ▷ To T obtain b i a circuit i i with i h optimum i yield i ld in i as small ll an area as possible ibl without ih compromising reliability of the circuit ▷ To allow a ready translation of circuit design concepts..

based rules ▷ popularized by Mead & Conway ▷ based on a single parameter λ ▷ characterizes the linear feature ▷ permits first-order scaling ▷ not suffice for submicron processes University of Incheon – 44 – Chong-Gun Yu .Layout Design Rules ▶ Two approaches for describing the design rules i) Micron-based rules ▷ stated at some micron resolution ▷ given as a list of minimum feature sizes & spacings for all the masks required in a given process ▷ normal style y for industry y ii) Lambda( λ ) .

Layout Design Rules ▶ Rules are defined in terms of ▷ feature sizes (width) ▷ separations (space) ▷ overlaps (enclose) ▷ extensions t i Width E l Enclose Space Extension University of Incheon – 45 – Chong-Gun Yu .

Layout Design Rules University of Incheon – 46 – Chong-Gun Yu .

1 1.pactive)<4" ************* poly ******************************* WIDTH poly LT 2 "Rule 3.3:min select overlap of contact < 1" ENCLOSE nplus contact LT 1 "Rule 4.2:min 4 2:min select overlap of active < 2 2" ENCLOSE nplus active LT 2 "Rule 4.3:gate ext of active < 2" EXTENSION poly nactive LT 3 "Rule 3.4:min n+ select space < 2" SPACE notovernplus notoverpplus LT 2 "Rule 4.2:space(active) 2 2:space(active) < 3 3" ENCLOSE nwell pactive LT 5 "Rule 2.5:space(nactive.3:min select overlap of contact < 1" WIDTH pplus LT 2 "Rule 4.1:min select spacing to channel < 3" SPACE pgate nplus LT 3 "Rule 4.1:width(active) < 3" SPACE active LT 3 "Rule Rule 2.4:min n+ select width < 2" SPACE pplus LT 2 "Rule 4.5um Design Rule %%% MOSIS SCMOS 0.5um Design rule Lambda=0.3:well edge < 5" SPACE nwell nactive LT 5 "Rule 2.2:min select overlap of active < 2" ENCLOSE pplus contact LT 1 "Rule 4.1:width(poly) < 2" SPACE poly LT 2 "Rule 3.4:min p+ select width < 2" WIDTH nplus LT 2 "Rule 4.5um (V5.4:well contact space < 3" SPACE nwell pplug LT 3 "Rule 2.1:width(n-well) width(n well) < 10 10" SPACE[N] nwell LT 9 "Rule 1.5:field poly to active < 1" ************* select ******************************* SPACE ngate pplus LT 3 "Rule 4.4:min 3 4:min active extension of poly < 3" 3 SPACE polact LT 1 "Rule 3.3:well edge < 5" ENCLOSE nwell nplug LT 3 "Rule 2.MOSIS SCMOS 0.4:min 4 4:min p+ select space < 2" SPACE nplus LT 2 "Rule 4.2:space(n-well) diff vtg < 9" SPACE[N'] nwell LT 6 "Rule 1.3:space(n-well) same vtg < 6" ************* active ****************************** WIDTH active LT 3 "Rule 2.4:min space(between n+ and p+ select) < 2" University of Incheon – 47 – Chong-Gun Yu .4:min active extension of poly < 3" EXTENSION poly pactive LT 3 "Rule Rule 3.2:space(poly) < 2" LENGTH polyext LT 2 "Rule 3.4:well contact space < 3" SPACE notovernact notoverpact LT 4 "Rule 2.1) ************* n-well ***************************** WIDTH nwell LT 10 "Rule Rule 1.1:min select spacing to channel < 3" ENCLOSE pplus active LT 2 "Rule Rule 4.

via) < 1" University of Incheon – 48 – Chong-Gun Yu .2:minimum poly overlap < 1. min active overlap < 1.via) < 1" via contact LT 2 "Rule ( ) < 2" " ************** metal2 ***************************** WIDTH metal2 LT 3 "Rule 9. contact) < 1" ************* LENGTH LENGTH SPACE ENCLOSE SPACE SPACE SPACE via ********************************* contact LT 2 "Rule 8.MOSIS SCMOS < 2" via poly LT 2 "Rule 8.1:exact 5 1:exact contact size < 2" 2 poly contact LT 1.3:enclose(metal1.4:space(contact) < 2" contact ngate LT 2 "Rule 5.4:space(contact) < 2" active contact LT T 1.5" ************* WIDTH SPACE ENCLOSE metal1 ****************************** metal1 LT 3 "Rule 7.5" contact LT 2 "Rule 5.5 1.1:exact via size < 2" contact GT 2 "Rule 8.1:exact via size < 2" via LT 3 "Rule 8.3:enclose(metal1.4:min space(via.2:min via space < 3" metal1 via LT 1 "Rule 8.5 "Rule 5.5um Design Rule ************ LENGTH LENGTH ENCLOSE SPACE SPACE SPACE NC OS ENCLOSE contact ****************************** contact LT 2 "Rule 5.2:space(metal1) < 3" metal1 contact LT 1 "Rule 7.2:min 2 i space(metal2) ( t l2) < 4" ENCLOSE metal2 via LT 1 "Rule 9.5:min space(via.1:min width(metal2) < 3" SPACE metal2 t l2 LT 4 "R l 9 "Rule 9.poly) < 2" via active LT 2 " "Rule 8.5:min space(via.3:space(contact) < 2" contact pgate LT 2 "Rule 5.5 "Rule Rule 6.2:min 6.1:exact contact size < 2" contact GT 2 "Rule Rule 5.3:enclose(metal2.1:width(metal1) < 3" metal1 LT 3 "Rule 7.

spacing(different potential) Min spacing(same potential) Min. width Min.MOSIS SCMOS 0.3 n-well 1. 10 9 6 n-well 1.1 University of Incheon – 49 – Chong-Gun Yu .1 1.2 13 1.3 Min.5um Design Rule n-well 1.2 n-well 1.

5 Mi width Min.4 24 2.1 Active N-plus P-plus Poly Metal1 Metal2 Contact 2.3 N well 23 2. spacing between non-abutting active of different implant 3 3 5 3 4 2.4 2. active to well edge Min.5 2.4 Via University of Incheon – 50 – Chong-Gun Yu .2 2.5um Design Rule Active 21 2.3 2.2 2.2 2. spacing Min.1 2.3 2. id h Min.MOSIS SCMOS 0.5 2.1 2. nplug/pplug to well edge Min.

MOSIS SCMOS 0.3 3.2 3.3 Via 3.2 University of Incheon – 51 – Chong-Gun Yu . gate extension of active Min.5 Min. space Min.1 3.4 3.4 3.5 3. width Min.1 Active N-plus P-plus P plus Poly Metal1 Metal2 Contact 3. active extension of poly Min.5um Design Rule Poly 3. field poly to active 2 2 2 3 1 3.

width & space 3 2 1 2 42 4.MOSIS SCMOS 0.4 Active N-plus P-plus Poly Metal1 Metal2 Contact 41 4.3 44 4.3 Via 4.2 4.2 4.4 University of Incheon – 52 – Chong-Gun Yu .1 4.2 4.5um Design Rule Select (n-plus & p-plus) 41 4. Min.4 Min space to channel Min.4 N well 4. overlap of active Min.3 4.1 4. overlap of contact Min.1 4.

3 5. poly overlap Min.1 University of Incheon – 53 – Chong-Gun Yu . space Min.2 5.2 Exact contact size Min.1 5.4 6.MOSIS SCMOS 0. space to gate of Tr.2 5.2 5.5um Design Rule Contact 5. active overlap 2x2 2 2 2 2 N-plus P-plus p Poly Metal2 Contact Active Metal1 Via 5.1 53 5.3 5.4 6. Min.4 5.

1 7. 3 3 1 Active N plus N-plus P-plus Poly Metal1 Metal2 Contact 7. space Min overlap of contact Min.5um Design Rule Metal1 7.2 73 7.1 7. width Min.MOSIS SCMOS 0.2 Vi Via 7.3 Min.3 University of Incheon Chong-Gun Yu – 54 – .

5 8. space to contact Min.3 8.MOSIS SCMOS 0.2 8.5um Design Rule VIA 8.5 8. space to poly or active edge 2x2 3 1 2 2 Active N-plus P plus P-plus Poly Metal1 Metal2 Contact Via 8. space Min.4 University of Incheon – 55 – Chong-Gun Yu .2 8.1 8. overlap by metal1 Min.1 8.3 8.5 Exact via size Min.4 8.

1 Via 93 9.1 9.5um Design Rule Metal2 9. width Min.3 University of Incheon – 56 – Chong-Gun Yu . 3 4 1 Active N-plus P-plus Poly Metal1 Metal2 92 9.2 93 9.3 Min. space Min overlap of via Min.MOSIS SCMOS 0.2 Contact 9.

1 & 10.1 10. Min.3 University of Incheon – 57 – Chong-Gun Yu .4 10.5 Via 10. poly or active 100 75 6 30 15 10.3 10. pad-metal space to metal2 Min.4 Active N-plus P plus P-plus Poly Metal1 Metal2 C t t Contact 10. pad-metal space to metal1.5um Design Rule Overglass 10 1 10.2 Pad-metal (Metal 1 & 2) 10.MOSIS SCMOS 0.2 10. probe glass Min.5 Min bonding glass Min. pad-metal overlap of glass Min.