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®

HI-506A, HI-507A, HI-508A, HI-509A
Data Sheet August 2003 FN3143.4

16-Channel, 8-Channel, Differential 8-Channel and Differential 4-Channel, CMOS Analog MUXs with Active Overvoltage Protection
The HI-506A, HI-507A, HI-508A and HI-509A are analog multiplexers with active overvoltage protection. Analog input levels may greatly exceed either power supply without damaging the device or disturbing the signal path of other channels. Active protection circuitry assures that signal fidelity is maintained even under fault conditions that would destroy other multiplexers. Analog inputs can withstand constant 70VP-P levels with ±15V supplies. Digital inputs will also sustain continuous faults up to 4V greater than either supply. In addition, signal sources are protected from short circuiting should multiplexer supply loss occur. Each input presents 1kΩ of resistance under this condition. These features make the HI-506A, HI-507A, HI-508A and HI-509A ideal for use in systems where the analog inputs originate from external equipment, or separately powered circuitry. All devices are fabricated with 44V dielectrically isolated CMOS technology. The HI-506A is a single 16-channel multiplexer, the HI-507A is an 8-channel differential multiplexer, the HI-508A is a single 8-channel multiplexer and the HI-509A is a differential 4-channel multiplexer. If input overvoltage protection is not needed the HI-506/507/508/509 multiplexers are recommended. For further information see Application Notes AN520 and AN521.

Features
• Analog Overvoltage . . . . . . . . . . . . . . . . . . . . . . . . 70VP-P • No Channel Interaction During Overvoltage • Maximum Power Supply . . . . . . . . . . . . . . . . . . . . . . 44V • Fail Safe with Power Loss (No Latch-Up) • Break-Before-Make Switching • Analog Signal Range . . . . . . . . . . . . . . . . . . . . . . . . ±15V • Access Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns • Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . 7.5mW

Applications
• Data Acquisition Systems • Industrial Controls • Telemetry

Ordering Information
PART NUMBER HI1-0506A-2 HI1-0506A-5 HI1-0506A-8 HI3-0506A-5 HI3-0507A-5 HI1-0508A-8 HI3-0508A-5 HI1-0509A-2 HI1-0509A-5 HI1-0509A-8 HI3-0509A-5 TEMP. RANGE (oC) -55 to 125 0 to 75 PACKAGE 28 Ld CERDIP 28 Ld CERDIP PKG. DWG. # F28.6 F28.6 F28.6 E28.6 E28.6 F16.3 E16.3 F16.3 F16.3 F16.3 E16.3

-55 to 125 28 Ld CERDIP + 160 Hour Burn-In 0 to 75 0 to 75 28 Ld PDIP 28 Ld PDIP

-55 to 125 16 Ld CERDIP + 160 Hour Burn-In +0 to 75 -55 to 125 0 to 75 16 Ld PDIP 16 Ld CERDIP 16 Ld CERDIP

-55 to 125 16 Ld CERDIP + 160 Hour Burn-In 0 to 75 16 Ld PDIP

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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003. All Rights Reserved

PDIP) TOP VIEW +VSUPPLY 1 NC 2 NC 3 IN 16 4 IN 15 5 IN 14 6 IN 13 7 IN 12 8 IN 11 9 IN 10 10 IN 9 11 GND 12 VREF 13 ADDRESS A3 14 28 OUT 27 -VSUPPLY 26 IN 8 25 IN 7 24 IN 6 23 IN 5 22 IN 4 21 IN 3 20 IN 2 19 IN 1 18 ENABLE 17 ADDRESS A0 16 ADDRESS A1 15 ADDRESS A2 +VSUPPLY 1 OUT B 2 NC 3 IN 8B 4 IN 7B 5 IN 6B 6 IN 5B 7 IN 4B 8 IN 3B 9 IN 2B 10 IN 1B 11 GND 12 VREF 13 NC 14 HI-507A (PDIP) TOP VIEW 28 OUT A 27 -VSUPPLY 26 IN 8A 25 IN 7A 24 IN 6A 23 IN 5A 22 IN 4A 21 IN 3A 20 IN 2A 19 IN 1A 18 ENABLE 17 ADDRESS A0 16 ADDRESS A1 15 ADDRESS A2 HI-508A (CERDIP. HI-507A. HI-509A Pinouts HI-506A (CERDIP. HI-508A.HI-506A. PDIP) TOP VIEW A0 1 ENABLE 2 -VSUPPLY 3 IN 1 4 IN 2 5 IN 3 6 IN 4 7 OUT 8 16 A1 15 A2 14 GND 13 +VSUPPLY 12 IN 5 11 IN 6 10 IN 7 9 IN 8 HI-509A (CERDIP. PDIP) TOP VIEW A0 1 ENABLE 2 -VSUPPLY 3 IN 1A 4 IN 2A 5 IN 3A 6 IN 4A 7 OUT A 8 16 A1 15 GND 14 +VSUPPLY 13 IN 1B 12 IN 2B 11 IN 3B 10 IN 4B 9 OUT B 2 .

HI-506A. HI-509A Truth Tables HI-506A A3 X L L L L L L L L H H H H H H H H A2 X L L L L H H H H L L L L H H H H A1 X L L H H L L H H L L H H L L H H A0 X L H L H L H L H L H L H L H L H EN L H H H H H H H H H H H H H H H H “ON” CHANNEL None 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A1 X L L H H A0 X L H L H HI-509A EN L H H H H “ON” CHANNEL PAIR None 1 2 3 4 A2 X L L L L H H H H A1 X L L H H L L H H A0 X L H L H L H L H HI-508A EN L H H H H H H H H “ON” CHANNEL None 1 2 3 4 5 6 7 8 HI-507A A2 X L L L L H H H H A1 X L L H H L L H H A0 X L H L H L H L H EN L H H H H H H H H “ON” CHANNEL PAIR None 1 2 3 4 5 6 7 8 3 . HI-507A. HI-508A.

HI-506A. HI-509A Functional Diagrams HI-506A 1K IN 1A 1K IN 8A DECODER/ DRIVER 1K IN 16 IN 8B OVERVOLTAGE CLAMP AND SIGNAL ISOLATION 5V REF LEVEL SHIFT 1K DECODER/ DRIVER 1K IN 1B OUT B HI-507A OUT A 1K IN 1 1K IN 2 OUT † † † † † † DIGITAL INPUT PROTECTION VREF A0 A1 A2 A3 EN OVERVOLTAGE CLAMP AND SIGNAL ISOLATION 5V REF LEVEL SHIFT † † DIGITAL INPUT PROTECTION † † † VREF A0 A1 A2 EN HI-508A 1K IN 1A 1K IN 4A DECODER/ DRIVER 1K IN 8 IN 4B OVERVOLTAGE CLAMP AND SIGNAL ISOLATION 5V REF LEVEL SHIFT 1K 1K IN 1B HI-509A OUT A 1K IN 1 1K IN 2 OUT OUT B DECODER/ DRIVER † † DIGITAL INPUT PROTECTION A0 † † † OVERVOLTAGE CLAMP AND SIGNAL ISOLATION 5V REF LEVEL SHIFT A1 A2 EN † † DIGITAL INPUT PROTECTION A0 † † A1 EN 4 . HI-507A. HI-508A.

HI-509A Schematic Diagrams ADDRESS INPUT BUFFER AND LEVEL SHIFTER TTL REFERENCE CIRCUIT V+ R10 R9 VREF Q1 Q4 D3 GND LEVEL SHIFTER V+ P P P P P P P P P OVERVOLTAGE PROTECTION V+ D2 P N R2 R5 R3 N N R4 R6 N N N N R8 N N R7 LEVEL SHIFTED ADDRESS TO DECODE R1 200 Ω D1 N GND V- VADD IN ADDRESS DECODER V+ P P P P P P P N A0 OR A0 N N TO P-CHANNEL DEVICE OF THE SWITCH N A1 OR A1 N A2 OR A2 TO N-CHANNEL DEVICE OF THE SWITCH N A3 OR A3 N ENABLE DELETE A3 OR A3 INPUT FOR HI-507A. HI-507A.HI-506A. HI-508A. HI-508A. HI-509A DELETE A2 OR A2 INPUT FOR HI-509A V- 5 .

HI-508A. HI-507A.HI-506A. HI-509A Schematic Diagrams (Continued) MULTIPLEX SWITCH FROM DECODE OVERVOLTAGE PROTECTION N V+ P Q5 R11 1K IN D6 D7 D4 D5 N OUT N Q6 VP FROM DECODE 6 .

VA) . . . . . . .0 4. . . . . . . . . . . . . . . . . . . . . . . . . . . .. -55oC to 125oC HI-506A/507A/508A/509A-5. . . . .+22V V. . HI-507A. . . . . . -15V. 40mA Thermal Information Thermal Resistance (Typical. Pulsed 1ms. . . . . . . .8 1. . .5 1. IN or OUT. .0 0. 20mA Peak Current. . .150oC Maximum Storage Temperature Range . tS HI-506A and HI-507A To 0. (V-) -20V to (V+) +20V Continuous Current. . . . . . . . . . .5 80 300 300 - 1.0 0. . . . . . . . . . . . . . . . . .2 3. . . .+44V V+ to GND . . Whichever Occurs First Analog Signal (VIN.2 3. . 90 N/A Maximum Junction Temperature CERDIP Packages. . . VAH (Note 9) Input Leakage Current (High or Low). . . Electrical Specifications Supplies = +15V. . . . . . . . .0 V V µA 25 25 25 25 25 25 52 30 25 12 10 0. tOFF(EN) Note 2 25 Full Settling Time. . . . VAL (Logic Level Low) = 0. . CDS(OFF) DIGITAL INPUT CHARACTERISTICS Input Low Threshold. . .5 80 300 300 - 1. .5 1. . . . . . . . . . . (V-) -4V to (V+) +4V or 20mA. . . . . . . . . . HI-508A. .5 68 10 - 7 . . .2 3. .2 3. . . . . . tA Note 2 25 Full 25 - 0. . . . . . .1 pF pF pF pF pF pF Note 7 25 25 25 25 25 25 50 1. . . . CD(OFF) HI-506A HI-507A HI-508A HI-509A Digital Input Capacitance. . . . . . VAH (Logic Level High) = 4V. . .300oC Operating Conditions Temperature Ranges HI-506A/507A/508A/509A-2. . . . . . . . . . . . . . . . . .HI-506A. . . .8 1. . VOUT) . IA Note 2 Note 2 Notes 2. . . . VAL Input High Threshold. . 6 Full Full Full 4. . . . . . This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.to GND . . . VREF Pin = Open. . . .01% Off Isolation Channel Input Capacitance. HI-509A Absolute Maximum Ratings V+ to V. . . . . . . . . -8 . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 55 18 16 Ld CERDIP Package. . IN or OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . .01% HI-508A and HI-509A To 0. . . .1% To 0. . CA Input to Output Capacitance. . . . . . tON(EN) Note 2 Note 2 25 25 Full Enable Delay (OFF). . . .1 52 30 25 12 10 0. -8 MIN TYP MAX MIN -5 TYP MAX UNITS PARAMETER DYNAMIC CHARACTERISTICS Access Time. . . . . . 75 22 28 Ld PDIP Package . . . . . TTL Drive. Consult Test Circuits Section TEST CONDITIONS TEMP (oC) -2. .0 1000 1000 µs µs ns ns ns ns ns µs µs µs µs dB pF Break-Before-Make Delay. For Test Conditions. . . . . . .8V. .5 68 10 50 1. . . . . . -25V Digital Input Voltage (VEN . . . . . . . . CS(OFF) Channel Output Capacitance. . . . NOTE: 1. . . . . . . . . .1% To 0.175oC PDIP Packages . 10% Duty Cycle (Max) . . . . . . . . . . . . . tOPEN Enable Delay (ON). 0oC to 75oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. . . . . . . . .0 500 1000 500 1000 25 - 0. . . . . Note 1) θJA (oC/W) θJC (oC/W) 28 Ld CERDIP Package. . . . . θJA is measured with the component mounted on an evaluation PC board in free air. . . . . . . 60 N/A 16 Ld PDIP Package . . . Unless Otherwise Specified. . . . . .

8 50 300 200 200 100 2. 10nA is the practical lower limit for high speed measurement in the production test environment.5 1.1 - +15 1. I+ Current.5 2. VAH . For Test Conditions.1 - +15 1.0 - mA mA mW 2. 4 25 Full Full Full Full Full Notes 2. IPower Dissipation. VS = 7VRMS .5 0. ID(OFF) HI-506A HI-507A HI-508A HI-509A ID(OFF) With Input Overvoltage Applied Notes 2. 9.HI-506A. 8 Notes 2. VREF Pin = Open. 4 25 Full Full Full Full Note 5 25 Full On Channel Leakage Current. 8 . VAL .5 0. (HI-507A. HI-509A Electrical Specifications Supplies = +15V. rON Note 2 Notes 2.2 1. f = 100kHz. HI-508A. -15V. 4 25 Full Off Output Leakage Current. Analog Overvoltage = ±33V.8 MIN 6. 7. VAH (Logic Level High) = 4V. VA = 0V or 4V. ID(ON) HI-506A HI-507A HI-508A HI-509A Differential Off Output Leakage Current. IOUT = +100µA. VEN = 0.0 - - 0. Digital input leakage is primarily due to the clamp diodes (see Schematic).8 UNITS V V PARAMETER MOS Drive.5 1. HI-509A Only) POWER SUPPLY CHARACTERISTICS Current. 6.0 TYP MAX 0. HI-506A/HI-507A MOS Drive. To drive from DTL/TTL Circuits. IDIFF . Leakage currents not tested at -55oC.8V. Consult Test Circuits Section (Continued) TEST CONDITIONS VREF = +10V VREF = +10V TEMP (oC) 25 25 -2.8 2. VAL (Logic Level Low) = 0.1 4. VOUT = ±10V. 100% tested for Dash 8.0 -5 TYP MAX 0.0 50 300 200 200 100 300 200 200 100 50 V kΩ kΩ nA nA nA nA nA nA nA nA µA nA nA nA nA nA nA Off Input Leakage Current. 3 Full 25 Full -15 - 1. IS(OFF) Notes 2. 1kΩ pull-up resistors to +5V supply are recommended. VIN On Resistance. -8 MIN 6. 8.0 0.8 0. HI-506A/HI-507A ANALOG CHANNEL CHARACTERISTICS Analog Signal Range. Unless Otherwise Specified. 3. 5. CL = 15pF.5 0. 4.5 2.8V. Typical leakage is less than 1nA at 25oC.03 0.0 1.02 7.0 1.0 0.1 4.03 0. PD NOTES: Notes 2. 8 Full Full Full - 0. RL = 1K. VEN . HI-507A.0 300 200 200 100 50 -15 - 1.02 7.

VAH = 4V. ID(OFF) TEST CIRCUIT (NOTE 10) 9 ± ±10V 10V . TEST CIRCUIT 1. VREF = Open.8 0. HI-509A Test Circuits and Waveforms TA = 25oC. VAL = 0.7 0.9 0. ON RESISTANCE 100nA 10nA LEAKAGE CURRENT OFF OUTPUT CURRENT ID(OFF) EN OUT +0.1 25oC 1. HI-508A.4 1.4 1. ON RESISTANCE vs ANALOG INPUT VOLTAGE FIGURE 1C. Unless Otherwise Specified 100µA V2 IN OUT V2 100µA VIN rON = FIGURE 1A.2 1.8V ON LEAKAGE CURRENT ID(ON) 1nA A ID(OFF) 100pA OFF INPUT LEAKAGE CURRENT IS(OFF) 10pA 25 50 75 100 125 TEMPERATURE (oC) FIGURE 2A.0 0.5 1.3 ON RESISTANCE (kΩ) 1.6 -10 -55oC NORMALIZED RESISTANCE (REFERRED TO VALUE AT ±15V) 125oC 1. HI-507A. LEAKAGE CURRENT vs TEMPERATURE FIGURE 2B. NORMALIZED ON RESISTANCE vs SUPPLY VOLTAGE FIGURE 1.HI-506A.1 1.3 1. VSUPPLY = ±15V.9 0.0 0.2 1.8V.8 -8 -6 -4 -2 0 2 4 ANALOG INPUT (V) 6 8 10 5 6 7 8 9 10 11 12 13 14 15 SUPPLY VOLTAGE (±V) -55oC TO 125oC VIN = +5V FIGURE 1B.

Unless Otherwise Specified (Continued) OUT A IS(OFF) EN ± 10V +0. Two measurements per channel: ±10V and +10V. TEST CIRCUIT FIGURE 3.8V A0 A1 EN OUT A ID(ON) FIGURE 2C. HI-508A. HI-509A Test Circuits and Waveforms TA = 25oC. TEST CIRCUIT 10 .) FIGURE 2. (Two measurements per device for ID(OFF) ±10V and +10V. ANALOG INPUT OVERVOLTAGE CHARACTERISTICS 125oC FIGURE 4B. ID(On) TEST CIRCUIT (NOTE 10) 7 A IIN A ID(OFF) ±VIN FIGURE 3B.HI-506A. IS(OFF) TEST CIRCUIT (NOTE 10) NOTE: 10. ON CHANNEL CURRENT vs VOLTAGE FIGURE 4. VAH = 4V. ON CHANNEL CURRENT ± ±10V ±10V 10V 4V FIGURE 2D.8V. HI-507A. LEAKAGE CURRENTS 18 ANALOG INPUT CURRENT (mA) 15 12 9 6 3 0 15 18 21 24 27 30 33 36 ANALOG INPUT OVERVOLTAGE (±V) OUTPUT OFF LEAKAGE CURRENT ID(OFF) ANALOG INPUT CURRENT (IIN) 6 5 4 3 2 1 0 OUTPUT OFF LEAKAGE CURRENT (nA) FIGURE 3A. VREF = Open. VAL = 0. ANALOG INPUT OVERVOLTAGE CHARACTERISTICS ±14 -55oC ±12 SWITCH CURRENT (mA) ±10 ±8 ±6 ±4 ±2 0 0 2 4 6 8 10 12 14 VOLTAGE ACROSS SWITCH (±V) ±VIN A 25oC FIGURE 4A. VSUPPLY = ±15V.

VREF = Open. TEST CIRCUIT VAH = 4. ACCESS TIME FIGURE 6D. S1 ON +10V OUTPUT 10% tA OUTPUT 5V/DIV. VAH = 4V. HI-509A Test Circuits and Waveforms 8 A TA = 25oC. VAL = 0. -10V S16 ON 200ns/DIV. DYNAMIC SUPPLY CURRENT 900 800 ACCESS TIME (ns) 700 600 500 +4V 400 300 3 4 5 6 7 8 9 10 11 12 LOGIC LEVEL (HIGH) (V) 13 14 15 VA 50Ω VREF = OPEN FOR LOGIC HIGH LEVEL ≤ 6V VREF = LOGIC HIGH FOR LOGIC HIGH LEVELS > 6V A3 A2 A1 A0 EN GND VREF +15V V+ IN 1 ±10V IN 2 THRU IN 7/IN 15 ± HI-506A † IN 16 OUT V10V 10 kΩ -15V FIGURE 6A. VSUPPLY = ±15V. ACCESS TIME vs LOGIC LEVEL (HIGH) † Similar connection for HI-507A/HI-580A/HI-509A FIGURE 6B.8V. TEST CIRCUIT FIGURE 5. HI-507A.0V 1/ V 2 AH ADDRESS DRIVE (VA) 0V VA INPUT 2V/DIV. MEASUREMENT POINTS FIGURE 6. Unless Otherwise Specified (Continued) +15V/+10V +ISUPPLY SUPPLY CURRENT (mA) 6 A3 VSUPPLY = ±15V VA VSUPPLY = ±10V 2 +4V V+ IN 1 HI-506A † A2 IN 2 THRU A1 IN 7/IN 15 A0 EN GND IN 8/IN 16 OUT V±10V/±5V 4 50Ω 10V/ 10 MΩ 0 1K 10K 100K TOGGLE FREQUENCY (Hz) 1M 10M A -ISUPPLY -15V/-10V FIGURE 5A. WAVEFORMS 11 ± ± 5V 14 pF 50 pF . FIGURE 6C.HI-506A. HI-508A. SUPPLY CURRENT vs TOGGLE FREQUENCY † Similar connection for HI-507A/HI-508A/HI-509A FIGURE 5B.

VSUPPLY = ±15V. VAH = 4V.HI-506A. MEASUREMENT POINTS VA INPUT 2V/DIV. BREAK-BEFORE-MAKE DELAY 12 . FIGURE 7C.0V VA 50Ω A1 A0 IN 7/IN 15 IN 8/IN 16 OUT GND VOUT 1kΩ 50pF 50% 50% 0V ADDRESS DRIVE (VA) +4. VREF = Open.5V/DIV.0V EN OUTPUT † Similar connection for HI-507A/HI-508A/HI-509A FIGURE 7A. 100ns/DIV.8V. HI-509A Test Circuits and Waveforms TA = 25oC. HI-507A. S1 ON S16 ON OUTPUT 0. Unless Otherwise Specified (Continued) A3 A2 HI-506A † IN 1 IN 2 THRU +5V VAH = 4. TEST CIRCUIT tOPEN FIGURE 7B. HI-508A. VAL = 0. WAVEFORMS FIGURE 7.

HI-509A Test Circuits and Waveforms TA = 25oC. VAH = 4V. 100ns/DIV. VREF = Open. HI-507A. ENABLE DELAYS 13 . VAL = 0. VSUPPLY = ±15V.0V 50% 50% ENABLE DRIVE (VA) 0V OUT GND 1kΩ VOUT 50pF A1 A0 EN VA 50Ω 90% OUTPUT 10% 0V tON(EN) † Similar connection for HI-507A//HI-508A/HI-509A FIGURE 8A. DISABLED ENABLED (S1 ON) OUTPUT 2V/DIV. Unless Otherwise Specified (Continued) A3 A2 HI-506A † IN 1 IN 2 THRU IN 7/IN 15 IN 8 /IN 16 +10V VAH = 4.8V. TEST CIRCUIT tOFF(EN) FIGURE 8B. FIGURE 8C.HI-506A. MEASUREMENT POINTS ENABLE DRIVE 2V/DIV. HI-508A. WAVEFORMS FIGURE 8.

HI-506A. WORST CASE CURRENT DENSITY: 1. HI-507A.9 mils METALLIZATION: Type: CuAl Thickness: 16kÅ ±2kÅ SUBSTRATE POTENTIAL (NOTE): -VSUPPLY PASSIVATION: Silox: 12kÅ ±2kÅ Nitride: 3.5kÅ ±1kÅ NOTE: The substrate appears resistive to the -VSUPPLY terminal. HI-508A.(27) OUT A (28) +V (1) OUT B(2) 14 . HI-509A Die Characteristics DIE DIMENSIONS: 159 mils x 83. therefore it may be left floating (Insulating Die Mount) or it may be mounted on a conductor at -VSUPPLY potential.4 x 105 A/cm2 TRANSISTOR COUNT: 485 PROCESS: CMOS-DI Metallization Mask Layouts HI-506A EN (18) A0 (17) A1 A2 (16) (15) A3 VREF (14) (13) GND (12) EN (18) A0 (17) HI-507A A1 A2 (16) (15) NC VREF (14) (13) GND (12) IN 1 (19) IN 2 (20) IN 9 (11) IN 10 (10) IN 1A (19) IN 2A (20) IN 1B (11) IN 2B (10) IN 3 (21) IN 4 (22) IN 11 (9) IN 12 (8) IN 3A (21) IN 4A (22) IN 3B (9) IN 4B (8) IN 5 (23) IN 6 (24) IN 13 (7) IN 14 (6) IN 5A (23) IN 6A (24) IN 5B (7) IN 6B (6) IN 7 (25) IN 8 (26) IN 15 (5) IN 16 (4) IN 7A (25) IN 8A (26) IN 7B (5) IN 8B (4) V.(27) OUT (28) +V (1) NC (2) V.

WORST CASE CURRENT DENSITY: 1.5kÅ ±1kÅ NOTE: The substrate appears resistive to the -VSUPPLY terminal.HI-506A.4 x 105 A/cm2 TRANSISTOR COUNT: 253 PROCESS: CMOS-DI Metallization Mask Layouts HI-508A HI-509A IN 6 (11) IN 7 IN 8 (10) (9) OUT (8) IN 4 IN 3 (7) (6) IN 3B IN 4B OUT B (11) (10) (9) OUT A (8) IN 4A IN 3A (7) (6) IN 5 (12) +V (13) GND (14) IN 2 (5) IN 1 (4) -V (3) IN 2B (12) IN 1B (13) +V (14) IN 2A (5) IN 1A (4) -V (3) A2 (15) A1 (16) A0 (1) EN (2) GND (15) A1 (16) A0 (1) EN (2) 15 . HI-508A. HI-509A Die Characteristics DIE DIMENSIONS: 108 mils x 83 mils METALLIZATION: Type: CuAl Thickness: 16kÅ ±2kÅ SUBSTRATE POTENTIAL (NOTE): -VSUPPLY PASSIVATION: Silox: 12kÅ ±2kÅ Nitride: 3. therefore it may be left floating (Insulating Die Mount) or it may be mounted on a conductor at -VSUPPLY potential. HI-507A.

20 12.610 MILLIMETERS MIN 0.46 0.100 BSC 0.70 MAX 5. 3.023 0.6 MIL-STD-1835 GDIP1-T28 (D-10. HI-507A.015 0.1982.66 0.18 0.010 0.014 0.49 NOTES 2 3 4 2 3 5 5 6 7 2.005 90o 28 0.500 MAX 0.600 BSC 0. and glass overrun. The manufacturer’s identification shall not be used as a pin one identification mark. This dimension allows for off-center lid. For this configuration dimension b3 replaces dimension b2.62 BSC 3.13 90o 28 5.023 0. Dimension Q shall be measured from the seating plane to the base plane.014 0.038 aaa M C A .36 0.38 0.08 1. HI-508A. Dimension M applies to lead plating and finish thickness. 4.065 0. 9. 8.58 1.060 105o 0. when solder dip or tin plate lead finish is applied.14 0. 0 4/94 α eA c1 D E e eA eA/2 L Q S1 e D S eA/2 c 0.300 BSC 0. HI-509A Ceramic Dual-In-Line Frit Seal Packages (CERDIP) c1 -A-DBASE METAL E b1 M -Bbbb S BASE PLANE SEATING PLANE S1 b2 b ccc M C A-B S A A C A-B S D Q -CA L D S M (b) SECTION A-A (c) LEAD FINISH F28.36 1.58 0.232 0.54 BSC 15.030 0. 2. 3 8 Rev. N is the maximum number of terminal positions. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces.HI-506A. 10. Dimensioning and tolerancing per ANSI Y14. N/2. 7. Controlling dimension: INCH. Measure dimension S1 at all four corners. Corner leads (1. N.0015 2.125 0. meniscus.20 0.38 37. α aaa bbb ccc M N 16 .76 0.38 0.018 0. Dimensions b1 and c1 apply to lead base metal only.5M .65 1.015 1.B S D S NOTES: 1.008 0.85 15.52 105o 0.045 0. and N/2+1) may be configured with a partial lead paddle.015 0.200 0.026 0. 5.25 0.008 0.24 BSC 7.490 0. 6.92 0. CONFIGURATION A) 28 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE INCHES SYMBOL A b b1 b2 b3 c MIN 0. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown.14 0.045 0.

022 0.125 0.87 14.030 0.25mm). N.558 1.3.565 0.08 17 .045 inch (0.5M-1982. 95.008 1.25mm).6 will have a B1 dimension of 0. E42.0. N/2 and N/2 + 1) for E8. 7. E and eA are measured with the leads constrained to be perpendicular to datum -C.77 0.77 0.1 0. 10. 4.356 0.485 MAX 0. Corner leads (1. and E1 dimensions do not include mold flash or protrusions. E16. N is the maximum number of terminal positions.76 .030 .14mm). Dimensioning and tolerancing per ANSI Y14. the inch dimensions control.3.18 0. HI-509A Dual-In-Line Plastic Packages (PDIP) N E1 INDEX AREA 1 2 3 N/2 E28.35 4. eB and eC are measured at the lead tips with the leads unconstrained.700 0.24 12. 0.3. 1 12/00 MIN 0. 8.73 NOTES 4 4 8 5 5 6 5 6 7 4 9 Rev. In case of conflict between English and Metric dimensions.100 BSC 0. 6.195 0.010 (0.625 0.2 of Publication No.95 0.381 39.600 0.7 15.1.070 0. E28. HI-508A. Symbols are defined in the “MO Series Symbol List” in Section 2.24 BSC 2. Dimensions A. HI-507A. 2.580 A E A2 L A C L -AD BASE PLANE SEATING PLANE D1 B1 B 0.015 1.6 (JEDEC MS-011-AB ISSUE B) 28 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL -B- MILLIMETERS MIN 0. B1 maximum dimensions do not include dambar protrusions. D1.13 15.010 inch (0.204 35.380 0. 3.015 0.HI-506A.200 2. Controlling Dimensions: INCH.93 28 17.014 0. Dambar protrusions shall not exceed 0.115 28 0. E18.250 0. eC must be zero or greater. D. 9.25) M D1 A1 A1 A2 -C- B B1 C D D1 E E1 e eA eB L N eA eC C e C A B S eB NOTES: 1.010 inch (0.78 5. Mold flash or protrusions shall not exceed 0.54 BSC 15.32 MAX 6.39 3.3.005 0..600 BSC 0. 5. A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3.

015 0.36 1.200 0. Measure dimension S1 at all four corners.5M . Dimension Q shall be measured from the seating plane to the base plane. Dimension M applies to lead plating and finish thickness. N is the maximum number of terminal positions.014 0.0015 2.87 NOTES 2 3 4 2 3 5 5 6 7 2.310 MILLIMETERS MIN 0.14 0. 3. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown.015 0.08 0. 7.015 0.38 21.59 MAX 5.045 0.25 0. 8.54 BSC 7.58 1.38 0.010 0.18 0.220 MAX 0. CONFIGURATION A) 16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE INCHES SYMBOL A b b1 b2 b3 c MIN 0. Dimensions b1 and c1 apply to lead base metal only.100 BSC 0.038 aaa M C A .20 5.150 BSC 0.005 90o 16 0.125 0. HI-508A. 6. 0 4/94 α eA c1 D E e eA eA/2 L Q S1 e D S eA/2 c 0.14 0. Controlling dimension: INCH.62 BSC 3. This dimension allows for off-center lid. N/2. and glass overrun. Dimensioning and tolerancing per ANSI Y14. Corner leads (1. 10.08 1.46 0.76 0.300 BSC 0.3 MIL-STD-1835 GDIP1-T16 (D-2.13 90o 16 5.023 0. 9.38 0.008 0.060 105o 0.36 0. N.58 0. and N/2+1) may be configured with a partial lead paddle.1982.045 0.200 0.840 0.026 0.81 BSC 3.HI-506A.65 1. meniscus. when solder dip or tin plate lead finish is applied. 5.018 0.030 0. HI-507A.34 7. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces. 2. HI-509A Ceramic Dual-In-Line Frit Seal Packages (CERDIP) c1 -A-DBASE METAL E b1 M -Bbbb S BASE PLANE SEATING PLANE S1 b2 b ccc M C A-B S A A C A-B S D Q -CA L D S M (b) SECTION A-A (c) LEAD FINISH F16. For this configuration dimension b3 replaces dimension b2.023 0.20 0. 3 8 Rev.008 0. α aaa bbb ccc M N 18 .52 105o 0.66 0.B S D S NOTES: 1. 4.014 0. The manufacturer’s identification shall not be used as a pin one identification mark.065 0.

E42. 0 5/00 -C- A2 B B1 C D D1 E E1 e eA eB L N eA eC C e C A B S eB NOTES: 1. software and/or specifications at any time without notice. 8. 7.356 1.010 inch (0.HI-506A.3. E18. Intersil Corporation reserves the right to make changes in circuit design. For information regarding Intersil Corporation and its products.5M-1982.S. 5.27 0.3.015 0.430 0.195 0.240 MAX 0. 9.93 All Intersil U. Corner leads (1. 4. HI-509A Dual-In-Line Plastic Packages (PDIP) N E1 INDEX AREA 1 2 3 N/2 -B-AD BASE PLANE SEATING PLANE D1 B1 B 0..14mm).25mm).intersil.045 0.005 0. see www.355 34.93 0. Dambar protrusions shall not exceed 0.014 0. 95.com/design/quality Intersil products are sold by description only.62 6. 2.3.76 . no responsibility is assumed by Intersil or its subsidiaries for its use.25 7.3.280 MILLIMETERS MIN 0.92 3. Accordingly. 10 5 5 6 5 6 7 4 9 Rev.150 - 2. the reader is cautioned to verify that data sheets are current before placing orders. 6. A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. eC must be zero or greater.070 0. 10.558 1. Mold flash or protrusions shall not exceed 0. Information furnished by Intersil is believed to be accurate and reliable. E and eA are measured with the leads constrained to be perpendicular to datum -C.13 7.115 0.0.3A (JEDEC MS-001-AC ISSUE D) 18 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL A A1 MIN 0. D1.95 0. D. 0.39 2.325 0. Dimensioning and tolerancing per ANSI Y14.920 0.25mm).300 0. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.010 inch (0. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No.008 0. the inch dimensions control.030 .045 inch (0.10 MAX 5. nor for any infringements of patents or other rights of third parties which may result from its use.15 0.33 4.6 will have a B1 dimension of 0.115 18 0.25) M D1 A1 A2 L A C L E E18.77 0.62 BSC 10. N is the maximum number of terminal positions. Controlling Dimensions: INCH.210 0.022 0.65 8. 3.com 19 . HI-508A. products are manufactured. B1 maximum dimensions do not include dambar protrusions.880 0.100 BSC 0. and E1 dimensions do not include mold flash or protrusions.11 NOTES 4 4 8. E16.204 33. assembled and tested utilizing ISO9000 quality systems.300 BSC 0. However. In case of conflict between English and Metric dimensions. HI-507A. N/2 and N/2 + 1) for E8.54 BSC 7. E28. Dimensions A. eB and eC are measured at the lead tips with the leads unconstrained.010 (0.014 0.1.81 18 2. Intersil Corporation’s quality certifications can be viewed at www. N.intersil.