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DESIGN AND SIMULATION OF SUCCESSIVE APPROXIMATION ADC IN VERILOG USING MODELSIM

B.Tech. Project Report

B.Divya J.Pravalika S.Mamatha P.Vineesha

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING GOKARAJU RANGARAJU INSTITUTE OF ENGINEERING AND TECHNOLOGY
(Affiliated to Jawaharlal Nehru Technological University)

HYDERABAD 500 090 2013

DESIGN AND SIMULATION OF SUCCESSIVE APPROXIMATION ADC IN VERILOG USING MODELSIM


Project Report Submitted in Partial Fulfillment of the Requirements for the Degree of

Bachelor of Technology in Electronics and Communication Engineering by

B.Divya(Roll No. 09241A0405) J.Pravalika(Roll No.09241A0411) S.Mamatha(Roll No.09241A0415) P.Vineesha(Roll No.09241A0451)

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING GOKARAJU RANGARAJU INSTITUTE OF ENGINEERING AND TECHNOLOGY
(Affiliated to Jawaharlal Nehru Technological University)

HYDERABAD 500 090 2013

Department of Electronics and Communication Engineering Gokaraju Rangaraju Institute of Engineering and Technology
(Affiliated to Jawaharlal Nehru Technological University)

Hyderabad 500 090 2013

Certificate
This is to certify that this project report entitled Design and Simulation of Successive Approximation ADC using Verilog by B.Divya(Roll No. 09241A0405), J.Pravalika(Roll No.09241A0411), S.Mamatha(Roll No.09241A0415), P.Vineesha(Roll No.09241A0451), submitted in partial fulfillment of the requirements for the degree of Bachelor of Technology in Electronics and Communication Engineering of the Jawaharlal Nehru Technological University, Hyderabad, during the academic year 2012-13, is a bonafide record of work carried out under our guidance and supervision. The results embodied in this report have not been submitted to any other University or Institution for the award of any degree or diploma.

(Guide) Thanusree Sahana Assistant Professor

(External Examiner)

(Head of Department) Ravi Billa

(i)

ACKNOWLEDGMENT

Writing and implementing this master project was a very rewarding for me. It is a pleasure to express thanks to my project guides Ms. Thanusree Sahana for her encouragement and guidance throughout the course of this project. .

I would like to say thanks to Mr. M O V Pavan Kumar for his direction to planning and completion this master project report. Finally, thanks to the readers of this project report for their suggestions and comments.

B.Divya

________________________

J.Pravalika

________________________

S.Mamatha

________________________

P.Vineesha

________________________

(ii)

Abstract
In recent years, there has been a growing need for Successive Approximation Register (SAR) Analog-to-Digital Converter in medical application such as pacemaker. The demand for long battery life-time in these applications poses the requirement for designing ultra-low power SAR ADCs. The project involves custom design and implementation of 8 bit successive approximation ADC for low power and low frequency signals. The ADC would comprise of a SAR Logic, DAC, a comparator and a sample and hold circuit. The DAC would be designed to reduce the systematic and the symmetric errors using the hierarchical symmetrical switching. The main motivation is to implement design of capacitor array DAC and achieve high speed with medium resolution using 60nm technology. The advantage is matching of capacitor can be achieved better then resistor. The market and cost analysis says current SAR ADC has better future.

Keywords: SAR ADC, SAR Logic, Comparator, Low Power, high speed

(iii)

CONTENTS
Abstract iii

List of Figures
Resolution Mixed- level modeling Synthesis process Typical design process SAR ADC & DAC Output waveform Track & hold terminologies Schematic of Sample & Hold circuit. Ideal input output characteristics for a 3 bit quantizer Quantization transfer functions Quantizer models Quantization noise models Symbol of Comparator Ideal Characteristics Observed Characteristics Typical Comparator architecture Schematic of Comparator 2 14 15 16 18 20 23 24 25 26 27 29 29 29 29 30

1 Introduction
1.1 Background 1.2 Aim of this project 1.3 Methodology 1.4 Significance of this work 1.5 Outline 1 1 1 2 4 4

1.6 Conclusion

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2 Introduction of vlsi
2.1 Introduction 2.2 What is VLSI? 2.3 Advantages of ICs over discrete components 2.4 VLSI and systems 2.5 Applications of VLSI 2.6 Conclusion 6 7 8 8 9 10

3 VERILOG HDL
3.1 Introduction 3.2 Major Capabilities 3.3 Synthesis 3.4 Conclusion 11 12 13 14

4 Successive Approximation Register ADC


4.1 Introduction 4.2 SAR Architecture 4.3 Track and Hold 4.4 Comparator 4.5 SAR Logic 4.6 Conclusion 15 15 17 20 29 30

5 MODELSIM SOFTWARE
5.1 Modelsim 31

6 VERILOG CODE
6.1 Code 34

7 SCHEMATIC WAVEFORMS
7.1 Schematic 7.2 Waveform 7.3 Waveform in decimal format 7.4 Synthesis report (v) 37 38 39 40

Chapter 1 INTRODUCTION

1.1 Background

In recent years, there has been a growing need for Successive Approximation Register (SAR) Analog-to-Digital Converter in medical application such as pacemaker. The demand for long battery life-time in these applications poses the requirement for designing low power SAR ADCs.

1.2 Aim of this Project

Design and Simulation of Successive Approximation ADC. The purpose of this work is to realize a very low power Analog to Digital Converter (ADC) for biomedical application.

1.3 Methodology

A successive approximation ADC works by using a digital to analog converter (DAC) and a comparator to performa binary search to find the input voltage. A sample and hold circuit (S&H) is used to sample the analog input voltage and hold (i.e. keep a non-changing copy) the sampled value whilst the binary search is performed. The binary search starts with the most significant bit (MSB) and works towards the least significant bit (LSB). For a 8-bit output resolution, 8 comparisons are needed in the binary search, taking a least 8 clock cycles. The sample and hold circuit samples the analog input on a rising edge of the sample signal. The comparator output cmp is a logic 1 if the sampled analog voltage is greater than the output of the DAC, 0 otherwise. 1

The circuit in this example has two control signal go and done. At any point if go is 0 the circuit is reset. When go becomes a 1 the process of sampling and converting takes place. When a conversion if finished valid is set to 1 and the result is available.

1.4 Significance of this Work Resolution

Fig. 1.1 An 8-level ADC coding scheme.

The resolution of the converter indicates the number of discrete values it can produce over the range of analog values. The values are usually stored electronically in binary form, so the resolution is usually expressed in bits. In consequence, the number of discrete values available, or "levels", is a power of two. For example, an ADC with a resolution of 8 bits can encode an analog input to one in 256 different levels, since 28 = 256. The values can represent the ranges from 0 to 255 (i.e. unsigned integer) or from 128 to 127 (i.e. signed integer), depending on the application.

where M is the ADC's resolution in bits and EFSR is the full scale voltage range (also called 'span'). EFSR is given by

where VRefHi and VRefLow are the upper and lower extremes, respectively, of the voltages that can be coded. Normally, the number of voltage intervals is given by

Accuracy
An ADC has several sources of errors. Quantization error and (assuming the ADC is intended to be linear) non-linearity are intrinsic to any analog-to-digital conversion. There is also a so called aperture error which is due to a clock jitter and is revealed when digitizing a time-variant signal (not a constant value). These errors are measured in a unit called the least significant bit (LSB). In the above example of an eight-bit ADC, an error of one LSB is 1/256 of the full signal range, or about 0.4%.

Non-linearity
All ADCs suffer from non-linearity errors caused by their physical imperfections, causing their output to deviate from a linear function of their input. Important parameters for linearity are integral non-linearity (INL) and differential non-linearity (DNL). These non-linearities reduce the dynamic range of the signals that can be digitized by the ADC, also reducing the effective resolution of the ADC.

Sampling rate
The analog signal is continuous in time and it is necessary to convert this to a flow of digital value. The accuracy is limited by quantization error. However, this faithful reproduction is only possible if the sampling rate is higher than twice the highest frequency of the signal. Many ADC integrated circuits include the sample and hold subsystem internally.

1.5 Outline of this Report

INTRODUCTION TO VLSI The growing sophistication of applications continually pushes the design and manufacturing of integrated circuits and electronic systems to new levels of complexity. Our ability to do so is a testament to our growing mastery of both integrated circuit manufacturing and design, but the increasing demands of customers continue to test the limits of design and manufacturing.

VERILOG HDL
Verilog HDL is a hardware description language that can be used to model a digital system at many levels of abstraction ranging from the algorithmic-level to the gate-level to the switch-level. The complexity of the digital system being modeled could vary from that of a simple gate to a complete electronic digital system, or anything in between. The digital system can be described hierarchically and timing can be explicitly modeled within the same description.

Successive Approximation Register ADC


Successive approximation ADC operates with medium conversion speed, moderate circuit complexity and high conversion accuracy. SAR ADC is one of the most popular Nyquist rate data converters. The terms Divided reference algorithm and Binary search algorithm can be used to best describe the basic principles of SAR data converter.

SCHEMATIC
The final simulation results are shown in modelsim using verilog code.

1.6 Conclusion
Implemented an analog circuit - where the value of each successive bit is not perfectly 2^N (e.g. 1.1, 2.12, 4.05, 8.01, etc.) - a successive approximation approach might not output the ideal value because the binary search algorithm incorrectly removes what it believes to be half of the values the unknown input cannot be.

Depending on the difference between actual and ideal performance, the maximum error can easily exceed several LSBs, especially as the error between the actual and ideal 2^N becomes large for one or more bits. Since we don't know the actual unknown input, it is therefore very important that accuracy of the analog circuit used to implement a SAR ADC be very close to the ideal 2^N values. Successfully implemented successive approximation adc using binary search algorithm and found given analog input value in less conversion cycles. ADVANTAGES 1] The conversion time is equal to the "n" clock cycle period for an n-bit ADC. Thus conversion time is very short. For example for a 10-bit ADC with a clock frequency of -1 MHz,the conversion time will be 10*10^-6 i.e. 10 micro sec. only. 2] Conversion time is constant and independent of the amplitude of analog signal V to the base A.

Chapter 2 INTRODUCTION OF VLSI


2.1 Introduction
Very-large-scale integration (VLSI) is the process of creating integrated circuits by combining thousands of transistor-based circuits into a single chip. VLSI began in the 1970s when complex semiconductor and communication technologies were being developed. The microprocessor is a VLSI device. The term is no longer as common as it once was, as chips have increased in complexity into the hundreds of millions of transistors. The first semiconductor chips held one transistor each. Subsequent advances added more and more transistors, and, as a consequence, more individual functions or systems were integrated over time. The first integrated circuits held only a few devices, perhaps as many as ten diodes, transistors, resistors and capacitors, making it possible to fabricate one or more logic gates on a single device. Now known retrospectively as "small-scale integration" (SSI), improvements in technique led to devices with hundreds of logic gates, known as large-scale integration (LSI), i.e. systems with at least a thousand logic gates. Current technology has moved far past this mark and today's microprocessors have many millions of gates and hundreds of millions of individual transistors. At one time, there was an effort to name and calibrate various levels of large-scale integration above VLSI. Terms like Ultra-large-scale Integration (ULSI) were used. But the huge number of gates and transistors available on common devices has rendered such fine distinctions moot. Terms suggesting greater than VLSI levels of integration are no longer in widespread use. Even VLSI is now somewhat quaint, given the common assumption that all microprocessors are VLSI or better. As of early 2008, billion-transistor processors are commercially available, an example of which is Intel's Montecito Itanium chip. This is expected to become more commonplace as semiconductor fabrication moves from the current generation of 65 nm processes to the next 45 nm generations (while experiencing new challenges such as increased variation across process corners). 6

This microprocessor is unique in the fact that its 1.4 Billion transistor count, capable of a teraflop of performance, is almost entirely dedicated to logic (Itanium's transistor count is largely due to the 24MB L3 cache). Current designs, as opposed to the earliest devices, use extensive design automation and automated logic synthesis to lay out the transistors, enabling higher levels of complexity in the resulting logic functionality. Certain high-performance logic blocks like the SRAM cell, however, are still designed by hand to ensure the highest efficiency (sometimes by bending or breaking established design rules to obtain the last bit of performance by trading stability). 2.2 What is VLSI? VLSI stands for "Very Large Scale Integration". This is the field which involves packing more and more logic devices into smaller and smaller areas. VLSI Simply we say Integrated circuit is many transistors on one chip. Design/manufacturing of extremely small, complex circuitry using modified semiconductor material Integrated circuit (IC) may contain millions of transistors, each a few mm in size Applications wide ranging: most electronic logic devices

History of Scale Integration


late 40s Transistor invented at Bell Labs late 50s First IC (JK-FF by Jack Kilby at TI) early 60s Small Scale Integration (SSI) 10s of transistors on a chip late 60s Medium Scale Integration (MSI) 100s of transistors on a chip early 70s Large Scale Integration (LSI) 1000s of transistor on a chip early 80s VLSI 10,000s of transistors on a chip (later 100,000s & now 1,000,000s) Ultra LSI is sometimes used for 1,000,000s 7

2.3 Advantages of ICs over discrete components


While we will concentrate on integrated circuits , the properties of integrated circuits-what we can and cannot efficiently put in an integrated circuitlargely determine the architecture of the entire system. Integrated circuits improve system characteristics in several critical ways. ICs have three key advantages over digital circuits built from discrete components: Size. Integrated circuits are much smaller-both transistors and wires are shrunk to micrometer sizes, compared to the millimeter or centimeter scales of discrete components. Small size leads to advantages in speed and power consumption, since smaller components have smaller parasitic resistances, capacitances, and inductances. Speed. Signals can be switched between logic 0 and logic 1 much quicker within a chip than they can between chips. Communication within a chip can occur hundreds of times faster than communication between chips on a printed circuit board. The high speed of circuits onchip is due to their small size-smaller components and wires have smaller parasitic capacitances to slow down the signal. Power consumption. Logic operations within a chip also take much less power. Once again, lower power consumption is largely due to the small size of circuits on the chip-smaller parasitic capacitances and resistances require less power to drive them

2.4 VLSI AND SYSTEMS


These advantages of integrated circuits translate into advantages at the system level: Smaller physical size. Smallness is often an advantage in itselfconsider portable televisions or handheld cellular telephones.

Lower power consumption. Replacing a handful of standard parts with a single chip reduces total power consumption. Reducing power consumption has a ripple effect on the rest of the system: a smaller, cheaper power supply can be used; since less power consumption means less heat, a fan may no longer be necessary; a simpler cabinet with less shielding for electromagnetic shielding may be feasible, too. Reduced cost. Reducing the number of components, the power supply requirements, cabinet costs, and so on, will inevitably reduce system cost. The ripple effect of integration is such that the cost of a system built from custom ICs can be less, even though the individual ICs cost more than the standard parts they replace. Understanding why integrated circuit technology has such profound influence on the design of digital systems requires understanding both the technology of IC manufacturing and the economics of ICs and digital systems.

Applications
Electronic system in cars. Digital electronics control VCRs Transaction processing system, ATM Personal computers and Workstations Medical electronic systems. Etc.

2.5 Applications of VLSI


Electronic systems now perform a wide variety of tasks in daily life. Electronic systems in some cases have replaced mechanisms that operated mechanically, hydraulically, or by other means; electronics are usually smaller, more flexible, and easier to service. In other cases electronic systems have created totally new applications. Electronic systems perform a variety of tasks, some of them visible, some more hidden. 9

Electronic systems in cars operate stereo systems and displays; they also control fuel injection systems, adjust suspensions to varying terrain, and perform the control functions required for antilock braking (ABS) systems. Digital electronics compress and decompress video, even at highdefinition data rates, on-the-fly in consumer electronics. Low-cost terminals for Web browsing still require sophisticated electronics, despite their dedicated function. Personal computers and workstations provide word-processing, financial analysis, and games. Computers include both central processing units (CPUs) and special-purpose hardware for disk access, faster screen display, etc. Medical electronic systems measure bodily functions and perform complex processing algorithms to warn about unusual conditions. The availability of these complex systems, far from overwhelming consumers, only creates demand for even more complex systems.

2.6 Conclusion
The growing sophistication of applications continually pushes the design and manufacturing of integrated circuits and electronic systems to new levels of complexity. And perhaps the most amazing characteristic of this collection of systems is its variety-as systems become more complex, we build not a few general-purpose computers but an ever wider range of special-purpose systems. Our ability to do so is a testament to our growing mastery of both integrated circuit manufacturing and design, but the increasing demands of customers continue to test the limits of design and manufacturing.

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Chapter 3 VERILOG HDL


3.1 Introduction
Verilog HDL is a hardware description language that can be used to model a digital system at many levels of abstraction ranging from the algorithmic-level to the gate-level to the switch-level. The complexity of the digital system being modeled could vary from that of a simple gate to a complete electronic digital system, or anything in between. The digital system can be described hierarchically and timing can be explicitly modeled within the same description.

The Verilog HDL language includes capabilities to describe the behavior-al nature of a design, the dataflow nature of a design, a design's structural composition, delays and a waveform generation mechanism including aspects of response monitoring and verification, all modeled using one single language. In addition, the language provides a programming language interface through which the internals of a design can be accessed during simulation including the control of a simulation run. The language not only defines the syntax but also defines very clear simulation semantics for each language construct. Therefore, models written in can be verified using a Verilog simulator. The language inherits this language many of its

operator symbols and constructs from the C programming language. Verilog HDL provides an extensive range of modeling capabilities, some of which are quite difficult to comprehend initially. However, a core subset of the language is quite easy to leam and use. This is sufficient to model most applications.

The verilog HDL language was first developed by Gateway Design Automation in 1983 as hardware are modleling language for their simulator product, At that time ,twas a propnetary language. Because of the popularity of the,simulator product, Verilog HDL gained acceptance as a usable and practical language by a number of designers. In an effort to increase the popularity of the language, the language was placed in the public domain in 1990. 11

Open verilog International (OVI) was formed to promote Verilog. In 1992 OVI decided to pursue standardization of verilog HDL as an IEEE standard. This effort was succeful and the language became an IEEE standard in 1995. The complete standard is described in the verilog hardware description language reference manual. The standard is called std 1364-1995.

3.2 Major Capabilities


Listed below are the majort capabilities of the verilog hardware description: Primitive logic gates, such as and, or and nand, are built-in into the language. Flexibility of creating a user-defined primitive (UDP). Such a primitive could either be a combinational logic primitive or a sequential logic primitive. Switch-level modeling primitive gates, such as pmos and nmos, are also builtin into the language. A design can be modeled in three different styles or in a mixed style. These styles are: behavioral style - modeled using procedur-al constructs; dataflow style - modeled using continuous assign-ments; and structural style - modeled using gate and module instantiations. There are two data types in Verilog HDL; the net data type and the register data type. The net type represents a physical connection between structural elements while a register type represents an abstract data storage element. Figure.3-1 shows the mixed-level modeling capability of Verilog HDL, that is, in one design, each module may be modeled at a different level.

Figure 3.1 Mixed level modeling

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Verilog HDL also has built-in logic functions such as & (bitwise-and) and I (bitwise-or). High-level programming language constructs such as condition- als, case statements, and loops are available in the language. Notion of concurrency and time can be explicitly modeled. Powerful file read and write capabilities fare provided. The language is non-deterministic under certain situations, that is, a model may produce different results on different simulators; for example, the ordering of events on an event queue is not defined by the standard.

3.3 SYNTHESIS
Synthesis is the process of constructing a gate level netlist from a registertransfer level model of a circuit described in Verilog HDL. Figure.3-2 shows such a process. A synthesis system may as an intermediate step, generate a netlist that is comprised of register-transfer level blocks such as flip-flops, arithmetic-logic-units, and multiplexers, interconnected by wires. In such a case, a second program called the RTL module builder is necessary. The purpose of this builder is to build, or acquire from a library of predefined components, each of the required RTL blocks in the userspecified target technology.

Figure.3-2 synthesis process

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In this book, we assume that the target netlist is at the gate level. The logic gates used in the synthesized netlists are described in Appendix B. The module building and logic optimization phases are not described in this book. The above figure shows the basic elements ofVerilog HDL and the elements used in hardware. A mapping mechanism or a construction mechanism has to be provided that translates the Verilog HDL elements into their corresponding hardware elements as shown in figure.3-3

Fig.3-3 Typical design process

3.5 Conclusion
The Verilog HDL language includes capabilities to describe the behavior-al nature of a design, the dataflow nature of a design, a design's structural composition, delays and a waveform generation mechanism including aspects of response monitoring and verification, all modeled using one single language. 14

CHAPTER 4 Successive Approximation Register ADC


4.1 Introduction
Successive approximation ADC operates with medium conversion speed, moderate circuit complexity and high conversion accuracy. SAR ADC is one of the most popular Nyquist rate data converters. The terms Divided reference algorithm and Binary search algorithm can be used to best describe the basic principles of SAR data converter.

4.2 SAR Architecture


Successive approximation employs a binary search algorithm in a feedback loop including a 1 bit A/D converter. The Fig. 4.1 illustrates this architecture which consists of a front end track & hold circuit, comparator, DAC and SAR logic. SAR logic is basically a shift register combined with decision logic and decision register. The pointer points to the last bit changed in the decision register and the data stored in this register is the result of all comparisons performed during conversion period. During binary search, the circuit halves the difference between the sampled signal ( VIN ) and DAC output ( VDAC ). The conversion first sets MSB as 1 so that the DAC produces midscale at analog output. The comparator is then strobed to determine the polarity of Vin-Vdac. The pointer and the decision logic direct to logical output of the comparator to the MSB. If Vin>Vdac, the MSB of the register is maintained at 1 or else set to 0. Subsequently the pointer is set to choose the bit

penultimate to MSB as 1.After the DAC output has settled to its new value, the comparator is strobed once again and the above sequence is repeated.

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Fig 4.1 Block diagram of SAR ADC & DAC Output Waveform For a resolution of M bits, the successive approximation architecture is at least M times slower than the full-flash configurations, but it offers several advantages. The comparator offset voltage does not affect the overall linearity of the converter because it can be represented as a voltage source in series with Sample & hold output, indicating that offset voltage simply adds to analog input and hence appears as an offset in the overall characteristics. Consequently the comparator can be designed for high speed operation in high resolution systems. This architecture does not require an explicit subtractor which is an important advantage for high resolution applications The circuit complexity and power dissipation are in general less than that of the other architectures.

If the Sample & hold circuit provides the required linearity, speed and comparator input referred noise is small enough, and then the converters performance depends primarily on the DAC. In particular differential and integral non linearities of the converter are given by those of the DAC, 16

and the maximum conversion rate is limited by its output settling time. In the first conversion cycle, the DAC output must settle to maximum resolution of the system so that the comparator determines the MSB correctly. If the clock period is constant, the following conversion cycles will be as long as the first one, implying that the conversion rate is constrained by the speed of the DAC.

4.3 Track & Hold


A sample-and-hold (S/H) or track-and-hold (T/H) circuit is frequently required to capture rapidly varying signals for subsequent processing by slower circuitry. The function of the S/H circuit is to track/sample the analog input signal and to hold that value while subsequent circuitry digitizes it. Although an S/H refers to a device which spends an infinitesimal time acquiring signals and a T/H refers to a device which spends a finite time in this mode, common practice will be followed and the two terms will be used interchangeably throughout this discussion as will the terms sample and track. The function of a track-and-hold circuit is to buffer its input signal accurately during track mode providing at its output a signal which is linearly proportional to the input, and to maintain a constant output level during hold mode equal to the T/H output value at the instant it was strobed from track to hold by an external clock signal. Fig. 4.2 shows the waveforms of a practical sample-and-hold circuit.

Several parameters describe the speed and accuracy with which this operation is performed. The track mode is the state when the T/H output follows the T/H input. The hold mode refers to the period when the T/H output is maintained at a constant value. Track-to-hold transition is the instant when the circuit switches from the track mode to the hold mode and the hold-to-track transition refers to the switch from hold mode back to track mode. The time between successive trackto-hold transitions is the sample period thats reciprocal is the sample rate.

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Fig. 4.2 Track & hold terminologies

In track mode, the T/H functions as a simple buffer amplifier. While in the hold mode two effects are of primary importance. The first is droop which describes the decay of the output signal as energy is lost from the storage element (usually a capacitor) within the T/H circuit. This is usually not a problem for CMOS amplifiers which have infinite DC input impedance. The second important aspect of hold mode performance is feedthrough , which describes the

unwanted presence at the T/H output of a signal component proportional to the input signal. The signal feedthrough is usually described as the ratio of the unwanted output signal to the input signal amplitude. The acquisition time, is the time during which the sample-and-hold circuit must remain in the sample mode to ensure that the subsequent hold mode output will be within specified error band of the input level that existed at the instant of the sample and hold conversion. The acquisition time assumes that the gain and offset effects have been removed. The remainder of time during the track mode exclusive of acquisition time is called the track time during which the T/H output is a replica of its input.

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The settling time, is the time interval between the sample-and-hold transition command and the time when the output transient and subsequent ringing have settled to within a specified error band. Thus, the minimum sample-and-hold time is equal to the sum of acquisition time and settling time. The remainder of the time during the hold mode represents the maximum time available for A/D conversion if the T/H is used for that purpose. Conversion time of an A/D converter is the interval between the convert command and the instant when the digital code is available at the ADC output. Therefore, the minimum sample period of a practical A/D converter system is the sum of acquisition time, settling time, and conversion time. The track-to-hold transition determines many aspects of sample-andhold performance. The delay time is the time elapsed from the execution of the external hold command until the internal track-to-hold transition actually begins. In practical circuits this switching occurs over a non-zero interval called the aperture time measured between initiation and completion of the track-to-hold transition. Practical circuits do not exhibit precisely the same sample period for each sample. This random variation from sample to sample is caused by phase noise on the incoming clock signal and further exacerbated by electronic noise within the sample-and-hold itself. The standard deviation of the sample period is termed the aperture jitter. The time jitter causes an amplitude uncertainty, which depends on the rate of rise of the signal at the sample point. Finally, at the track-to- hold transition, circuit effects frequently give rise to a perturbation at the sample-andhold output. This effect which manifests itself as a discontinuity in the sample-andhold output waveform called hold jump or hold pedestal can depend on the input signal giving rise to distortion.

A large number of Sample & Hold limitations originate from nonidealities of the sampling switch. Aperture jitter, nonlinearity, pedestal error, feed through and SNDR of these circuits are strongly influenced by the sampling switch performance.

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4.4 Comparator
The comparator can be basically defined as a quantizer where in the quantization noise forms the crux of the ADC design. A quantizer is a device that converts a continuous range of input amplitude levels into a finite set of discrete digital code words. Theoretically an analog-to-digital conversion process comprises a sampling and quantization processes. A/D converter system usually consists of a quantizer along with other signal conditioning circuitry such as amplifiers, filters, sample-and-hold circuits etc. Despite this difference, the terms quantizer and A/D converter are often used synonymously. A quantizer can be uniquely described by its transfer function or quantization characteristic, which contains two sets of information: the first includes the digital codes associated with each output state, and the second includes the threshold levels which are the set of input amplitudes at which the quantizer transitions from one output code to the next. Fig. 4.4 shows the transfer characteristic of an ideal 3-bit quantizer. The analog input voltage normalized to full scale (FS) is shown on the horizontal axis. The digital output code is given on the vertical axis. The quantizer has been designed so that the output digital word changes when the analog input is at odd multiples of FS/16. The LSB of the digital output code changes each time the analog input changes by FS/2 n where n is equal to number of digital bits. A change of FS/2^n in the analog input is called an LSB. In fig 4.4 These ranges are centered about even multiples of FS/16 except for the rightmost and leftmost, which have no right or left limits, respectively. Graphically, the quantizing process means that a straight line

representing the relationship between the input and the output of a linear analog system is replaced by a transfer characteristic that is staircase-like in appearance. The quantizing process has a two-fold effect: (i) the peak-to-peak range of input sample values is subdivided into a finite set decision levels or decision thresholds that are alighted with the risers of the staircase, and (ii) the output is assigned a discrete value selected from a finite set of representation levels or reconstruction 20

values that are aligned with the treads of the staircase.

Fig. 4.4 Ideal input output characteristics for a 3 bit quantizer The transfer characteristic of uniform quantizer is shown in Fig. 4.5(a) for midtread type and in Fig. 4.5(b) for midriser type. The separation between the decision thresholds and the separation between the representation levels of the quantizer have a common value called the step size .

An ADCs actual threshold levels are denoted by Tk where the index k ranges from 0 to M giving a total of M+ 1 value. Correspondingly, ideal thresholds levels are denoted. For an N-bit bipolar quantizer, a midtread characteristic has M = 2^N thresholds and has one quantization level with value zero. A midriser characteristic has M +1 = 2N +1 thresholds, one of which has value zero. By convention, T0 = and TM= + and for each characteristic so only M 1physical thresholds actually exist. Based on the locations of thresholds, quantizers can be divided to two categories: uniform and non- uniform (Fig. 4.5). The thresholds of uniform quantizers are evenly distributed while in non-uniform quantizers thresholds locations match the probability density function of the incoming signal (such as human speech). Uniform quantizers are commonly used and will be dealt with exclusively here. 21

The Full-Scale Range, FSR, of a quantizer represents full scale input range. The length of adjacent intervals is called the quantization step or simply . For an Nbit quantizer, the relationship between the Full-Scale Range and the quantization step can be described by =FSR/2^N. A term related to Full-Scale Range is Full-Scale, FS, which is the magnitude of the Full-Scale Ranges maximum excursion from the transfer

function origin. For a bipolar quantizer with origin located at the center of fullscale range, FS = FSR / 2. For a unipolar quantizer, FS = FSR.

Fig. 4.5 Ideal quantizer transfer characteristic (a) midtread (b) midriser

Real quantizer transfer functions fall short of the ideal because imperfections in fabrication cause actual thresholds to deviate from their desired placement. Such nonidealities can be expressed in several ways (Fig. 4.6). An error which causes all thresholds to shift from their ideal positions by an equal amount is called an offset ( Voff ). Non-ideality which results in an erroneous quantizer step size, , is called gain error. can be defined as a function of FSR The step size can be assigned the value which minimizes threshold errors as calculated by linear regression. In the latter case FSR and relationship still holds, but FSR is a function of instead of vice-versa. Linearity error refers to the deviation of the actual threshold levels from their ideal values after offset and gain errors have been removed. 22

. Excessive linearity error results in missing codes, a condition wherein a valid output code say i , never occurs because its defining interval [Ti,Ti+1] has become vanishingly small, Ti+1<_ Ti. Linearity error is quantified by the threshold level errors.

This array of error terms, also called Integral nonlinearity or simply INL. Here, INL is defined for each digital word, but one should be aware that sometimes the term INL is defined as the maximum magnitude of the INL values. Related to INL is the Differential non linearity or DNL.

d k = Tk-Tk-1

Eq (4.1)

Since DNL is defined by a first-order difference equation, it is valid only for the range 1<k<M and only has physical meaning over 2<k<M-1. The element array of DNL values is also frequently described by its statistical properties such as peak and rms. The terms integral and differential arise when describing the above two error measures because DNL can be defined as the first-order difference of the INL sequence.

23

Fig. 4.6 Quantization transfer functions including error sources (a) Offset error. (b)Gain error. (c) Linearity error. (d) Missing codes

Fig. 4.7 Quantizer models. (a) nonlinear deterministic model (b) statistic model

Several terms are commonly used to describe the relative power of the analog input to an A/D converter. The loading factor, LF, express the RMS amplitude of the input waveform relative to the quantizer FSR LF= Vrms(input)/ FSR/2 Eq (4.2)

Quantization Noise can be described by a nonlinear inputoutput transfer function as depicted in fig 10. The quantized output signal, Q(x), is the sum of the original input signal x, and a quantization error, where 24

U(x)=Q(x)-x

Eq (4.3)

Here U(x) is the error resulting when the input signal, x, is quantized with finite resolution. This quantization error, as shown in Fig. 4.8, is a deterministic function of the input signal, x. However, subject to certain simplifying constraints it can be approximated as a random noise component. The constraints necessary to justify this statistical model are: U(x) is a stationary process U(x) is uncorrelated with x The elements of are U(x) uncorrelated with each other The probability density function of U(x) is uniform over ( / 2, / 2)

Fig. 4.8 Quantization noise models. (a) Ideal quantizer (b) quantizer with threshold level errors.

Under these constraints U(x) is often modeled as a uniformly distributed random variable thereby simplifying the analysis of quantizer performance. Quantizer operation is frequently characterized by signal-to-noise ratio (SNR), which expresses (usually in decibels) the ratio of the output signal power to the output noise power.

2 ( ) =

2 12

q 4.4

25

The power of the full swing sinusoidal input signal is 2

Ps = (2^N )
8 The quantizer SNR is therefore given by q (4.5)

SNRQ = 6.02N + 1.76(dB)

Eq(4.6)

Where the subscript Q modifying SNR refers to quantization noise as distinct from thermal noise or other deleterious error sources which compromise overall signal to noise ratio. Eq. (4.6) is a frequently used equation for predicting optimum A/D performance. For a 7-bit converter maximum SNR is 43.9 dB, and for an 8-bit converter the maximum SNR is 49.92dB. Eq. (4.6) can be used to assess the performance of any quantizer relative to the ideal. Replacing the maximum achievable SNR by the actual SNR and solving for the equivalent resolution, N, a figure of merit called the Effective Number Of Bits (ENOB) is derived.

ENOB = SNR-1.76 6.02

Eq(4.7)

The effective number of bits is a commonly used metric for summarizing the performance of non-ideal quantizers. In practice, A/D converters encounter inputs which are more complicated than simple sinusoids.

Under conditions with such complicated signal environments, the A/D converter may have different achievable maximum SNR. Comparison is in effect a binary phenomenon that produces a logic output of one or zero depending on the polarity of the input. The Fig. 4.10 depicts the input output characteristic of an ideal comparator, indicating an abrupt transition at Vin1-Vin2=0 26 Eq(4.8)

Vin1 Vout Vin2 Fig 4.9 Symbol of Comparator

Vin1-Vin2

Vin1-Vin2 Fig 4.10 Ideal Characteristics Fig 4.11 Observed Characteristics

Latch Vin1 A1 Vin2 Vout

CLK Fig 4.12 Typical Comparator architecture

This non linear characteristics can be approximated with a high gain amplifier where in the slope of the characteristics is small signal gain in its active region.the output of the high gain amplifier would reach saturation if Vin1-Vin2 is sufficiently large.If the saturation voltage or maximum output voltage is defined as Vh then the minimum voltage difference that the amplifier can detect is given as Vh/Av. 27

As a consequence high resolution can be obtained only by increasing the voltage gain(Av) because the logical output Vh cannot be reduced.the amplifiers used in comparators need not be linear, rather they should be capable to pick out even minimal voltage difference between the two inputs, and so positive feedback is incorporated. However there is a problem of latch up in positive feedback, in order to avoid this comparators are split into two stages. The first stage is the preamplifier and the second stage is the latch. Typical comparator architecture as in Fig. 4.12 with a preamplifier and latch has two operating modes: tracking and latching. In the tracking mode the preamplifier is enabled to amplify the input difference, hence its output tracks the input while the latch is disabled. In the latching mode, preamplifier is disabled and the latch is enabled so that the instantaneous output is regeneratively amplified by and logic levels are produced at the output. The use of latch to perform sampling and amplification of a voltage difference entails an important issue related to the output response in the presence of small inputs: metastability. If a comparator is given a finite time to regeneratively produce a logic-level output, then for some range of differential input values near zero, the comparator output will not be large enough to be unambiguously interpreted by succeeding encoding logic. This logic can produce erroneous output codes which increase the noise power in the comparator output waveform thereby diminishing SNR. They are generally known as conversion errors, rabbit errors, sparkle codes and metastability errors. The nature of the digital output produced under the conditions of metastability errors depends greatly on the output coding format used. If gray coding is used rather than binary, metastability errors manifest themselves as a single bit error in an otherwise accurate output word.

P2 M6 P1 P3

P4

M1

M3

M4 M2 P5 P6 M5 P7 P8

Vop-CMp

Vop_TH

Vop_DAC Fig 4.13 Schematic of Comparator 28

The comparator circuit presented in Fig 4.13 is a clocked comparator with power consumption of 30uW. The input stage has been designed to facilitate any common mode voltage from 0 to 1.2 V. The output stage of this circuit consists of SR latch which provides the Comparator decision value to the SAR Digital logic. The positive terminal of the comparator is driven by the output of the track and hold circuit. Here we have presented the comparator with appropriate connections for the Positive going signal. To accommodate the complete input common mode range NMOS differential pair (M3 & M4) and PMOS differential pair (M1 & M2) is used. The P2, P3, P5, P6, P7 and P8 can be imagined as a clocked inverter with cross coupling to achieve positive feedback. P1 and P4 are driven by the clock which can pull up the output nodes to VDD . This leaves the output nodes at a dynamic state. The dynamic output nodes are converted into static nodes by using a RS latch. Use of RS latch also eliminates metastability errors. An inverted based driver is placed at the output if necessary to ensure that it can drive the required capacitivie load. Positive terminal accepts the time varying input and compares the reference voltage applied on the Negative terminal. A decision is made and applied to the Output terminal of the comparator. Another comparator with Input terminals of Von_TH, Von_DAC and Output terminal of Von_CMP is used where the functionality of these terminals are exactly the same as the one mentioned above. The comparator has a rise time of 1 ns. This slewing is necessary to ensure it doesnt create a race condition by changing the Output state along with the rising edge of the clock. More details on this problem and its solution have been presented in the SAR Digital logic section.

4.5 SAR Logic


The SAR logic for the ADC is a state machine which takes the Clock signal as input. The clock signal is divided by 8 to generate the clock required for Sample & Hold circuit. 6 clock cycles are required for one complete conversion. Two additional clock cycles are for Start of Conversion and End of Conversion. 29

1. The Start of Conversion (SOC) 1st Clock cycle is used to reset all the registers in thelogic block. 2. The 2nd Clock cycle Comparator performs comparison between Input data and reference voltage and generates a 1 or 0. The data is stored in the registers and applied to the DAC. The DAC sets the reference voltage for the next conversion cycle. The same process is repeated for 2nd to 7th clock cycle to complete conversion process. 3. The End of Conversion(EOC) 8th Clock cycle latches the output data to databus. The SAR logic operated over an 8 clock cycle period, with 2 cycles allotted for SOC & EOC and 6 clock cycles for digital data. A 6 bit conversion scheme is used to divide the entire voltage head room of 0 to 1.2 V into 64 levels. If observed closely it will be found that the signal in the range of 300 to 600 mV occupies the digital data in the range of 01XXXX where XXXX varies from 0000 to 1111. This XXXX component is the 4 bit data of interest. This ensures the input signal is split into 16 levels of each 18.75 mV and an accurate digital conversion data is produced. Each level is separated by 18.75 mV which is adequate to combat the variations in DAC output voltage due to process corner variations.

Conclusion
The SAR logic also provides the clock signal to the analog sample and hold circuit as the clock out signal. This clock is based upon the SPI clock, which is divided down by a factor of eight. This is done with a counter, producing a 50% duty cycle clock. Clock out is held high for 1 cycle of the standard clock and is then held low for 7 cycles of the standard clock. The rising edge of clock out is synchronized with the beginning of the sample state.

30

CHAPTER 5 Modelsim Software


5.1 Model Sim
It is software used to simulate and verify the functionality of a VHDL/VERILOG code. In our project, we use this software for the same purpose. For each module, the input values are given and the results are observed accordingly. Following steps have to be followed to simulate a design in Modelsim: 1. Invoke modelsim by double clicking the icon. Then a window appears containing menu for various commands, work space and library space. Create a directory where the simulation files have to be saved.

2. Create a new file/Add existing file in Add items to the Project window and Create a new file window. 31

3. Then, on the work space of the main window, you find your file in which the code can be written when double-clicked.

4. After the code is written, it is saved and then compiled for syntax errors. If no syntax errors, a Green Tick mark will be seen in the work space, else a Red Cross. A red message indicates that there is an error in our code. To correct any errors, just double-click on the Error message and the error is highlighted in the source window.

32

5. Simulate the compiled code, by clicking (+) sign of work in Library tab. Clicking that file will directly open a Signals window in which all the signals(internal/external) used in the module are ready for simulation.

6. The appropriate signals are selected and added to the wave window by clicking Add to wave in the tool bar. Hence the obtained signals are assigned with required values to provide desired outputs. 7. There are different options available in the waveform window to view the output values in various representations such as Binary, Hexadecimal, Symbolic, Octal, ASCII, Decimal and Unsigned representations. 8. The Modelsim can be exited by selecting File -> quit from menu. 9. In this way the Modelsim software is used for functional verification or Simulation of the users code.

33

CHAPTER 6
6.1 VERILOG CODE
module controller(clk,go,valid,result, sample,value,cmp); input clk; // clock input input go; // go=1 to perform conversion output valid; // valid=1 when conversion finished output [7:0] result; // 8 bit result output output sample; // to S&H circuit output [7:0] value; // to DAC input cmp; // from comparitor reg [1:0] state; // current state in state machine reg [7:0] mask; // bit to test in binary search reg [7:0] result; // hold partially converted result // state assignment parameter sWait=0, sSample=1, sConv=2, sDone=3;

// synchronous design always @(posedge clk) begin if (!go) state <= sWait; // stop and reset if go=0 else case (state) // choose next state in state machine sWait : state <= sSample; sSample : begin // start new conversion so state <= sConv; // enter convert state next mask <= 8'b10000000; // reset mask to MSB only result <= 8'b0; // clear result end 34

sConv : begin // set bit if comparitor indicates input larger than // clear if (cmp) result <= result | mask; // shift mask to try next bit next time mask <= mask>>1; // finished once LSB has been done if (mask[0]) state <= sDone; end sDone :; endcase end assign sample = state==sSample; // drive sample and hold assign value = result | mask; // (result so far) OR (bit to try) assign valid = state==sDone; // indicate when finished endmodule value currently under consideration, else leave bit

6.2 TEST BENCH CODE


module testbench(); // registers to hold inputs to circuit under test, wires for outputs reg clk,go; wire valid,sample,cmp; wire [7:0] result; wire [7:0] value; // instance controller circuit controller c(clk,go,valid,result, sample,value,cmp); 35

// generate a clock with period of 20 time units always begin

#10; clk=~clk; end initial clk=0; // simulate analogue circuit with a digital model reg [7:0] hold; always @(posedge sample) hold = 8'b01001110; assign cmp = ( hold >= value); // monitor some signals and provide input stimuli initial begin $monitor($time, " go=%b valid=%b result=%b sample=%b value=%b cmp=%b state=%b mask=%b", go,valid,result,sample,value,cmp,c.state,c.mask); #100; go=0; #100; go=1; #5000; go=0; #5000; go=1; #40; go=0; #5000; $stop; end

endmodule

36

CHAPTER 7 7.1 SCHEMATIC WAVEFORMS

7.1.1 SCHEMATIC

37

7.1.2 WAVEFORM

38

7.1.3 Waveform in decimal format

39

7.2 SYNTHESIS REPORT


Release 8.2i - xst I.31 Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to ./xst/projnav.tmp CPU : 0.00 / 0.21 s | Elapsed : 0.00 / 0.00 s --> Parameter xsthdpdir set to ./xst CPU : 0.00 / 0.21 s | Elapsed : 0.00 / 0.00 s --> Reading design: controller.prj

7.2.1 TABLE OF CONTENTS


1) Synthesis Options Summary 2) HDL Compilation 3) Design Hierarchy Analysis 4) HDL Analysis 5) HDL Synthesis 5.1) HDL Synthesis Report 6) Advanced HDL Synthesis 6.1) Advanced HDL Synthesis Report 7) Low Level Synthesis 8) Partition Report 9) Final Report 9.1) Device utilization summary 9.2) TIMING REPORT

40

* Synthesis Options Summary * ---- Source Parameters Input File Name Input Format : "controller.prj" : mixed

Ignore Synthesis Constraint File : NO ---- Target Parameters Output File Name Output Format Target Device ---- Source Options Top Module Name Automatic FSM Extraction FSM Encoding Algorithm FSM Style RAM Extraction RAM Style ROM Extraction Mux Style Decoder Extraction Priority Encoder Extraction Shift Register Extraction Logical Shifter Extraction XOR Collapsing ROM Style : lut : Yes : Auto : Yes : Auto : YES : YES : YES : YES : YES : Auto 41 : controller : YES : Auto : "controller" : NGC : xc3s500e-5-fg320

Mux Extraction Resource Sharing Multiplier Style

: YES : YES : auto : No

Automatic Register Balancing ---- Target Options Add IO Buffers Global Maximum Fanout

: YES : 500 :8

Add Generic Clock Buffer(BUFG) Register Duplication Slice Packing : YES : YES

Pack IO Registers into IOBs Equivalent register Removal ---- General Options Optimization Goal Optimization Effort Keep Hierarchy RTL Output Global Optimization Write Timing Constraints Hierarchy Separator Bus Delimiter Case Specifier Slice Utilization Ratio Slice Utilization Ratio Delta :/ : <>

: auto : YES

: Speed :1 : NO : Yes : AllClockNets : NO

: maintain : 100 :5 42

---- Other Options lso Read Cores cross_clock_analysis verilog2001 safe_implementation : controller.lso : YES : NO : YES : No

Optimize Instantiated Primitives : NO use_clock_enable use_sync_set use_sync_reset * : Yes : Yes : Yes HDL Compilation *

Compiling verilog file "sadc_top.v" in library work Module <controller> compiled No errors in compilation Analysis of file <"controller.prj"> succeeded * Design Hierarchy Analysis *

Analyzing hierarchy for module <controller> in library <work> with parameters. sConv = "00000000000000000000000000000010" sDone = "00000000000000000000000000000011" sSample = "00000000000000000000000000000001" sWait = "00000000000000000000000000000000" Building hierarchy successfully finished * HDL Analysis *

Analyzing top module <controller>. 43

sWait = 32'sb00000000000000000000000000000000 sSample = 32'sb00000000000000000000000000000001 sConv = 32'sb00000000000000000000000000000010 sDone = 32'sb00000000000000000000000000000011 Module <controller> is correct for synthesis * HDL Synthesis *

Performing bidirectional port resolution... Synthesizing Unit <controller>. Related source file is "sadc_top.v". Found 8-bit register for signal <result>. Found 8-bit register for signal <mask>. Found 2-bit register for signal <state>. Summary: inferred 18 D-type flip-flop(s). Unit <controller> synthesized. HDL Synthesis Report Macro Statistics # Registers 2-bit register 8-bit register * :3 :1 :2 Advanced HDL Synthesis *

Loading device for application Rf_Device from file '3s500e.nph' in environment C:\Xilinx Advanced HDL Synthesis Report Macro Statistics 44

# Registers Flip-Flops * Low Level Synthesis

: 18 : 18 *

Optimizing unit <controller> ... Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block controller, actual ratio is 0. FlipFlop state_0 has been replicated 1 time(s) FlipFlop state_1 has been replicated 1 time(s) Final Macro Processing ... Final Register Report Macro Statistics # Registers Flip-Flops : 20 : 20

Timing Detail:
All values displayed in nanoseconds (ns) Timing constraint: Default period analysis for Clock 'clk' Clock period: 3.282ns (frequency: 304.688MHz) Total number of paths / destination ports: 89 / 22 Delay: Source: Destination: Source Clock: 3.282ns (Levels of Logic = 2) state_0_1 (FF) result_0 (FF) clk rising

Destination Clock: clk rising 45

Total memory usage is 186060 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : Number of infos 0 ( 0 filtered)

: 0 ( 0 filtered)

46

CHRONOLOGICAL BIBLIOGRAPHY

[1] J. Werner, M. Meine, K. Hoeland, M. Hexamer, and A. Kloppe,Sensor and control technology for cardiac pacing, Transactions of the Institute of Measurement and Control, 2000.

[2] L. S. Y. Wong, S. Hossain, A. Ta, J. Edvinsson, D. H. Rivas, and H. Ns. A Very Low-Power CMOS Mixed-Signal IC for Implantable Pacemaker Application, IEEE Journal of Solid-State Circuits, vol. 39, no. 12, Dec 2004.

[3] P. Lowenborg, Mixed-Signal Processing Systems, Linkoping University, 2006.

47

ALPHABETICAL BIBLIOGRAPHY

[1] B. Razavi, Principles of Data Conversion System Design, Wiley-Interscience, IEEE Press, 1995.

[2] J. L. McCreary and P. R. Gray, All-MOS Charge Redistribution Analog-toDigital Conversion Techniques-Part I, IEEE Journal of Solid-State Circuits, vol. SC10, no. 6, December 1975.

[3] A. Rodriguez-Perez, M. Delgado-Restituto, and F. Medeiro, Power efficient ADCs for Biomedical Signal Acquisition, IMSE-CNM and University of Seville.

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APPENDIX