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Introduction

• Computer simulation is today a standard part of IC design • Computer solves a large set of equation describing interconnection between various element & device model • Circuit under simulation can contain large no of elements. • Model for each element can contain large no of equations.

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Introduction (cont’d)

• Behavior of entire circuit may be needed at many points • All device equations may be solved repeatedly for all points. • Thus time complexity of computer simulation depends on complexity of device model

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Types of Models

Physical model: They are based on device physics. Parameters in this model have physical significance such as flat band voltage, doping concentration etc. • They take long time to develop, varies from process to process

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**Types of Models(cont’d)
**

• Empirical Models: Based on curve fitting technique. It can use any equation that can adequately fit data Parameters in this types of models are coefficient, exponent etc. & have no physical significance.

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**Types of Models(cont’d)
**

• Empirical Model Example:-

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**Types of Models(cont’d)
**

• Table models: They are in form of table that contain a set of o/p data for a large set of i/p parameters. Example: contain values of MOSFET drain current/ small signal parameters for a large no. of combination of bias voltage

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**SPICE Modeling for MOS Transistor
**

• Goals

Understand the element description for MOSFETs Understand the meaning and significance of the various parameters in SPICE model levels 1 through 3 for MOSFETs Understand the basic capacitance models Have a general notion of BSIM model parameters • Become aware of some newer models Understand the use and shortcomings of the models covered

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**The MOSFET Description Lines Model and Element
**

• What does SPICE stand for? • Simulation Program with Integrated Circuit Emphasis • The MOSFET Model and Element Description Lines • Process and circuit parameters which apply to a particular class of MOSFETS with varying dimensions are described for that class of MOSFETS in a single .model line in which + is used to denote line continuation.

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**SPICE mosfet model levels
**

• Level 1 is the Schichman-Hodges model • Level 2 is a geometry-based, analytical model • Level 3 is a semi-empirical, short-channel model • Level 4 is the BSIM1 model • Level 5 is the BSIM2 model, etc

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**SPICE Parameters Level 1 - 3 (Static)
**

Param. Parameter Description VTO KP GAMMA PHI TOX NSUB NSS LD

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Def. 1 0.0 0.6 0.0 0.0 0.0 0.0

Typ. 1 0.35 0.65 0.02 1.E+15 1.E+10 8.E-05

**Units V A/V^2 V^1/2 V 1/V m cm^-3 cm^-2 m
**

11

Zero-bias Vthresh Transconductance Body-effect par. Surface inversion pot. Thin oxide thickness Substrate doping Surface state density Lateral diffusion

2.E-05 3.E-05

LAMBDA Channel-length mod.

1.E-07 1.E-07

KIIT UNIVERSITY, BHUBANESWAR

**SPICE Parameters Level 1 - 3 (Static)
**

Param. Parameter Description TPG UO IS JS PB RD RS RSH Type of gate material* Surface mobility Bulk jctn. sat. curr. Bulk jctn. sat. curr. dens. Bulk junction potential Drain ohmic resistance Source ohmic resistance S/D sheet ohmic res. 0.8 0 0 0 0.75 10 10 10 Def. 1 600 Typ. 1 700 cm^2/V-s A A/m^2 V Ohms Ohms Ohms/sq Units

1.E-14 1.E-15

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**SPICE Parameters Level 1 - 3
**

Param. Parameter Description CJ MJ CJSW MJSW FC CGBO CGDO CGSO AF KF

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Def. 0 0.5 0 0.5 0.5 0 0 0 1 0.0

Typ. 1.E-09 0.5 1.E-09 0.5 0.5 2.E-10 4.E-11 4.E-11 1.2 1.E-26

Units Fd/m^2 Fd/m

Zero-bias bulk cap./A Bulk jctn. grading coeff. Zero-bias perimeter C/l Per. C grading coeff. For.-bias cap. coeff. Gate-bulk overlap C/L Gate-drain overlap C/L G-S overlap C/L Flicker-noise exp. Flicker-noise coeff.

Fd/m Fd/m Fd/m

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**Level 1 Static Const. For Device Equations
**

• Vfb = -TPG*EG/2 -Vt*ln(NSUB/ni) - q*NSS*TOX/eOx • VTO = as given, or • = Vfb + PHI + GAMMA*sqrt(PHI) • KP = as given, or • = UO*eOx/TOX

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**Level 1 Static Const. For Device Equations
**

• • • • • • • β = KP*[W/(L-2*LD)] GAMMA = as given, or = TOX*sqrt(2*eSi*q*NSUB)/eOx 2*Φp = PHI = as given, or = 2*Vt*ln(NSUB/ni) ISD = as given, or = JS*AD ISS = as given, or = JS*AS

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**Level 1 Static Device Equations
**

• • • • • • vgs < VTH, ids = 0 VTH < vds + VTH < vgs, linear region id = KP*[W/(L-2*LD)]*[vgs-VTH]*vds-vds^2/2]

VTH < vgs < vds + VTH, Saturation region id = KP/2*[W/(L-2*LD)]*(vgs - VTH)^2 *(1 + LAMBDA*vds)

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**DC SPICE Models Level 1 (Schichman-Hodges) DC Model
**

• The SPICE element description line for a MOSFET has the following form: Mx nd ng ns <nb> mname <L=val W=val AD=val + AS=val PD=val PS=val NRD=val OFF IC=vds, vgs, vbs TEMP=val> • All parameter value pairs between < and > are optional. • Equations • VT – Equation as derived previously • ID – Equations as derived previously with linear mode equation times (1+λVDS) for continuity across linear-saturation boundary. Both use Leff in place of L where: • Leff = L – 2 LD • Key Parameters: What do they represent? KP – process trans conductance k‘

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**DC SPICE Models Level 1 (Continued)
**

• VTO (note O, not 0!) – zero substrate-bias threshold voltage VT0 • GAMMA – substrate-bias or body-effect coefficient γ • PHI – twice the Fermi potential 2ΦF • LAMBDA – channel length modulation λ • Additional Parameters: What do they represent? • LD – Lateral diffusion (If not present, may need to find Leff manually!) • TPG – Type of gate material: 0 – A1, +1 – opposite to substrate, -1 – same as substrate. Default +1 For the typical CMOS process, TPG = 1 for NMOS and – 1 for PMOS

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**DC SPICE Models Level 1 (Continued)
**

• NSUB – substrate impurity concentration NA (NMOS) ND (PMOS) • NSS – Surface state density – Used to define surface component of VT0. • TOX – Oxide thickness tox • U0 (note 0, not O) – Surface mobility µ0 • RD, RS – Drain resistance, Source resistance • RSH – Drain and Source sheet resistance (Ω/□) • Derived Parameters. Note that if some parameters missing, others, if present, can be used to derive them. E. g. NSUB to derive PHI, and TOX and U0 to derive KP. Question: What parameters to derive GAMMA? If the derivable parameters are present in the model, they will be used; if not, derived if possible from other parameters (and defaults), else, defined.

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**SPICE simulation of MOS V-I Characteristics
**

• *drain characteristics of MOSFET vds 1 0 dc 5 vgs 2 0 dc 1 vnull 1 3 dc 0 m1 3 2 0 0 nmos w=10u l=1u .model nmos nmos() .dc vds 0 5 .1 vgs 0 5 1 .print dc i(vnull) .plot dc i(vnull) .end

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To be continued……….

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