Digital Signal Processing

BITS Pilani
Pilani|Dubai|Goa|Hyderabad

Date : 30/08/2013

BITS Pilani Pilani|Dubai|Goa|Hyderabad Previous class: Computation required in DSP Evolution of DSP architecture .

BITS Pilani Pilani|Dubai|Goa|Hyderabad Today class Evolution of DSP architecture Numeric Representation used in DSP Fixed point Floating point .

..+a7X[n-7] Most recurring computation is multiplication and then accumulation (MAC) . Y[n] = a0 X[n]+ a1 X[n-1]+ a2 X[n-2]+ -..Analysis of computation required for FIR filter Expression for 8-tap FIR filter.

.DSP~GPP • Real time throughput requirement • Used in embedded application. special features are provided. • Have MAC unit • Not real time throughput needed • Desktop computing • No special features. convolution. • To support DSP computation like FFT.

Most computers today are of the Von Neumann design. an American mathematician. Designed by: John Von Neumann. Single memory shared by both the program instructions and data. .What is the best suitable architecture for DSP? Architectural evolution: Von Neumann Called as Von Neumann architecture.

(Assume that CPU computation takes very small time in comparison to memory access) So need four cycles. Get the opcode of instruction. Multiply and accumulate and store result. 2. . Get data1 3. Get data2 4.How many cycles needed for MAC instruction for two numbers that reside in external memory? 1.

Harvard architecture •Developed at Harvard University (1940) •Program instructions and data can be fetched at the same time. •Increasing overall processing speed •Most present day DSPs use this dual bus architecture. . •Ex: ADSP-21xx and AT&T's DSP16xx.

Cycles needed for MAC instruction in Harvard architecture 1. So single MAC operation need 3 cycles . Instruction 1 fetched. Perform MAC operation and store result in DM (for inst 2) as well as fetch Instruction 3 from PM. Instruction 2 decode get data1 from DM and coefficient from PM 5. 2. Perform MAC operation and store result in DM as well as fetch Instruction 2 from PM. 4. Instruction 1 decode and get data1 from DM and coefficient from PM 3.

•Processors based on a three-bank modified Harvard architecture include the Zilog Z893xx. DSP563xx .Modified Harvard architecture •Three memory banks •Allow three independent memory accesses per instruction cycle. Motorola DSP5600x.

sequential accesses per instruction cycle over a single set of buses OR Using multi-ported memories that allow multiple concurrent memory accesses over two or more independent sets of buses. This arrangement provides one program memory access and two data memory accesses per instruction word. Ex: Motorola DSP561xx processors.Multiple-Access Memories Using fast memories that support multiple. .

The first time through a loop.Super Harvard Architecture (SHARCH DSP) Part of program memory is used as data memory. slower operation Next executions of the loop will be faster This means that all of the memory to CPU information transfers can be accomplished in a single cycle. Including an instruction cache in the CPU. EX: ADSP-2106x and new ADSP-211xx .

Enhanced DSP architectures: Very Long Instruction Word (VLIW) architecture: VLIW CPUs have four to eight execution units. One VLIW instruction encodes multiple operations. EX:if a VLIW device has four execution units. then a VLIW instruction for that device would have four operation fields. EX: TMS320 C6xx . VLIW instructions are usually at least 64 bits in width. VLIW CPUs use software (the compiler) to decide which operations can run in parallel. Hardware's complexity for instruction scheduling is reduced.

Endians: •Big Endian(MSB in first location) •Little endian How 12345678 will be stored in four location starting from 4000 in each case? TI DSP: Little endian Motorola DSP: Big endian .

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