6.

002

CIRCUITS AND ELECTRONICS

State and Memory

6.002 Fall 2000

Lecture 14

1

Review
Recall

vI + –
v I = VI
for

R

C

+ vC – vC (0 )

t ≥0
−t

vC = VI + (vC (0)− VI ) e RC

1

Reading: Sections 10.3, 10.5, and 10.7

6.002 Fall 2000

Lecture 14

2

This lecture will dwell on the memory property of capacitors.
For the RC circuit in the previous slide

vI

VI

vI

t ≥0
VI

0

t vC vC = VI + (vC (0)− VI ) e RC
−t

vC (0 )
0

t

Notice that the capacitor voltage for t ≥ 0 is independent of the form of the input voltage before t = 0 . Instead, it depends only on the capacitor voltage at t = 0 , and the input voltage for t ≥ 0 .

6.002 Fall 2000

Lecture 14

3

State
State : summary of past inputs relevant
to predicting the future

q=CV
for linear capacitors, capacitor voltage V is also state variable state variable, actually

6.002 Fall 2000

Lecture 14

4

State
Back to our simple RC circuit 1

vC = f (vC (0 ), vI (t ))
vC = VI + (vC (0 ) − VI ) e
−t RC

Summarizes the past input relevant to predicting future behavior

6.002 Fall 2000

Lecture 14

5

State

We are often interested in circuit response for zero state vC (0) = 0 zero input Correspondingly, zero state response or ZSR
vC = VI − VI e
−t RC

vI (t) = 0

2

zero input response or ZIR
vC = vC (0 ) e
−t RC

3

6.002 Fall 2000

Lecture 14

6

One application of STATE

DIGITAL MEMORY
Why memory? Or, why is combinational logic insufficient?

Examples
Consider adding 6 numbers on your calculator 2+9+6+5+3+8 M+ “Remembering” transient inputs

6.002 Fall 2000

Lecture 14

7

Memory Abstraction
A 1-bit memory element

d IN store M d OUT

The 6.004 view

$

The NEC View ☺

¥

Remembers input when store goes high. Like a camera that records input (dIN) when the user presses the shutter release button. The recorded value is visible at dOUT .

d IN store d OUT
6.002 Fall 2000 Lecture 14

remembers the 1
8

Building a memory element …
A First attempt

dIN

*
store

dOUT C

storage node

6.002 Fall 2000

Lecture 14

9

Building a memory element …
A

dIN store = 1

* *

vC d OUT C

dIN store = 0

vC d OUT C vC 5V VOH T t RL

Stored value leaks away

vC = 5 ⋅ e

−t RL C

T = − RLC ln

VOH 5

from 2

store pulse width >> RON C
6.002 Fall 2000 Lecture 14

10

Building a memory element …
B Second attempt buffer

dIN

*
C

dOUT RIN
buffer

store Input resistance RIN VOH T = − RIN C ln 5 RIN >> RL
Better, but still not perfect.

Demo

6.002 Fall 2000

Lecture 14

11

Building a memory element …
C Third attempt buffer + refresh

store dIN store dOUT C
Does this work?

*

No. External value can influence storage node.

6.002 Fall 2000

Lecture 14

12

Building a memory element …
D Fourth attempt buffer + decoupled refresh

store dIN store dOUT C
Works!

*

6.002 Fall 2000

Lecture 14

13

A Memory Array
4-bit memory

store Address

IN OUT

Decoder
00

A

d IN S M d OUT d IN S M d OUT d IN S M d OUT d IN S M d OUT

01

B

A

2 Address
10

a0 a1

C

B

11

D

C

IN store
D OUT

6.002 Fall 2000

Lecture 14

14

Truth table for decoder

a0 0 0 1 1

a1 0 1 0 1

A 1 0 0 0

B 0 1 0 0

C 0 0 1 0

D 0 0 0 1

6.002 Fall 2000

Lecture 14

15

Agarwal’s top 10 list on memory
10 9 8 7 6 5 I have no recollection, Senator. I forgot the homework was due today. Adlibbing ≡ ZSR I think, therefore I am. I think that was right. I forgot the rest …

6.002 Fall 2000

Lecture 14

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