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CIRCUITS AND

6.002 ELECTRONICS

State and Memory

6.002 Fall 2000 Lecture 14 1


Review

Recall

R +
vI +
– C vC

v I = VI for t ≥0 vC (0 )

−t

vC = VI + (vC (0)− VI ) e RC 1

Reading: Sections 10.3, 10.5, and 10.7

6.002 Fall 2000 Lecture 14 2


This lecture will dwell on the
memory property of capacitors.
For the RC circuit in the previous slide
vI
vI VI

t
t ≥0 0
vC
VI
−t

vC = VI + (vC (0)− VI ) e RC
vC (0 )

t
0
Notice that the capacitor voltage for t ≥ 0 is
independent of the form of the input voltage
before t = 0 . Instead, it depends only on the
capacitor voltage at t = 0 , and the input voltage
for t ≥ 0 .
6.002 Fall 2000 Lecture 14 3
State

State : summary of past inputs relevant


to predicting the future

q=CV

for linear capacitors,


capacitor voltage V
is also state variable
state variable, actually

6.002 Fall 2000 Lecture 14 4


State

Back to our simple RC circuit 1


vC = f (vC (0 ), vI (t ))
−t
vC = VI + (vC (0 ) − VI ) e RC

Summarizes the past input relevant


to predicting future behavior

6.002 Fall 2000 Lecture 14 5


State

We are often interested in circuit


response for
zero state vC (0) = 0
zero input vI (t) = 0

Correspondingly,
zero state response or ZSR
−t
vC = VI − VI e RC 2

zero input response or ZIR


−t
vC = vC (0 ) e RC 3

6.002 Fall 2000 Lecture 14 6


One application of STATE

DIGITAL MEMORY

Why memory?
Or, why is combinational logic insufficient?

Examples
Consider adding 6 numbers on your
calculator
2+9+6+5+3+8

M+

“Remembering” transient inputs

6.002 Fall 2000 Lecture 14 7


Memory Abstraction
A 1-bit memory element
The
6.004
d IN view $

store M The
NEC
d OUT View ¥

Remembers input when store goes high.


Like a camera that records input (dIN) when the
user presses the shutter release button.
The recorded value is visible at dOUT .

d IN

store

d OUT remembers the 1


6.002 Fall 2000 Lecture 14 8
Building a memory element …
A First attempt

dIN dOUT
* storage
C node
store

6.002 Fall 2000 Lecture 14 9


Building a memory element …
A
dIN vC d
* OUT

store = 1
C

dIN vC d
* OUT

store = 0
C
vC RL
5V
Stored value leaks away VOH
t
−t
T
from 2
RL C
vC = 5 ⋅ e
VOH
T = − RLC ln
5
store pulse width >> RON C

6.002 Fall 2000 Lecture 14 10


Building a memory element …
B Second attempt buffer

dIN dOUT
*
RIN
C buffer
store
Input resistance RIN
VOH
T = − RIN C ln
5
RIN >> RL
Better, but still not perfect.

Demo

6.002 Fall 2000 Lecture 14 11


Building a memory element …
C Third attempt buffer + refresh
store

dIN dOUT
*
C
store
Does this work?

No. External value can


influence storage node.

6.002 Fall 2000 Lecture 14 12


Building a memory element …

D Fourth attempt buffer + decoupled


refresh

store

dIN dOUT
*
C
store
Works!

6.002 Fall 2000 Lecture 14 13


A Memory Array
store IN
4-bit memory
Address
OUT

Decoder
A d IN
00 S M
d OUT

B d IN A
01 S M
d OUT
a0 a1
2
Address d IN
C B
10 S M
d OUT

D d IN C
11 S M
d OUT

IN store
OUT
D

6.002 Fall 2000 Lecture 14 14


Truth table for decoder

a0 a1 A B C D
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1

6.002 Fall 2000 Lecture 14 15


Agarwal’s top 10 list on memory

10 I have no recollection, Senator.


9 I forgot the homework was due today.
8 Adlibbing ≡ ZSR
7 I think, therefore I am.
6 I think that was right.
5 I forgot the rest …

6.002 Fall 2000 Lecture 14 16