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CIRCUITS AND

6.002 ELECTRONICS

Energy, CMOS

6.002 Fall 2000 Lecture 23 1


Review
„ VS
RL
2
vO VS
vI P=
RL + RON
RON

„ T1: closed open


T2: open R closed
1

S1 S2
VS +
– C R2

1
T = T1 + T2 =
f
2
P = CVS f

Reading: Section 11.5 of A & L.

6.002 Fall 2000 Lecture 23 2


Review VS
RL
Inverter —
vO
vI RON C

1
Square wave input T= RL >> RON
2 f
VS 2 T
P= + CVS f >>" RC"
2 RL 2
Demo time constant
P STATIC P DYNAMIC
independent of f. related to switching
MOSFET ON half capacitor.
the time.
In standby mode,
In standby mode, half fÆ0,
the gates in a chip can so dynamic power is 0
be assumed to be on.
So P STATIC per gate is
still VS2 .
2RL

6.002 Fall 2000 Lecture 23 3


Review
2
VS 2
P= + CVS f
2 RL
Chip with 106 gates clocking at 100 MHz
C = 1 f F, RL = 10 KΩ , f = 100 × 10 6 , VS = 5 V
⎡ 5 2
−15 6⎤
P = 10 ⎢
6
+ 10 × 5 × 100 × 10 ⎥
2

gates ⎣ 2 × 10 × 10
3

= 10 6 [1.25 milliwatts + 2.5 μ watts ]
1.25KWatts + 2.5Watts
problem ! not bad

• independent of f • αf
• also standby power • αVS2
(assume ½ MOSFETs reduce VS
ON if f Æ 0) 5VÆ1V
• must get rid of this! 2.5VÆ150mW

6.002 Fall 2000 Lecture 23 4


How to get rid of static power
Intuition:

VS VS
RL
i RL
vO high
vI high vO low vI low
MOSFET
RON off

idea !

VS

vI high vO low

6.002 Fall 2000 Lecture 23 5


New Device PFET

• N-channel MOSFET (NFET)

D
on when vGS ≥ VTN
G off when vGS < VTN
e.g. VTN = 1V
S

• P-channel MOSFET (PFET)


S
on when vGS ≤ VTP
G off when vGS > VTP
e.g. VTP = -1V
D 5V
ON when
less than 4V

6.002 Fall 2000 Lecture 23 6


Consider this circuit:
VS

S
PU = pull up
G D
vI vO
+ D
– G PD = pull down
S

works like an inverter!


IN OUT

6.002 Fall 2000 Lecture 23 7


Consider this circuit:
works like an inverter!
IN OUT

vI = 5V (input high) vI = 0V (input low)

VS = 5V VS = 5V

RON p

vO vO
+ +
vI = 5V = 0V vI = 0V = 5V
– RON n –

Complementary
Called “CMOS logic”
MOS
(our previous logic was called “NMOS”)

6.002 Fall 2000 Lecture 23 8


Key: no path from VS to GND!
no static power!
Let’s compute P DYNAMIC
VS
vI
T

vI vO
t
C f =
1
T

closed for closed for


vI low vI high
RON p

VS +
– C RON n

From
2
P = CVS f

6.002 Fall 2000 Lecture 23 9


For our previous example —
C = 1 f F, VS = 5 V , f = 100 MHz , 1
2
P = CV S f
− 15
= 10 × 5 2 × 100 × 10 6
= 2 . 5 μwatts per gate
P = 2 . 5 μwatts for 10 6 gate chip

Gates f P “keep
100 ~2.5 all
106 MHz watts Pentium? else
same”
300 ~15
2x106 MHz watts PII?
600 ~30
2x106 MHz watts PII?
~240
s p !
8x106 1.2 GHz watts
~1875
PIII?
ga
25x106 3 GHz watts PIV?

6.002 Fall 2000 Lecture 23 10


How to reduce power

A VS 5V Æ 3V Æ 1.8V Æ 1.5V
~PIV Æ 170 watts Æ better, but high

and use big heatsink

B Turn off clock when not in use.


C Change VS depending on need.
Æ Æ next time:
power supply

6.002 Fall 2000 Lecture 23 11


CMOS Logic
NAND:
VS
A B Z
0 0 1
A B 0 1 1
1 0 1
1 1 0
Z
A

5V 5V

0V S 5V S
on off
G D G D

6.002 Fall 2000 Lecture 23 12


In general, if we want to implement F

VS e.g. F = A ⋅ B = A + B
short short when
when F A = 0 or B = 0,
is true,
else open open otherwise
A
Z
B short
when F short when
is true, A · B is true,
else open else open

m b er
reme gan’s law
eM o r
D

6.002 Fall 2000 Lecture 23 13