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Agenda
Introduction Verilog Basic Concepts Modeling for Synthesis Verilog Constructs to Gates Modeling Examples Advanced Topics
Mohamed Shalan
Verilog Course
Agenda
Introduction Verilog Basic Concepts Modeling for Synthesis Verilog Constructs to Gates Advanced Topics
Verilog Course
Mohamed Shalan
A Hardware Description Language (HDL) is a highlevel programming language that offers special constructs with which you can model microelectronic circuits. HDLs are mainly used for:
Describe the operation of a circuit at various levels of abstraction (the behavior of a circuit, the function of a circuit, the structure of a circuit, ) Describe the timing of a circuit Express the concurrency of circuit operation
Mohamed Shalan
Verilog Course
You can design at a high implementation-independent level You can delay decisions on implementation details You can easily explore design alternatives You can solve architectural problems before implementation You can automate mapping of your high-level description to a technology-specific implementation You can re-use earlier design components You can move your design between multiple vendors and tools You can more quickly capture your design intent You can more easily manage your design data
Mohamed Shalan
Verilog Course
What is Verilog?
Verilog is a Hardware Description Language: You can describe digital electronic systems at multiple levels of abstraction
You can model the timing of the systems You can express the concurrency of the system operation You can test the systems
Mohamed Shalan
Verilog Course
Verilog History
1995 2001
Gateway Design Automation developed Verilog Verilog-XL released by Gateway Design Automation First Verilog synthesis tool released by Synopsys Cadence acquired Gateway Cadence released Verilog to the public domain. Open Verilog International (OVI) formed to: (1)Evolve and maintain Verilog and (2) Promote the use of Verilog IEEE ratified the Verilog LRM (Std. 1364) IEEE updated the Verilog LRM
Verilog Course
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Verilog Applications
System architects doing high level system simulations Verification engineers writing advanced tests for all levels of simulation ASIC and FPGA designers writing RTL code for synthesis Library developers describing ASIC or FPGA cells, or higher level components
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Verilog Course
Levels of Abstractions
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Behavioral
Describes a system by the flow of data between its functional blocks Defines signal values when they change Describes a system by the flow of data and control signals between and within its functional blocks Defines signal values with respect to a clock Describes a system by connecting predefined components Uses technology-specific, low-level components when mapping from an RTL description to a gate-level netlist, such as during synthesis
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Structural
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The behavioral level describes the behavior of a design without implying any specific internal architecture.
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The RTL (functional) level describes the design architecture in sufficient detail that a synthesis tool can construct the circuit.
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RTL and gate-level library components RTL functional submodule descriptions Structural system netlist Behavioral system testbench
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VHDL was developed to provide a consistent modeling language for documentation of digital systems. Verilog has been developed and will continue to evolve to address the needs of the design community. Verilog is based on C and VHDL is based on ADA. Verilog is mainly being used in Japan and the USA, while VHDL is very popular in Europe.
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Agenda
Introduction Verilog Basic Concepts Modeling for Synthesis Verilog Constructs to Gates Advanced Topics
Verilog Course
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Verilog Modules A Simple Verilog Example Verilog Data Types Verilog Operators Verilog Primitives
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The Verilog module is the basic building block of your design. Start a Verilog module with the module keyword and end with endmodule.
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Module Ports
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Module Ports
If output ports hold their value, they must be declared as reg. It is legal to connect width mismatched ports together. Some ports can be left unconnected.
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Module Ports
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Module Instances
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TestBench
Testbench Template
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Instantiating a Submodule
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Procedural Blocks
The simulator starts executing all procedure blocks at time 0 The simulator executes all procedural blocks concurrently The simulator executes initial blocks once and always blocks continually
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Applying Stimulus
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Among the built-in system tasks and functions that Verilog provides are:
The $time system function returns the current simulation time The $monitor system task displays the values of the listed arguments at the end of any time unit in which any of the arguments change value
For example:
$monitor($time, o, in1, in2); $monitor($time,, out,, a,, b,, sel); $monitor($time,, %b %h %d, sig1, sig2, sig3);
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Nets
Represent physical connection between devices
Registers
Represent abstract storage elements
Module parameters
Configure module instances
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Nets
Nets are continuously driven by the devices that drive them. Continuous assignments, primitives, and registers can drive nets. The simulator automatically propagates new driver values into the net.
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Net Types
The Verilog language offers specific net types for specific technologies:
wire, tri For standard interconnection wires (default) supply1, supply0 For power or ground rails wor, trior For multiple drivers that are Wire-ORed wand, triand For multiple drivers that are Wire-ANDed trireg For nets with capacitive storage. It maintains its last value when all of its drivers go to the high impedance state. tri1, tri0 For nets that pull up or down when not driven
The simulator assumes an undeclared signal in an instance port map to be a single-bit net of type wire.
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Verilog Course
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Declaring Nets
Declare the net type You can optionally declare a [MSB:LSB] range You can optionally declare a net delay You can declare multiple nets of the same type, range, and delay
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Conflict Resolution
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Registers
A register maintains its value between discrete assignments. You make assignments to registers in procedural code blocks. Use registers to model synchronous hardware and apply testbench stimulus.
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Register Types
integer Signed 32-bit integer variable real Signed double precision floating-point variable reg Unsigned storage of varying bit width time Unsigned 64-bit integer variable
Verilog register data types do not imply structural storage elements as implemented in hardware!
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Declaring Registers
You can optionally declare a [MSB:LSB] range for the reg type You can optionally declare an array of integer, reg, and time types You can declare multiple registers of the same type and range Here are some examples of register declarations:
reg a; // A scalar reg reg [3:0] v; // A 4-bit vector reg reg [1:8] m,n; // Two 8-bit regs
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Module Parameters
A parameter is an untyped constant You can use a parameter anywhere that you can use a constant or literal You can change the module parameters on an instance-by instance basis
module mod1(out,in1,in2); . . . parameter cycle = 20; parameter prop_del = 3; parameter setup = cycle/2 - prop_del; parameter width = 8; parameter x_word = 16bx; parameter file = "/usr1/team/design/mem_file.dat"; . . . wire [width-1:0] w1; // A wire declaration using parameter . . . endmodule
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Use the defparam statement to override a module parameter: defparam parameter_reference new_parameter_value module mod1(out,in1,in2); . . . parameter cycle = 8, real_constant = 2.039, x_word = 16bx, file = "/usr1/team/design/mem_file.dat"; . . . endmodule
module test; . . . mod1 I1 (out,in1,in2); defparam I1.cycle = 6, I1.file = "./mem_file.dat"; . . . endmodule Verilog Course Mohamed Shalan
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Follow these rules when choosing between net and register data types:
An input or inout port must be a net An output port can be a register data type A signal assigned a value in a procedural block must be a register data type
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You make a procedural assignment to a net You connect a register to an instance output You declare a module input port as a register
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Verilog Memories
You can also declare arrays of integer and time data types:
integer int_array [0:1]; // array of 2 integers time time_array [8:1]; // array of 8 time variables
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Memory Addressing
You can only access one word of memory at a time. Access the word by indexing into the memory array.
module mems; reg [8:1] mema [0:255]; // memory "mema" reg [8:1] mem_word; // temporary reg "mem_word" . . . initial begin // Display contents of the 6th memory address $displayb(mema[5]); // Display the MSB of the 6th memory word mem_word = mema[5]; $displayb(mem_word[8]); end endmodule
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Verilog Constants
Real and string constants are not supported for synthesis An integer constant can be written in either:
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0 if the leftmost bit of the literal is 0 or 1 Z or X (respectively) if the leftmost bit of the literal is Z or X
It zero-extends operands to matching sizes before operating on them It truncates or zero-extend high-order RHS bits to meet the LHS size It performs bitwise assignments of signed values to unsigned registers
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Concatenation Operator {}
module concat; reg [7:0] a,b,c,d,y; initial begin a = 8'b00000011; b = 8'b00000100; c = 8'b00011000; d = 8'b11100000; y = {a[1:0],b[2],c[4:3],d[7:5]}; // 11111111 end endmodule
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Replication Operator
The replication operator ({n{}}) replicates an expression a fixed number of times to form a new vector quantity.
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Negation Operators
The logical negation operator (!) produces a 0, 1, or X scalar value. The bitwise negation operator (~) inverts each individual bit of the operand.
A = ! 4b0000; // 1 A = ~4b0000; // 4b1111
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The unary reduction operators (&, |, ^, ^~) produce a 0, 1, or X scalar value. They operate across all bits of a vector.
A = &4'b1110; A = |4'b1110; A = ^4'b1110; // 0 // 1 // 1
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Arithmetic Operators
The (+, -) operators take precedence when used as unary operators Integer division discards any remainder A modulus operation retains the sign of the first operand An unknown operand produces an unknown result Assignment of a signed value to an unsigned register is 2s-complement
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Shift Operator
The shift operators (<<, >>) shift the left operand left or right the number of times given by the right operand. The simulator treats the right operand as unsigned (-2 is +4294967293). If the right operand is unknown, the simulator sets the result unknown.
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Relational Operators
The relational operators (<, <=, >=, >) produce 0, 1, or X scalar values. The relational operators all have the same precedence. An unknown operand may produce an unknown result.
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Equality Operators
The logical equality operator (==) does not perform a definitive match for Z or X. The case equality operator (===) does perform a definitive match for Z or X (not synthesizable). All equality operators have the same precedence.
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Bit-Wise Operators
The bit-wise operators (&, |, ^, ^~) operate on each individual bit of a vector. Unknown bits of an operand do not necessarily produce unknown results.
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Logical Operators
An operand is logically false if all of its bits are 0 An operand is logically true if any of its bits are 1
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Conditional Operator
The conditional operator (?:) selects from two operands, based on a third.
conditional_expression ? true_expression : false_expression
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Conditional Operator
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Operator Precedence
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Verilog Primitives
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Verilog Primitives
Some Primitive Pins Are Expandable. The and, nand, or, nor, xor, and xnor primitives permit one or more inputs, and one output. The buf and not primitives permit one input, and one or more outputs.
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Verilog Primitives
Verilog offers 4 conditional primitives. Conditional primitives drive a high impedance state when disabled.
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Verilog Primitives
The "r" version of gates are "resistive" versions of the primitives. Resistive primitives drop one strength-value from input to output.
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Agenda
Introduction Verilog Basic Concepts Modeling for Synthesis Verilog Constructs to Gates Advanced Topics
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Combinational logic: The current state of the output can be determined solely by the current state of the inputs.
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Continuous Assignment
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Continuous Assignment
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Sensitivity Lists
Good coding practice means you complete the sensitivity list. The synthesized output may simulate differently than the RTL description.
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Conditional Statements
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In nested if sequences, every else is associated with the closest previous if at the same nesting level. Not every if will necessarily be associated with an else, though:
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case Statements
case ( expression ) case_item ... endcase
The case statement may sometimes be more readable than if-else statement. The Verilog case statement automatically breaks after the first match.
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case Statements
case casex
z and x are considered as dont care ? can be used instead of z or x z is treated as dont care ? can be used instead of z
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casez
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Conditional Statements
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Conditional Statements
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Conditional Statements
Naturally complete conditional statements imply combinational logic. Incomplete conditional statements imply state storage.
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Conditional Statements
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Inferring Latches
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Conditional Statements
Naturally complete conditional statements imply combinational logic. Incomplete conditional statements imply state storage. Default complete conditional statements imply combinational logic.
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Conditional Statements
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Loop Statements
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Loop Statements
Only the for-loop is supported for synthesis. for-loop is implemented by unrolling. for-loop bounds should be constant for synthesis.
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Verilog Registers
If the current state of the output can be determined by the current state of the inputs:
Declare a Verilog reg to satisfy the Verilog semantics rules The Verilog reg keyword does not by itself imply sequential logic
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Verilog Registers
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Verilog Registers
If the current state of the output cannot be determined by the current state of the inputs:
Declare a Verilog reg to satisfy the Verilog semantics rules The Verilog reg keyword does not by itself imply sequential logic The synthesis tool infers a latch to hold the output state
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Verilog Registers
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Sequential logic: The current state of the output cannot be determined solely by the current state of the inputs. This implies internal state storage.
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Verilog Registers
The synthesis tool can remove a Verilog reg you use in a synchronous block. It will remove a register you write and then read in the same clock cycle. The Verilog reg keyword does not imply sequential logic.
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Verilog Registers
The synthesis tool cannot remove a register you write and read in different clock cycles.
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Modeling Resets
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Blocking Assignment
Evaluated and assigned in a single step Execution flow within the procedure is blocked until the assignment is completed Evaluations of concurrent statements in the same time step are blocked until the assignment is completed
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Non-Blocking Assignment
The right-hand side is evaluated immediately The assignment to the left-hand side is postponed until other evaluations in the current time step are completed
Execution flow within the procedure continues until a timing control is encountered (flow is not blocked)
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Non-Blocking Assignment
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Non-Blocking Assignment
Myth: Making multiple nonblocking assignments to the same variable in the same always block is undefined Truth: Making multiple nonblocking assignments to the same variable in the same always block is defined by the 1364 Verilog Standard
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Guideline #1: Sequential logic - use nonblocking assignments Guideline #2: Latches - use nonblocking assignments Guideline #3: Combinational logic in an always block - use blocking assignments Guideline #4: Mixed sequential and combinational logic in the same always block - use nonblocking assignments Guideline #5: Do not mix blocking and nonblocking assignments in the same always block Guideline #6: Do not make assignments to the same variable from more than one always block
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FSM
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Latched Logic
Method 1
wire[7:0] out; assign out= EN ? In : out;
Method 2
always @(EN or in) if(EN) out=in;
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Efficient Comparison
Equality operators are implemented more efficiently (use = & !=) Avoid threshold comparisons, except where resources can be shared (do not use <=) Use case instead of if for few branches consisting of many consecutive cases
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Do not Forget to
Use blocking (=) for combinatorial logic and nonblocking (<=) for sequential logic Know whether you have prioritized or parallel conditions Completely specify all branches of all conditional statements Initialize output of conditional statements prior to defining the statements Don't instantiate gates unless you have to: make the code technology independent. Use for-loops only for bit-wise operations that can only be described one bit at a time
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Agenda
Introduction Verilog Basic Concepts Modeling for Synthesis Verilog Constructs to Gates Advanced Topics
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Continuous Assignments Procedural Assignments Operators Selection Conditional Operator/Statements For-loop Multi-Phase Clocks
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A continuous assignment statement presents, in hardware, logic that is derived from the expression on the right-hand-side of the assignment
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Equality Operators
z = A != B
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Shift Operator
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Shift Operator
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Conditional Operator
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Inferring Latches
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casex Statement
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Parallel Case
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For-loop
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Multi-Phase Clocks
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Resource Sharing
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Resource Sharing
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Common Sub-expressions
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Using Parentheses
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Using Parentheses
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Agenda
Introduction Verilog Basic Concepts Modeling for Synthesis Verilog Constructs to Gates Advanced Topics
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Advanced Topics
Annotating SDF Timing Programming Language Interface (PLI) Verilog 2001 System Verilog
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A silicon vendor simulation library typically contains estimated intrinsic timing. For accurate timing simulation you need additional data:
You also need to simulate fast clock with slow data and slow clock with fast data. Most event simulators cannot directly do this.
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SDF provides a tool-independent, uniform way to specify timing information. It can specify absolute or incremental delays (which can be conditional), timing checks (which can also be conditional), and timing constraints
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SDF Example
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Advanced Topics
Annotating SDF Timing Programming Language Interface (PLI) Verilog 2001 System Verilog
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PLI
Designers can customize the Verilog HDL by adding new system tasks and functions. The PLI provides a set of interface routines to:
Write to the internal data structures Read from the internal data structures Extracts information about the simulation Environment
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Overview
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Uses of PLI
PLI can be used to define additional system tasks and functions. Typical examples are:
Monitoring tasks Stimulus tasks Debugging tasks Complex operations that can not be done with standard Verilog constructs
PLI can be used to extract design information such as: hierarchy, connectivity, fanout, number of elements of certain type, etc.,
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PLI Example
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PLI Flow
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Internal Representation
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Internal Representation
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Access routines
Reads and writes data structures Starts with acc_ Pass data between Verilog/User tasks (in both directions) Starts with tf_
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Utility routines
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Access Routines
Module instances, module ports, module pinto-pin paths, intermodule paths Top-level modules Primitive instances Nets, registers, parameters Integer, time and real variables Timing checks Events
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Access Routines
Include acc_user.h On starting call acc_initialize() On finishing call acc_close() Access objects using their handles
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Example
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Utility Routines
Get information about the Verilog system task invocation Get argument list information (tf_nump() ) Get value of argument (tf_getp() ) Pass back a new values of arguments Monitor changes in values of arguments Get information about simulation time and events Do long arithmetic Display messages Halt, restore and terminate simulation (tf_dostop() , tf_dofinish() )
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Advanced Topics
Annotating SDF Timing Programming Language Interface (PLI) Verilog 2001 System Verilog
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Verilog-2001
Final draft completed March 1st, 2000 The final IEEE balloting process completed in December, 2000 The official standard is IEEE Std. 1364-2001
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Make Verilog even easier to use Correct errata and ambiguities Maintain backward compatibility existing models will work with the new standard Ensure that EDA vendors will implement all enhancements!
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Higher level, abstract system level modeling Intellectual Property (IP) modeling Greater timing accuracy for very deep submicron
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This is not really a language or modeling change register is not a reserved word; it is just a term Since its inception in 1984, Verilog manuals have used the term register to describe a class of data type:
reg (unsigned variable), integer (signed variable), real (double precision variable), etc.
Register is a hardware term for storage elements Verilog variables do not imply hardware registers
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Verilog Configuration
Configurations specify which module source code to use for each instance of a module.
With Verilog-1995, it is up to the simulator on how to specify which model version should be used for each instance
Verilog model source code does not need to be modified in order to change the design configuration!
Verilog source code does not need to be modified when a design is moved to a different physical source location!
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Verilog Configuration
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Verilog Generate
Use if else and case decisions to control what instances are generated
Provides greater control than the VHDL generate generate , endgenerate , genvar , localparam
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Verilog Generate
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Constant Functions
Same syntax as standard Verilog functions Limited to statements that can be evaluated at compile time Can be called anywhere a constant expression is required
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Constant Functions
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Verilog-2001 adds the capability to use variables to select a group of bits from a vector
The starting point of the part-select can vary The width of the part-select remains constant A +: indicates the part-select increases from the starting point A -: indicates the part-select decreases from the starting point
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Multi-dimensional Arrays
Typically used to model RAM and ROM memories Multidimensional arrays of any variable data type Multidimensional arrays of any net data type
Verilog-2001 adds:
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Verilog-2001 adds:
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Power Operator
Represented by the ** token Works like the C pow() function If either operand is real, a real value is returned If both operands are integers, an integer value is returned
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The @* token indicates that an always procedure is automatically sensitive to any change on any input to that procedure
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Verilog-2001 adds a second syntax style for listing signals in a sensitivity list
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In Verilog-1995:
Verilog assignments zero fill when the left-hand side vector is wider than the right-hand side Unsized integers default to 32-bits wide, which would not fill a vector greater than 32 bits correctly
Verilog-2001 automatically extends a logic Z or X to the full width of the left-hand side
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Sized Parameters
This has been a de-facto standard for many years, but was not in the Verilog-1995 standard An un-sized parameter will default to the size of the initial value assigned to it
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Verilog-2000 permits combining port declarations and data type declarations into one statement
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Verilog-2000 will default to a net data type on the left-hand side of any continuous assignment
The vector width is the size of the right-hand side expression, if not connected to a port of the module In Verilog-1995, the left-hand side must be explicitly declared, if not connected to a port of the module
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The default data type can be changed to another net data type using `default_nettype <data_type>
`default_nettype none Any undeclared signals will be a syntax error Prevents hard-to-debug wiring errors due to a mistyped name none is not a reserved word
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Advanced Topics
Annotating SDF Timing Programming Language Interface (PLI) Verilog 2001 System Verilog
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System Verilog
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Verilog Course
Mohamed Shalan
180
Verilog Course
Mohamed Shalan
181
Datatypes
Verilog Course
Mohamed Shalan
182
Verilog Course
Mohamed Shalan
183
Enumerated Datatypes
Verilog Course
Mohamed Shalan
184
System Verilog
Verilog Course
Mohamed Shalan
185
Structures
Verilog Course
Mohamed Shalan
186
Verilog Course
Mohamed Shalan
187
Process Statement
Verilog Course
Mohamed Shalan
188
Interfaces
Verilog Course
Mohamed Shalan
189
Interfaces
Encapsulates communication Captures Interconnect and Communication Separates Communication from Functionality Eliminates Wiring Errors Enables abstraction in the
Verilog Course
Mohamed Shalan
190
Interfaces
Verilog Course
Mohamed Shalan
191
Interfaces
Verilog Course
Mohamed Shalan
192
Interfaces
Verilog Course
Mohamed Shalan
193