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Ultra-low Power CMOS Front-End Readout ASIC for Portable Digital Radiation Detector*

ZHOU Yunbo ()1, YANG Yu ( )1, SHAN Yueer ()1,2, CAO Huafeng ()1, YANG Bing ( )1,2, YU Zongguang ()1,2,**

1. School of Internet of Things Engineering, Jiangnan University, Wuxi 214122, China; 2. 58th Research Institute, China Electronic Technology Group Corporation, Wuxi 214035, China Abstract: An ultra-low power complementary metal-oxide-semiconductor (CMOS) front-end readout ASIC was developed for a portable digital radiation detector. The ASIC having a charge sensitive amplifier and a semi-Gaussian pulse-shaper was produced using the CSMC 0.5 m DPDM process. The ENC noise of 363 e at 0 pF with a noise slope of 23 e/pF complies with the stringent low noise requirements. The peaking time was 250 ns at a 100 mV/fC conversion gain (detector capacitance is 20 pF). By operating this frontend readout ASIC in the weak inversion region, the ultra-low power dissipation is only 0.1 mW/channel (3.0 V). Simulations and test results suggest that this design gives lower power consumption than the front-end readout ASICs working in the strong inversion and is appropriate for the portable digital radiation detectors. Key words: charge sensitive; shaper; readout circuit; weak inversion region; nested feedback loop

Introduction

Semiconductor radiation detectors are widely used in nuclear power plants, seaports, and some important places of safety inspection[1], with a wide range of radiation sources from 1 eV (near infrared) to 10 MeV (gamma rays)[2]. To collect the charges generated by the detector, a CMOS front-end readout ASICs with relatively high integration density and improved noise performance have been designed[3-5]. Additionally, increasing demand for battery operated portable digital radiation detectors has led to stringent circuit design requirements being more power aware[6,7]. This paper describes an analog readout channel with a charge preamplifier followed by a shaping amplifier

Received: 2011-01-02; revised: 2011-02-10 * Supported by the National Natural Science Foundation of China (No. BK2007026) and the 333 High-Level Personnel Training Project of Jiangsu Province (No. 2007124) ** To whom correspondence should be addressed. E-mail: yuzg58@sina.com

(CR-RC active filter) as shown in Fig. 1. Wide channel devices are used for the input stage since they can be easily biased into the weak inversion region and get some extra advantages[6-9]. MOSFETs working in the weak inversion region can give higher voltage gains. The very low quiescent drain current also reduces the energy consumption. Another advantage is that they have much better linearity than in the strong inversion region. These features have been used in various power-efficient designs. However, some design tradeoffs are still needed to optimize the signal peaking time and the equivalent noise charge (ENC) at the low bias current. The design specifications are listed in Table 1.

The charge sensitive preamplifier, which acts as the interface between the detector pulse signal and the signal processing circuits[3,10], is shown in Fig. 2. In this circuit, the feedback capacitance is used to collect the charge from the detector. Besides, the feedback

158

Fig. 1

Table 1 Main design parameters Parameter Power supply Threshold range Bias current Detector capacitance Feedback capacitance Shaping time Power consumption ENC0 Noise slope Gain Linear dynamic range Value 3.0 V0.3 V 160 mV-200 mV Ibias =1 A Cd =20 pF Cf =150 fF s =200 ns Ptot =0.1 mW 400 e 30 e/pF 100 mV/fC 2 fC-200 fC

The schematic diagram of the CSA in Fig. 3 shows the two-stage cascaded single-ended structure needed to give high DC gain with low power consumption. The gate of MN1 is the preamplifier input while the drain of MN4 is the preamplifier output. The feedback circuit consists of a Y-resistor network and a feedback capacitor, Cf , which is able to provide two discharge channels. The simplified small-signal equivalent circuit of the amplifier without the feedback transistor and capacitor is shown in Fig. 4. The output for this circuit is Q(1 + s ) Vo = (2) Cf (1 + s 1 )(1 + s 2 )

1 =

R12 Cf R3

(3) (4)

2 = R3C1

This means that the output voltage decays exponentially with two time constants.

Fig. 2 Charge sensitive preamplifier

resistor, which is direct current feedback connected, discharges and stabilizes the DC operating point of the amplifier. Consequently, if the DC gain A0 is large enough, the output voltage can be expressed as Q (1) Vo = 1 Cf 1 + sRf Cf Since Cf is constant, Vo is only related to the total charge Q. Therefore, this circuit acts as a charge sensitive amplifier.

Fig. 3 CSA schematic

159

As is well known, MOSFETs operating in the weak inversion region generally have a high DC gain with an ultra low drain current[6]. This design has only 1 A bias current with a W/L=300 m/1 m input MOSFET. The open-loop gain, AV = Vo / Vin , is given by

C C A0 1 s gd1 1 s gd 2 g m1 g m2 AV = s (Cgd 2 + Cd 2 ) [1+ s (Cgd1 + Cd1 )ro1 ] 1+ (1+ sCL ro3 ) g mp2 (5) where the DC gain, A0 , is A0 = g m1 g m2 ro1ro3 (6) and the dominant pole, P1, is 1 P 1 = ro3CL

Fig. 5

Shaper schematic

(7)

In the frequency domain, this amplifier can be analyzed as a second order active band-pass filter limiting the bandwidth from the preamplifier signal which increases the system signal to noise ratio, S/N. Rm mainly affects the zero positions and the shaper transfer function is given by s d Ash (9) H ( s )shaper = 1 + s d 1 + s i

Since the transconductance transistors are working in the weak inversion region, the DC gain can be expressed as a constant given by 1 A0 = (8) 13 ( VT ) 2 Where is the channel-length modulation factor, can be extracted from experimental data. VT is the thermal voltage given by kT/q, k is the Boltzmann constant, T is the temperature, and q is the electronic charge. In addition, the smaller transconductance caused by the low bias current results in the right half plane zero probably occurring at a relatively low frequency. However, this frequency is still greater than 10 MHz so it will not have significant impact on the circuit stability.

1 = Reff Ceff

(10)

2.1 Shaper architecture

The semi-Gaussian shaping amplifier shown in Fig. 5 is based on the CR ( RC )n principle[3]. n = 1 was chosen to reduce the power consumption. In this circuit, Cc is the coupling capacitance and transistor NM2 considered as a split diode is the active feedback resistance RfS . To avoid short-circuiting this line, the adjustable resistor Rm is placed in series with the feedback capacitor CfS . This structure changes the reactance phase characteristics of the feed-forward network.

where d is the differentiator time constant, i is the integrator time constant, Ash is the shaper DC gain, and s is the shaper peaking time. The resulting output signal is a narrow pulse suitable for further processing with operating bandwidth as the most crucial factor to minimize the shaper noise with narrower bandwidths giving less noise. The bandwidth is narrowed by setting d = i . An excessively narrow bandwidth leads to undershoot in the output pulse, which makes the signal difficult to be further processed[4]. Different output overshoots are shown in Fig. 6. The undershoot can vary from 0% to 5% of the effective signal amplitude depending on the shaper bandwidth. As shown in Fig. 6, an increase of the dominant pole to obtain a narrow bandwidth results in output overshoot. There is no undershoot when capacitor CfS is 1.152 pF and CC is 17.28 pF. The dimensions of NMOS device NM2 biased in the weak inversion region are W/L=2.5 m/60 m. As shown in Fig. 6, Acl is the close-loop gain of the simplified small-signal equivalent circuit.

160

in the output stage. A long channel NNOS transistor is used as the feedback resistor for adjusting the capacitance feedforward phase using an external control voltage. The circuit diagram is given in Fig. 8.

(a)

Fig. 8

(b) Fig. 6 Different output signal undershoots and their AC responses of different undershoots

This design has only one adjustable resistance, Rm , in the nested feedback circuit, so the design significantly reduces system thermal noise and the circuits chip area. The shaping amplifier provides the pole-zero can1 CL cellation at the output, when Rm 1 + . The g m2 Cm open-loop gain, AVS, of the simplified small-signal equivalent circuit without the feedback resistor and capacitor is given by g m1 g m2 R1RL AVS = (11) (1 + sCm R1 RL g m2 )(1 + sC1 Rm ) and 1/ is given as 1 (1 + sCfS Rm )(1 + sCc RfS ) = (12) 1 + sCfS RfS where CL is the capacitive load and Rf the resistor load at the shaping amplifier output. The small signal AC simulation results in Fig. 9 showed that the system is stable. At low frequencies, CC , CfS , and Cm are open and the closed-loop gain is not affected by the feedback network. A phase shift of 135 at the pole is due to setting Cm R1 RL g m2 within a

2.2

The design uses a two-stage amplifier structure. A typical 2-stage MOS differential amplifier is shown in Fig. 7 with a PMOS differential pair with a current mirror load. Simulations give a voltage gain of 93 dB with a wide channel differential pair having W= 100 m and L=1 m. This gain occurs at a bias current of about 1 A, placing the input transistors in the weak inversion region.

However, the two-stage amplifier structure can give the shaping circuit additional poles, affecting the system stability. As described earlier, this amplifier also uses capacitance Cm for the Miller compensation

161

decade of Cc RfS . The rate-of-closure of 20 dB/decade at f CL (for a loop gain of 0 dB) occurs when a pole is added at CfS RfS by adjusting the feedback network. Placing RfS at least a decade below Rm keeps the phase angle from decreasing further.

Fig. 11, the maximum pulse cycle does not exceed 2 s with a peaking time constant of 250 ns.

Noise Analysis

The front-end readout ASIC noise performance is usually expressed as the ENC, which is defined as the ratio of the total integrated root mean square noise at the pulse shaper output to the signal amplitude given by one electron charge[1-5]. A significant effect that distinguishes weak inversion region operation from strong inversion region operation is the low frequency noise behavior. In the weak inversion region, the low frequency noise is dominated by 1/f 2 noise (where f is the frequency)[7,11,12]. The equivalent 1/f 2 input noise source is given by Kf2 1 2 Veqi = (13) 2 2 CoxWL f 1+ gm fc

where K f 2 is the 1/f 2 noise coefficient of the CMOS device working in the weak inversion region[11], g m is the transconductance, and f c is the corner frequency. The ENC 2f 2 due to the 1/f 2 noise is[13] K f 2 f c2 3 1 3 n !e 2 n s ENC2f 2 = , B n + (14) 2 2 2 n 2 n +3 2 CoxWL q gm where B( x, y ) is the beta function.

Fig. 10 output

The simulated CSA transient response is given in Fig. 12 for input signals of 2.67 fC, 15.35 fC, 28.03 fC, 40.71 fC, and 106.8 fC applied to a 20 pF capacitor at the preamplifier input.

Simulations were performed on a synopsys hspice_vA2008.03 simulator using the SPICE MODEL parameters for CSMC CMOS 0.5 m. The transient response result of the CSA for injected charges of about 6 fC ( Cd = 20 pF) is shown in Fig. 10. The design gives a conversion gain of 100 mV/fC. Unlike a semi-Gaussian pulse, the CSA output waveform has two different attenuation time constants, 1 and 2 . The pulse quickly returns to the baseline because of the two different discharge paths formed by R1 , R2 , and R3 . A typical transient shaping amplifier result is shown in Fig. 11 for an injected charge of 6 fC. As shown in

Fig. 12 Transient CSA output response for five injected charge signals

The transient shaping amplifier response is given in Fig. 13 for the same five injected charge signals. The results show that the system is very linear for 2 MeV signals. If the input signal is substantially increased, cut-off distortion may occur and the system will go into a large-signal operating state. However, this system has good linearity over a wide range, so the cutoff should not affect the timing performance.

162

Tsinghua Science and Technology, April 2011, 16(2): 157-163 Table 2 CMOS process (m) Ref. [4] 0.35 Ref. [1] 0.50 Ref. [5] 0.60 This paper 0.50 Source Performance comparisons Peaking time (s) 1.81 1.00 2.00 0.25 Power (mW) 1.0 4.0 2.0 0.1 ENC0 (e) 382 110 351 363 Noise slope (e/pF) 21.0 15.0 4.8 23.0

5 Conclusions

An ultra-low power readout circuit operating in the weak inversion region was developed for portable digital radiation detectors. The circuit implemented using the CSMC 0.5 m DPDM standard CMOS process had a whole channel power consumption of 0.1 mW with a gain of 100 mV/fC. For an input charge of 6 fC, the detector capacitance is equal to 20 pF and the peaking time is less than 250 ns, which is suitable for portable electronic dosimeters.

References

[1] Zhang Yacong, Chen Zhongjian, Lu Wengao, et al. A fully integrated CMOS readout circuit for particle detectors. Chinese Journal of Semiconductor, 2007, 28(2): 182-188. [2] Perillo E, Cola A, Donati A, et al. An overview on performance and possible applications of X- and gamma-ray semiconductor detector irradiated at various impinging angle. IEEE Transaction on Nuclear Science, 2004, 51(3): 1216-1223. [3] Sansen W M C, Zhong Yuanchang. Limits of low noise performance of detector readout front ends in CMOS technology. IEEE Transaction on Circuits and Systems, 1990, 37(11): 1375-1382. [4] Noulis T, Siakos S, Sarrabayrouse G, et al. Advanced low-noise X-ray readout ASIC for radiation sensor interfaces. IEEE Transactions on Circuits and Systems, 2008, 55(7): 1854-1862. [5] Noulis T, Deradonis C, Sarrabayrouse G, et al. Programmable OTA-based CMOS shaping amplifier for X-rays spectroscopy. In: Proceedings of IEEE PRIME. Otranto (Lecce), Italy, 2006: 173-176. [6] Comer D J, Comer D T. Using the weak inversion region to optimize input stage design of CMOS Op Amps. IEEE Transactions on Circuits and Systems, 2004, 51(1): 8-14. [7] Gupta S K, Raychowdhury A, Roy K. Digital computation in subthreshold region for ultralow-power operation: A device-circuit-architecture codesign perspective. Proceedings

The optimized noise performance is presented in Fig. 14 from which the ENC can be calculated. Considering the 100 mV/fC conversion gain of the chip taken from Fig. 10, the ENC is 363 eV for Cd = 0 pF.

Fig. 14

The noise of the front-end readout ASIC has been measured with a digital oscilloscope. The test results are shown in Fig. 15. The discrepancies between the test and theoretical results for the chip were all less than 4.4%.

Fig. 15

The performance of front-end ASICs depends on the model process and structure; therefore, comparisons of different circuits are difficult. Some recent results in the literature are listed in Table 2 for reference.

ZHOU Yunbo () et al.Ultra-low Power CMOS Front-End Readout ASIC of IEEE, 2010, 98(2): 160-190. [8] Comer D J, Comer D T. Operation of analog MOS circuits in the weak or moderate inversion region. IEEE Transactions on Education, 2004, 47(4): 430-435. [9] Salazar F A, Pimentel J C G, Pacheco M A, et al. Micro power CMOS analog cells. In: Proceedings of IEEE on Integrated Circuit Design. Rio de Janeiro, Brazil, 1998: 187-190. [10] Deng Zhi, Kang Kejun, Cheng Jianping, et al. Low-noise CMOS charge-sensitive preamplifier. Journal of Tsinghua University (Sci. & Technol.), 2005, 45(12): 1643-1645. (in Chinese)

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[11] Leyris C, Polorget S, Marin M, et al. Random telegraph signal noise spice modeling for circuit simulators. In: Solid State Device Research Conference 2007 ESSDERC, 37th European. Munich, Germany, 2007: 187-190. [12] Miller D A, Poocharoen P, Forbes L. 1/f noise and RTS (random telegraph signal) errors in comparators and sense amplifiers. In: IEEE Workshop on Microelectronics and Electron Devices 2007 WMED. Santa Clara, CA, USA, 2007: 21-22. [13] Wulleman J. Detector-noise suppression by appropriate CR-(RC)n shaping. Electronic Letter, 1996, 32(21): 1953-1954.

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