You are on page 1of 4


Vlad Anghel1, Chris Bartholomeusz1,2, Gheorghe Pristavu1, Gheorghe Brezeanu1

Politehnica University of Bucharest E-mail:; 2 ON Semiconductor Romania E-mail: AbstractInitial control loop conditions are essential in switching circuits where fault detection blocks are present, in order to avoid permanent fault triggers. Furthermore, multi-channel switching interference may affect circuit functionality and cause additional fault triggers. Error amplifiers aquire the difference between sensed and reference signals and output a correction voltage. We propose a solution which ensures that the initial correction voltage does not determine a perpetual fault condition. The proposed solution is implemented in a current mode buck control loop, which delivers constant current through a load. Keywords: error amplifier, capacitor precharge, fault conditions, CMOS technology, current mode buck controller.

of how it overcomes potential layout-related leakage problems.

The schematic of an error amplifier [1], [2], with increased response time is depicted in Fig. 1.

Error amplifiers (EA) are used in a wide variety of applications, usually as part of a control loop that measures a desired signal, compares it to a reference value and tunes it to meet specifications via feedback. The EA has a floating output voltage, whose value either increases or decreases, based on the positive or negative difference between its inputs respectively. This allows the circuit to find an ideal output voltage that ensures a steady state functioning of the application it was designed for. Depending on the working frequency of the application, the response time of the EA needs to be adjusted so that it generates a corrected output voltage only after a consistent deviation in application behavior has been detected. This response time is obtained via a capacitor that takes time to charge to the desired output value. Capacitor precharge should be considered when designing applications whose initial control loop conditions affect functionality. A solution of integrating this feature into an error amplifier design is offered, as well as an analysis
978-1-4673-0738-3/12/$31.00 2012 IEEE 381

Fig. 1. Schematic of error amplifier with increased response time.

This schematic was integrated into a buck current mode control loop. The control loop application is illustrated in Fig. 2 and presented in [3] and [4]. SW, RL, Lb, Cb and the Schottky diode are external components.

Fig. 2. Error amplifier-based buck control loop application.

The purpose of this application is to provide constant current through RL. When the SW switch is turned ON, inductor current rises. Based on inductor current, the Current Monitor

block outputs 3 voltages. Vpeak goes from logic 0 to logic 1 when the inductor current reaches a preset peak value. This transition resets the latch which commands SW, thus controlling the switch ON time. Vavg corresponds to the average inductor current during switch ON time. The EA compares Vavg with a reference value and generates a correction voltage (VCTRL). The time modulating block determines OFF time proportional to VCTRL [5]. When the inductor current reaches a safety limit, Vfail outputs a FAULT flag which disables the entire control loop for a predefined period of time. This mechanism represents the over-current protection.

block V(VCTRL), this current rises above the safety threshold and the entire loop is shut down. This behavior is repeated indefinitely, as capacitor voltage V(C) always falls to zero during the fault V(FAULT) period. As such, it is necessary for the capacitor to always be precharged when starting the control loop. In order to achieve this requirement, the EA output capacitor precharge technique was implemented as shown in Fig. 4.

Initially, the output voltage of the EA will be close to zero and will tend to grow slowly. This will determine the OFF time generated by the time modulator to be almost zero as well. Thus, the entire buck controller will appear to function mostly in the ON state. Inductor current will continue rising, and will most likely exceed the safety limit before the EA output can reach a significant value and determine proper OFF times. This initial discrepancy will cause the over-current protection block to trigger the power off of the entire control loop for a predefined period of time. During this power off time, Vavg value will fall, determining EA output capacitor discharge, so that VCTRL will once again be close to zero once the loop is restarted. This behavior will trigger constant over-current faults that will prevent the circuit from functioning properly, as illustrated in the simulation in Fig. 3. Simulations were performed in a PSpice environment, using EKV models and a 0.5m CMOS technology.

Fig. 4. Principle schematic of error amplifier with capacitor precharge.

At power-up, when the START signal is set to logic 1, the capacitor is charged at Vinit so that the output voltage will not erroneously trigger the over-current protection. Furthermore, N3 isolates capacitor C from the EA output during the fault period, commanded by the EN signal, so that its charge will not be depleted. The EN signal activates the control loop. These modifications were used when designing a multiple channel current mode buck controller which uses the aforementioned control loop in each channel. All EA output capacitors are precharged when the controller is powered on, although not all channels may be activated immediately afterwards, depending on application requirements.

A layout-based issue was detected, where EA output capacitors would be affected by significantly large leakage currents while the respective channel is disabled. Various applications may delay different channels activation over several orders of magnitude, allowing the leakage current to completely discharge capacitor C. In such a scenario, a channel would not function properly due to permanent over-current protection faults, as previously mentioned.

Fig. 3. Control loop behaviour without capacitor precharge.

In Fig. 3 I(Lb) is the inductor current. As can be seen, because of the low output of the EA


Fig. 5 shows silicon implementation in a 0.5m CMOS technology of a 2-channel current mode buck controller architecture using the control loop from Fig. 2. The second channel exhibits significant capacitor (C from Fig. 2) leakage current, most likely due to its proximity to the large-area output inverter INVchannel1.

. The value obtained for the equal to average leakage current I is 30nA.

Fig. 6. TOFF versus Td and curve fitting of measured results using eq. (3).

Fig. 5. Silicon implementation of 2-channel current mode buck controller.

Measuring the initial off time delay (TOFF) outputted by the time modulating block immediately after channel activation versus delay between separate channels activation yields the results plotted in Fig. 6. Considering EA output having the initial value Vinit set by the precharge, we can calculate the output value after a time delay Td (1) from [6], (1) where I is the average leakage current discharging capacitor C. Equation (1) is used taking into account the fact that the average leakage current I is constant. The time modulating block was designed to have an exponential variation between input voltage and output switching delay, given by equation (2) [5]. (2) By replacing the expression of Vin from (1) into (2), an analytical relationship between TOFF and Td is obtained (3). Design values for Vinit and C are 0,9V and 10pF respectively. Considering [5], T0 is 8,18ns and V0 has a value of 0,175V. Equation (3) can be rewritten in the following form (4):

As expected, the leakage current value induced by one channel onto the other can significantly affect channel performances, up to the point of permanent control loop failure. Further analysis of this matter was performed on an 8-channel current mode buck controller, in the same CMOS technology and using the same control loop as the 2-channel version. The layout of the circuit is depicted in Fig. 7.

Fig. 7. Layout of 8-channel buck controller.

(4) which leads to the fitting results from Fig. 6. Average leakage current I is easily determined because, from (3) and (4), fitting parameter Td0 is

To determine how multiple channels influence each other, measurements were performed on 3 identical chips and the results are depicted in Fig. 8. Measurements consisted of a sequence of power-up, then enabling one channel (initially enabled channel in Fig. 8) and after several seconds enabling another channel and ending with power-down. In some situations, the channel with a delayed enable would not start due to previously mentioned capacitor leakage.


In multiple channel applications, this solution completely overcomes channel to channel interference. Independent of the delay between separate channels activation, the individual initial OFF time of each channel will have a high preset value. Inductor current will not be able to reach excessive values in these conditions, and the over-current protection will not trigger. The 8-channel current mode buck controller was reimplemented in silicon, using the improved EA architecture. Measurements regarding channel influence were reiterated using the same sequence that generated the results from Fig. 8. New results show no channel to channel interference.
Fig. 8. Channel to channel failure influence.

This paper emphasizes the importance of precharging an error amplifiers output capacitor for a specific current mode buck control loop. A design solution for performing initial capacitor precharge was investigated, implemented in a 0,5 m CMOS technology as part of multi-channel control loops and measured. The obtained results show layout-based channel to channel interference, in the form of a 30nA leakage current discharging the capacitor and causing permanent over-current protection faults. A modification that performs an additional precharging operation, during each fault period, was implemented. New measurements show no channel to channel interference. Considering design modifications and the effectiveness of an appropriate precharge architecture, the use of this technique is recommended in all control loop designs that use error amplifiers with increased response time. AcknowledgementsOne of the authors, V. Anghel, acknowledges the support of POSDRU/107/1.5/S/76903. References
[1] [2] [3] R.J. Baker, CMOS Circuit Design, Layout and Simulation 3rd Edition, John Wiley & Sons, 2010. B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001. C. Basso, Switch-Mode Power Supplies, Mc-Graw Hill, 2008. S. Winder, Power Supplies for LED Driving, Newnes, 2008. G. Pristavu, C. Bartholomeusz V. Anghel, G. Brezeanu, Time Modulation The Exponential Way, sent to the International Semiconductor Conference, 2012. P. Gray, P.J. Hurst, S.H. Lewis, R.G. Meyer, Analysis and Design of Analog Integrated Circuits 4th Edition, John Wiley & Sons, 2001.

For example, after power-up, channel 1 is enabled (first row). If channel 2 is enabled, the buck control loop in one of the chips does not function - light grey. If channel 3 is enabled, there are no problems with any of the 3 chips. When enabling channel 4, the control loop does not function in two chips - dark grey. Should channels 5 through 8 be enabled, the control loop does not function for any of the 3 chips - black.

In order to overcome the leakage current issue in multi-channel designs, another capacitor precharge operation is performed during each over-current protection fault, as shown in Fig. 9.

Fig. 9. Block schematic of improved EA.

Signal FAULT is set to logic 1 and enables N5 every time a fault is triggered. Capacitor C is charged by the current source Icharge while the loop is shut down, also compensating for leakage losses. The time modulating circuit will produce a significant OFF time once the loop is restarted, which ensures that any over-current protection faults are not permanently re-triggered.

[4] [5]