You are on page 1of 55

Stick diagrams

CMOS Layers
n-well process p-well process Twin-tub process

n-well process
Gate NMOS NMOS FOX PMOS PMOS

n+

n+

n+

n+

p+

p+

p+

p+

n-well p-substrate

MOSFET Layers in an n-well process

Layer Types
p-substrate n-well n+ p+ Gate oxide Gate (polycilicon) Field Oxide
Insulated glass Provide electrical isolation

Top view of the FET pattern


NMOS NMOS PMOS PMOS

n+

n+

n+

n+

p+

p+

p+

p+

n-well

Metal Interconnect Layers


Metal layers are electrically isolated from each other Electrical contact between adjacent conducting layers requires contact cuts and vias

Stick Diagrams

Stick Diagrams

N+

N+

Stick Diagrams
Objectives:
To know what is meant by stick diagram. To understand the capabilities and limitations of stick diagram. To learn how to draw stick diagrams for a given MOS circuit.

Outcome:
At the end of this module the students will be able draw the stick diagram for simple MOS circuits.
8

Stick Diagrams
VDD VDD

X
X

Stick Diagra m

X Gnd

Gnd

Stick Diagrams
VDD X X X VDD

X Gnd

Gnd

10

Stick Diagrams
VLSI design aims to translate circuit concepts onto silicon. stick diagrams are a means of capturing topography and layer information using simple diagrams. Stick diagrams convey layer information through colour codes (or monochrome encoding). Acts as an interface between symbolic circuit and the actual layout.
11

Stick Diagrams
Does show all components/vias. It shows relative placement of components. Goes one step closer to the layout Helps plan the layout and routing

A stick diagram is a cartoon of a layout.


12

Stick Diagrams
Does not show
Exact placement of components Transistor sizes Wire lengths, wire widths, tub boundaries. Any other low level details such as parasitics..

13

Stick Diagrams Notations


Metal 1 poly ndiff

pdiff
Can also draw in shades of gray/line style.

Similarly for contacts, via, tub etc..

14

Stick Diagrams Some rules


Rule 1. When two or more sticks of the same type cross or touch each other that represents electrical contact.

15

Stick Diagrams Some rules


Rule 2. When two or more sticks of different type cross or touch each other there is no electrical contact. (If electrical contact is needed we have to show the connection explicitly).

16

Stick Diagrams Some rules


Rule 3. When a poly crosses diffusion it represents a transistor.

Note: If a contact is shown then it is not a transistor.


17

Stick Diagrams Some rules


Rule 4. In CMOS a demarcation line is drawn to avoid touching of p-diff with n-diff. All pMOS must lie on one side of the line and all nMOS will have to be on the other side.

18

How to draw Stick Diagrams

19

Stick Diagram
Stick diagrams are a design technique that represent the layout for a device

They are used as an intermediary step between schematic and


layout Here, the detailed layout design rules are simply neglected and the main features (active areas, polysilicon lines, metal lines) are represented by constant width rectangles or simple sticks They can save a lot of time in transistor placement and device minimization

Coloured Stick Diagram Notation


Silicon layers are typically colour coded as follows :

diffusion (device well, local interconnect) polysilicon (gate electrode, interconnect) metal (contact, interconnect) contact windows N well (CMOS devices) This colour representation is used during mask layer definition Translation from circuit format to a mask layout (and vice-versa) is relatively straightforward

From Schematic to Stick Diagram


The schematic for a three input NAND gate looks like this: Notice how the transistors are arranged The three PMOS transistors are connected to power on one end and the output on the other The three NMOS transistors are connected in series with one connected to output and one connected to ground The inputs, A, B and C all connect

to two transistors

From schematic to stick diagram (2)


Stick diagrams represent transistors by active to poly connections and active to metal connections To begin, you will need to draw a couple strips of active, one for PMOS transistors and one for NMOS transistors

From schematic to stick diagram (3)


Now draw a yellow well around the active that represents a p-type transistor and two horizontals blue lines to represent VDD and GND.

From schematic to stick diagram (4)


Refer back to the schematic, notice that every PMOS transistor is connected to VDD and an NMOS transistor connect to ground You should choose the upper blue line as VDD and the lower blue line as GND You might as well label them so that you keep this straight
NMOSs GND VDD PMOSs

From schematic to stick diagram (5)


Now create your gates by placing poly We will share diffusion regions so some of the drains are oriented up and

some are oriented down.


VDD

Notice that the gates of the n-type and


PMOSs

p-type transistors are connected with poly.


NMOSs GND

From schematic to stick diagram (6)


Now its time to interconnect the device. You will probably have to experiment to find the best routing:

Notice that Poly and Metal 1 can overlap Avoid routing signals that are side by side for long lengths. This adds capacitance to the device. Avoid all interconnect overlap if possible. This adds capacitance to the device. Strive for simplicity. This will later provide the smallest and fastest devices. You can use Poly, Metal 2 (M2), and even Active to interconnect your device. But keep in mind, Poly and especially Active adds resistance to you device.

From schematic to stick diagram (7)


To finish the stick diagram, draw the connections between transistors, outputs, VDD and GND The final stick diagram should avoid unnecessary vias M1 can alternate in any direction M2 can be used for vertically straps
PMOSs A B C NMOSs GND Out VDD

From schematic to stick diagram


Following are some points to consider while drawing stick diagrams:

Make VDD and GND horizontal and have them stretch from the left to the right of the cells. This allows the cells to be abutted top to bottom or side by side by overlaying the power lines. It will be helpful to make all of your cells the same height (distance between power and ground) so they will line up better when they are abutted.

Keep your inputs and outputs inside the cell, and try to keep them on M1.
M2 should be reserved for your select lines and clock. Data should flow in metal1 horizontally, and control should flow in M2

vertically. Clearly there will be times that this rule must be broken, but it will
save a lot of confusion and hassle if you do all you can to follow this advice.

From schematic to stick diagram


Following are some points to consider while drawing stick diagrams (cntd).

Use minimum Active. Fully use as much contact area as you have (unless you have a really good reason not to). Some of the Active contacts below are minimum size while they could clearly be larger!

Try to use shared Active regions. An example: Three transistors in series do


not need the M1 and contacts between each of the gates and can all be on one piece of active as shown in the stick diagrams.

Where possible avoid crossing nets. In other words, don't take a M1 line, change to M2, cross M1, change back to M1 and so on. It is a big space waste to do this. Plan ahead and route the signals in a way where this is avoid as often as possible.

31

32

33

34

35

Lambda-based Rules

36

Design Rules

37

Design Rules

38

Design Rules

39

40

Power

Out

C B
Ground

Static CMOS NAND gate

Static CMOS NOR gate

44

Connection label layout

45

VDD, VSS and Output Labels

46

Stick Diagram, Interconnected

47

48

Static CMOS Design Example Layout

Layout 2 (Different layout style to previous but same function being


implemented)

51

Euler Path

52

Euler Path

53

NOR Gate

54

Example
Power

Out

C B
Ground

55