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# PRELIM 1. a. b. c. d. 2. a. b. c. d. 3. a. b. c. d. 4. a. b. c. d. 5. a. b. c. d. 6. a. b. c. d. 7. a. b. c. d. 8. a. b. c. d. Base 10 refers to which number system?

binary coded decimal decimal octal hexadecimal Convert the decimal number 151.75 to binary. 10000111.11 11010011.01 00111100.00 10010111.11 Convert the binary number 1011010 to hexadecimal 5B 5F 5A 5C The number of bits used to store a BCD digit is: 8 1 4 2 The weight of the LSB as a binary number is: 1 2 3 4 Convert the binary number 1001.0010 to decimal. 125 12.5 90.125 9.125 Convert 110010012 (binary) to decimal. 201 2001 20 210 What is the decimal value of the hexadecimal number 777? 191 1911 19 19111

## 9. a(n): a. b. c. d. 10. a. b. c. d. 11. a. b.

If a signal passing through a gate is inhibited by sending a low into one of the inputs, and the output is HIGH, the gate is AND NOR NAND OR Single transistor can be used to build which of the following digital logic gates? NAND gates OR gates NOT gates AND gates The logic gate that will have HIGH or "1" at its output when any one of its inputs is HIGH is a(n): NOT gate AND gate

## c. 12. a. b. c. d. 13. a. b. c. d. 14. a. b. c. d. 15. a. b. c. d. 16. a. b. c. d. 17. a. b. c. d. 18. a. b. c. d. 19.

OR gate How many NAND circuits are contained in a 7400 NAND IC? 1 2 4 8 Exclusive-OR (XOR) logic gates can be constructed from what other logic gates? OR gates only AND gates and NOT gates AND gates, OR gates, and NOT gates OR gates and NOT gates How many truth table entries are necessary for a four-input circuit? 4 8 12 16 A NAND gate has: LOW output when two inputs are low HIGH inputs and a HIGH output LOW inputs and a HIGH output None of the these The basic logic gate whose output is the complement of the input is the: OR gate AND gate INVERTER gate Comparator What input values will cause an AND logic gate to produce a HIGH output? At least one input is HIGH. At least one input is LOW. All inputs are HIGH. All inputs are LOW. Which gates have only one input and one output? XOR and NAND XOR and NOT Buffer and NAND Buffer and NOT Below is an image of a(n) ______ gate.]

a. b. c. d. 20. a. b. c. d. 21. a. b. c. d.

OR XNOR NXS NAND Which of the following statements about NOT gates is true? NOT gates can only be used after OR and XOR gates NOT gates and NOR gates produce the same results A small circle at the end of a gate represents a NOT gate NOT gates usually have 1 input and 2 outputs Which of the gates will have an output of 1 whenever there is zero in the input combination? NOT OR XOR NOR

22. a. b. c. d. 23.

If the 0 and 1 were inputted into a NAND gate, what would be the output? 0 1 0&1 1&1 Below is the truth table for which of the following logic gates?

a. b. c. d. 24.

AND NAND OR XOR Complete the following output sequence for a NAND gate in the truth table below.

a. b. c. d. 25.

1 0 11 2 Complete the following output sequence for an OR gate in the truth table below.

a. b. c. d. 26. a. b. c. d.

0 1 2 None of the above. Which of the following statements are false? The output should be the left side of the algebraic equation Algebraic equations of logic gates are the basics of Boolean equations XOR and XNOR gates cannot be represented by algebraic equations Letters used in algebraic equations are variables and have no set value

27. a. b. c. d.

The algebraic equation X=A XOR AND NOR None of the above

## 28. a. b. c. d. 29. a. b. c. d. 30.

A+B is equivalent to which of the following gates? AND OR XOR None of the above How are NOTs represented in algebraic equations? A slash through the equation A line through the equation A line over the equation A small circle at the end Simplify.

a. b. c. d. 31.

NAND gate OR gate NOT gate XNOR gate Which logic gate represents the following system?

a. b. c. d. 32.

XOR gate XNOR gate OR gate NOR gate The following set of logic gates can be simplified into a __________.

a. b. c. d. e.

Buffer Gate NOR gate AND gate None of the above None of the above

33. a. b. c. d.

The two gates in a half adder circuit are: XOR gate and NAND gate XNOR gate and NAND gate XOR gate and AND gate Two XOR gates

34. a. b. c. d. 35. a. b. c. d. 36. a. b. c. d. 37. a. b. c. d. 38. a. b. c. d. 39. a. b. c. d. 40. a. b. c. d. 41. a. b. c. d. 42. a. b. c. d. 43. a. b. c. d. 44. a. b. c.

A full adder is used to add three binary digits together using: An OR gate and two NOR gates An AND gate and two NOR gates Two half adders connected by an OR gate Two half adders connected by an AND gate Which two inputs are used in a RS flip flop? Repeat and Start Repeat and Set Reset and Set Reset and Stop In what part of computer does RS flipflop being used? to create RAM to start and stop software to do loops none of the above The output of an AND gate with three inputs, A, B, and C, is HIGH when ________. A = 1, B = 1, C = 0 A = 0, B = 0, C = 0 A = 1, B = 1, C = 1 A = 1, B = 0, C = 1 If a 3-input NOR gate has eight input possibilities, how many of those possibilities will result in a HIGH output? 1. 2 7 8 A device used to display one or more digital signals so that they can be compared to expected timing diagrams for the signals is a: DMM spectrum analyzer logic analyzer frequency counter in using IC, what does the term "QUAD" indicates? 2 4 6 8 The output of an OR gate with three inputs, A, B, and C, is LOW when ________. A = 0, B = 0, C = 0 A = 0, B = 0, C = 1 A = 0, B = 1, C = 1 all of the above Which of the following logical operations is represented by the + sign in Boolean algebra? inversion AND OR Complementation How many pins does the 4049 IC have? 14 16 18 20 Which of the following choices meets the minimum requirement needed to create specialized waveforms that are used in digital control and sequencing circuits? basic gates, a clock oscillator, and a repetitive waveform generator basic gates, a clock oscillator, and a Johnson shift counter basic gates, a clock oscillator, and a DeMorgan pulse generator

d. 45. a. b. c. d. 46. a. b. c. d. 47. a. b. c. d. 48. a. b. c. d. 49. a. b. c. d. 50. a. b. c. d. 51. a. b. c. d. 52. a. b. c. d. 53. a. b. c. d. 54. a. b. c. d. 55. a. b. c. d.

basic gates, a clock oscillator, a repetitive waveform generator, and a Johnson shift counter TTL operates from a ________. 9-volt supply 3-volt supply 12-volt supply 5-volt supply Output of a NOR gate is HIGH if ________. all inputs are HIGH any input is HIGH any input is LOW all inputs are LOW The switching speed of CMOS is now ________. competitive with TTL three times that of TTL slower than TTL twice that of TTL The format used to present the logic output for the various combinations of logic inputs to a gate is called a(n): Boolean constant Boolean variable truth table input logic function The power dissipation, PD, of a logic gate is the product of the ________. dc supply voltage and the peak current dc supply voltage and the average supply current ac supply voltage and the peak current ac supply voltage and the average supply current The Boolean expression for a 3-input AND gate is ________. X = AB X = ABC X=A+B+C X = AB + C What are the pin numbers of the outputs of the gates in a 7432 IC? 3, 6, 10, and 13 1, 4, 10, and 13 3, 6, 8, and 11 1, 4, 8, and 11 The output of a NOT gate is HIGH when ________. the input is LOW the input is HIGH power is applied to the gate's IC power is removed from the gate's IC What is the Boolean expression for a three-input AND gate? X=A+B+C X=ABC ABC A\$B\$C Which of the following gates has the exact inverse output of the OR gate for all possible input combinations? NOR NOT NAND AND The output of an exclusive-OR gate is HIGH if ________. all inputs are LOW all inputs are HIGH the inputs are unequal none of the above

## 56. a. b. c. d. 57. a. b. c. d. 58. a. b. c. d. 59. a. b. c. d. 60. a. b. c. d. 61. a. b. c. d. 62. a. b. c. d.

How many input combinations would a truth table have for a six-input AND gate? 32 48 64 128 The NOR logic gate is the same as the operation of the ________ gate with an inverter connected to the output. OR AND NAND none of the above Which of the following equations would accurately describe a four-input OR gate when A = 1, B = 1, C = 0, and D = 0? 1 + 1 + 0 + 0 = 01 1+1+0+0=1 1+1+0+0=0 1 + 1 + 0 + 0 = 00 The basic types of programmable arrays are made up of ________. AND gates OR gates NAND and NOR gates AND gates and OR gates Which of the following is not a basic Boolean operation? NOT OR XOR NOR What is the Boolean expression for a four-input OR gate? Y = A + B + C+D Y = A B C D Y=A B C D Y=A \$ B \$ C \$ D how many entries would a truth table for a four-input NAND gate have? 2 8 16 32

63. The Boolean expression for a 3-input OR gate is ________. a. X=A+B b. X=A+B+C c. X = ABC d. X = A + BC 64. a. b. c. d. From the truth table for a three-input NOR gate, what is the only condition of inputsA, B, and C that will make the output X high? A = 1, B = 1, C = 1 A = 1, B = 0, C = 0 A = 0, B = 0, C = 1 A = 0, B = 0, C = 0

65.) Convert (1000100)2 to decimal. a.) (59)10 b.) (60)10 c.) (63)10 d.) (68)10 66.) Convert (68)10 to binary. a.) 10000012

b.) 10001002 c.) 01010102 d.) 11101002 67.) Convert (632)8 to decimal. a.) (410)10 b.) (415)10 c.) (416)10 d.) (425)10 68.) Convert (177)10 to octal. a.) 1508 b.) 2618 c.) 3548 d.) 3568 69.) Convert (F4C)16 to decimal. a.) (316)10 b.) (317)10 c.) (318)10 d.) (319)10 70.) Convert (4768)10 to hex. a.) (12A0)16 b.) (A120)16 c.) (21A0)16 d.) (0A12)16 71.) Convert (11100111)2 to octal. a.) 3378 b.) 3478 c.) 3578 d.) 3678 72.) Convert (11100111)2 to hex. a.) AE16 b.) B416 c.) C616 d.) E716 73.) Convert (AE)16 to binary. a.)101011102 b.) 10111112 c.) 010111012 d.) 001101012 74.) Convert (156)8 to decimal. a.) 9010 b.) 10010 c.) 11010 d.) 12010 75.) Convert (15)16 to binary. a.)101000112 b.) 110111002 c.) 000101012 d.) 111010102 76.) Convert (4096)10 to hex. a.) 10016 b.) 25016 c.) 50016 d.) 100016 77.) Convert (01000101)2 to decimal. a.) 5910 b.) 6910

c.) 7910 d.) 8910 78.) Convert (23)8 to decimal. a.) 1410 b.) 1510 c.) 1910 d.) 2010 79.) Convert (000001)2 to decimal. a.) 110 b.) 1010 c.) 10010 d.) 100010 80.) Convert (1000)8 to decimal. a.) 50910 b.) 51010 c.) 51110 d.) 51210 17.) Convert (10)16 to binary. a.) 000100002 b.) 001000002 c.) 100100012 b.) 110101012 81.) Convert (0110101)2 to hex. a.) 5516 b.) 6516 c.) 7516 d.) 8516 82.) Convert (99)16 to decimal. a.) 15010 b.) 15110 c.) 15210 d.) 15310 83.) Convert (20)16 to binary. a.) 010000002 b.) 001000002 c.) 000100002 a.) 000010002 84.) Convert (25)16 to decimal. a.) 1710 b.) 2710 c.) 3710 d.) 4710 85.) Convert (01010000)2 to hex. a.) 4716 b.) 4816 c.) 4916 d.) 5016 86.) Convert (15)8 to decimal. a.) 1310 b.) 1410 c.) 2310 d.) 2410 87.) Convert (25)10 to binary. a.) 110012 b.) 100012 c.) 111002 d.) 101012

88.) Convert (90)10 to hex. a.) 4b16 b.) 5a16 c.) 6c16 d.) 7d16 89.) Convert (1500)10 to hex. a.) 5bc16 b.) 5dc16 c.) 5de16 d.) 5ea16 90.) Convert (A10)16 to decimal. a.) 254610 b.) 255610 c.) 256610 d.) 257610 91.) Convert (120)10 to hex. a.) 7716 b.) 7816 c.) 7916 d.) 8016 92.) Convert (10000)10 to hex. a.) 210716 b.) 217016 c.) 270116 d.) 271016 93.) Convert (56)16 to binary. a.) 000011002 b.) 010000112 c.) 010101102 d.) 01111102 94.) Convert (99)16 to binary. a.) 010000012 b.) 001001112 c.) 1001100102 d.) 110101012 95.) Convert (11001100)2 to decimal. a.) 20110 b.) 20210 c.) 20310 d.) 20410 96.) Convert (58)8 to decimal. a.) 110 b.) 210 c.) 410 d.) 510

97.) Convert (24)16 to binary. a.) 000101002 b.) 001001002 c.) 100101002 d.) 101101012 98.) Convert (48)10 to hex. a.) 3016 b.) 4016 c.) 5016 d.) 6016

99.) Convert (0011)2 to decimal. a.) 210 b.) 310 c.) 410 d.) 510 100.) Convert (10000000)2 to hex. a.) 6916 b.) 7016 c.) 7916 d.) 8016 101.) Convert (79)16 to decimal. a.) 11910 b.) 12010 c.) 12110 d.) 12210

102.) Convert (115)8 to decimal. a.) 7710 b.) 8710 c.) 9710 d.) 10710 103.) Convert (00010101)2 to hex. a.) 416 b.) 516 c.) 1416 d.) 1516 104.) Convert (67)16 to decimal. a.) 10110 b.) 10110 c.) 10310 d.) 10410 105.) Convert (12)16 to binary. a.) 000100102 b.) 010010102 c.) 110101012 d.) 101100102 106.) Convert (100,000)8 to decimal. a.) 2367810 b.) 3276810 c.) 3286710 d.) 3287610 107.) Convert (256)10 to octal. a.) 1008 b.) 2008 c.) 3008 d.) 4008 108.) Convert (43)8 to decimal. a.) 340 b.) 3510 c.) 3610 d.) 3710 109.) Convert (45)10 to binary. a.) 1001002 b.) 1011012 c.) 1101002 d.) 1110002

110.) Convert (0.75)10 to binary. a.) 0.12 b.) 0.112 c.) 0.1112 d.) 0.11112 111.) Convert (45.75)10 to binary. a.) 100100.112 b.) 110100.112 c.) 101101.112 d.) 111000.112 112.) Convert (0.6)8 to decimal. a.) 0.6510 b.) 0.7010 c.) 0.7510 d.) 0.8010

113.) The output of an AND gate with three inputs A,B, and C, is high when a. b. c. d. ) A = 1, B = 1, C = 0 ) A = 0, B = 0, C = 0 ) A = 1, B = 1, C = 1 ) A = 1, B = 0, C = 1

114.) If a 3-input NOR gate has eight input possibilities, how many of those possibilities will result in a HIGH output? a.) 1 b.) 3 c.) 6 d.) 9

115.) Which of the following logical operations is represented by the + sign in Boolean algebra? a.) AND b.) OR c.) inversion d.) complementation 116.) If a 3-input AND gate has eight input possibilities, how many of those possibilities will result in a HIGH output? a.) 1 b.) 3 c.) 5 d.) 7 117.) What does the small bubble on the output of the NAND gate logic symbol mean? a.) open collector output b.) tristate c.) the output is inverted d.) none if the above 118.) How many inputs of a four-input AND gate must be HIGH in order for the output of the logic gate to go HIGH? a.) any one of the inputs b.) any two of the inputs c.) any three of the inputs d.) all four inputs 119.) Which of the following gates has the exact inverse output of the OR gate for all possible input combinations? a.) AND b.) NAND c.) NOT d.) NOR 120.) The output of an exclusive-OR gate is HIGH if ________. a.) All inputs are HIGH b.) All inputs are LOW c.) the inputs are unequal

## d.) none of the above

121.) The NOR logic gate is the same as the operation of the ________ gate with an inverter connected to the output. a.) OR b.) AND c.) NAND d.) none of the above

122.) The basic logic gate whose output is the complement of the input is the: a.) OR gate b.) AND gate c.) inverter d.) comparator

123.) When reading a Boolean expression, what does the word "NOT" indicate? a.) the same as b.) inversion c.) high d.) low

124.) The logic gate that will have HIGH or "1" at its output when any one (or more) of its inputs is HIGH is a(n): a.) OR gate b.) AND gate d.) NOR gate d.) none of the above 125.) Which of the following is not a basic Boolean operation? a.) OR b.) NOR c.) AND d.) FOR 126.) The logic gate that will have a LOW output when any one of its inputs is HIGH is the: a.) NAND gate b.) AND gate c.) NOR gate d.) OR gate 127.) How many entries would a truth table for a four-input NAND gate has? a.) 2 b.) 8 c.) 16 d.) 32verter 128.) The term "hex inverter" refers to: a.) an inverter that has six inputs b.) six inverters in a single package c.) a six-input symbolic logic device d.) an inverter that has a history of failure

## 129 What is the base of Hexadecimal ) Number System? A. B. 16 2

C. 8
D.5 E. 10

130. What is the base of Binary ) Number System A . B . C . D . E . 131 In decimal number system, what is the next ) digit after 9: A . B . C . D . E . 132 In hexadecimal number system, what is the next ) digit after 9: A . B . C . D . E . 133 In hexadecimal number system, what is the next ) digit after F: A . B .

A .

B .

C .

D .

E .

A .

B .

C .

D .

E .

## 136. Convert (12)10 to ( )8 ) octal.

A . B . C . D . E . 137. Convert (11011)2 to ( )10 ) decimal. A . B . C . D . E . 137. Convert (10101)2 to ) ( )10. A . B . C . D . E . 138. Convert (73)8 to ) ( )10. A . B . C . D . E . 139. Convert (46)8 to ) ( )2. 1 0 0 1 0 1 1 0 0 1 1

A .

B .

C .

D .

E .

0 1 1 0 1 0 0 1 0 0 0 1 0 1 0 0 1 1 1

140. Convert ) (1256)8 to ( )2. B . C . D . E . 00101 01101 10 00101 01011 10 00101 01010 11 00101 00111 10

## 142. Convert (A9)16 to ) ( )2. A . 10 10 10 00 10 01 10 10 10 10 10 10 10 10

B .

C . D .

10 11

A . C . D . E.

D D 4 6 D C C E 6

C D 6

A .

B .

C .

D .

E .

6 1 0 2 5 3 6 1

A .

B .

C .

D .

E .

## 147. Represent (25)10 in 1's ) complement form. A . 1 1

B .

C .

D .

E .

0 0 1 0 0 1 1 1 0 0 1 1 0 0 0 1 0 0 0 1 0 0 1

A .

B .

C .

D .

E .

## 149. Add (1101)2 with ) (0111)2. 1 1 0 1 1 1 0 1 0 1 1 0

A .

B . C .

D .

E .

1 1 0 1 0 1 0 0 1 1 0 0 1

B .

C .

D .

E .

B .

C .

D .

E .

## . B . C . D . E . 153. Convert (24)10 to ) BCD. A . 00 10 10 01 00 10 11 01 00 10 10 00 00 10 01 00 00 10 01 10

B .

C .

D .

E .

154. Perform BCD addition of ) (45)10 with (93)10. A . B . C . D . E . 00010 01111 00 00010 01110 00 00010 01110 01 00110 00110 00 00010 01111 10

## 155. Convert (25)10 to XS-3 ) code. A . 01 01 10 01 01 01 11 00 10 10 10 00 01

B .

C . D

E .

01 11 01 01 01 10 00

B .

C .

D .

E .

B .

C .

D .

E .

## 158. Find gray code of ) (12)10. A . 1 0 0 0 1 0 0 1 1

B . C

D .

E .

0 1 0 1 0 1 1 1 1 0 0

## 159. Convert the gray code ) (1001011)2 to binary. 1 1 1 0 1 1 0 1 1 1 0 0 1 1 1 1 0 0 1 1 0 1 1 1 0 0 1 0 1 1 1 0 1 0 1

A .

B .

C .

D .

E .

160. What does X-OR ) gate do? A . B . C. D . E . Give a high output when one or more of its inputs are high Give a high output when only one of its inputs are high Give a low output when one or more of its inputs are high Give a low output when only one of its inputs are high None of the above 161.) What type of logic gate does this symbol represent?

A .

B .

C .

D .

E .

AN D Ga te O R G a t e NA ND Gat e N OR Ga te XOR Ga te

162.) The following truth table represents the behavior of which logic gate?

A .

B .

C .

D .

E .

## NA ND Gat e N OR Ga te XOR Ga te XNOR Gat e AN D Ga te

163 What happens if we connect together the inputs of NAND ) and NOR gates? A . B . C Help produce multiinput gates Produce and X-NOR gate Produce a

. D . E .

NOT gate Shor t circu it Damage the gate What type of logic gate's behaviour does this truth table represent?

164. )

A .

B . C . D . E .

## 2 inp ut OR 3 inp ut OR 3 input X-OR 3 input XNOR 4 input X-OR

165.) What type of logic gate does this logic circuit configuration produce?

A .

B .

NA ND Gat e N OR Ga te

C .

D .

E .

## AN D Ga te XNOR Gat e XOR Ga te

166.) Which of the following gates generates the truth table shown?

A .

B .

C .

D .

E .

AN D Ga te O R G a t e NA ND Gat e N OR Ga te XOR Ga te 167.) The following circuit is equal to which logic gate?

A .

B .

AN D Ga te O R G a t e N

D .

E .

A .

B .

C .

D .

E .

## 169.) The following circuit is equal to which logic gate?

A . B .

AN D Ga te O R G a t

C .

D .

E .

## e N OT Ga te XOR Ga te XNOR Gat e

170. Which logic gate gives the ) complement of input? A . AN D Ga te O R G a t e N OT Ga te NA ND Gat e N OR Ga te What is the missing output in the given truth table for X-NOR gate?

B .

C .

D .

E .

171. )

## A . B . 172.) What type of logic gate does this symbol represent?

A .

AN D Ga te

C .

D .

E .

R G a t e NA ND Gat e N OR Ga te XOR Ga te

173. OR gate is equivalent to which ) operation? A . B . C . D . E . Logical Additio n Logical Multiplicatio n Logical Compleme nt Logical Divisio n Logical Subtractio n

174. AND gate is equivalent to which ) operation? A . B . C . D . E . Logical Additio n Logical Multiplicatio n Logical Compleme nt Logical Divisio n Logical Subtractio n

A .

B .

C .

D .

E .

## 176.) This The following circuit is equivalent to which logic gate?

A .

B .

C .

AN D Ga te O R G a t e N OT Ga te

D .

E .

## 178.) Which statement below best describes a Karnaugh map?

A. It is simply a rearranged truth table B. The Karnaugh map eliminates the need for using NAND and NOR gates C. Variable complements can be eliminated by using Karnaugh maps. D. A Karnaugh map can be used to replace Boolean rules.

. 179.) Which of the examples below expresses the commutative law of multiplication? A. A + B = B + A B. A B = B + A C. A (B C) = (A B) C D. A B = B A

180.) The observation that a bubbled input OR gate is interchangeable with a bubbled output AND gate is referred to as: A. a Karnaugh map B. DeMorgan's second theorem C. the commutative law of addition D. the associative law of multiplication .

181.) The systematic reduction of logic circuits is accomplished by: A. symbolic reduction B. TTL logic C. using Boolean algebra D. using a truth table

182.) Logically, the output of a NOR gate would have the same Boolean expression as a(n): A. NAND gate immediately followed by an INVERTER

B. OR gate immediately followed by an INVERTER C. AND gate immediately followed by an INVERTER D. NOR gate immediately followed by an INVERTER

183.) The commutative law of addition and multiplication indicates that: A. the way we OR or AND two variables is unimportant because the result is the same

## B. we can group variables in an AND or in an OR any way we want

C. an expression can be expanded by multiplying term by term just the same as in ordinary algebra D. the factoring of Boolean expressions requires the multiplication of product terms that contain like variables

Midterm

## 1. a) b) c) MUX DeMUX Encoder Decoder

A combinational circuit which gates one input of data line to one of 2^n output lines is defined as

d)
2. a) b) c)

A combinational circuit which translates n input lines into an m-bit code word, where n <= 2^m is defined as a MUX DeMUX Encoder Decoder A ________ has 2^n data inputs, n control inputs and 1 output. MUX DeMUX Encoder Decoder In Multiplexer, The value of the ______ _____ determines the data input that is selected. Control output Control Input Data input Data output A ______ has n inputs and 2^n outputs. MUX DeMUX Encoder Decoder

d)
3. a) b) c) d) 4. a) b) c) d) 5. a) b) c) d)

## 6. a) b) c) d) 7. a) b) c) d) 8. a) b) c) d) 9. a) b) c) d) 10. a) b) c) d) 11. a) b) c) d) 12. a) b) c) d) 13. a) b) c) d) 14. a) b) c) d) 15. a)

It selects one of 2^n outputs by decoding the binary value on the n inputs. MUX DeMUX Encoder Decoder Exactly ____ output will be active for each combination of the inputs in multiplexer circuit. one two three four An ________ has 2^n inputs and n outputs. MUX DeMUX Encoder Decoder Encoder performs the inverse operation of a _________. MUX DeMUX Encoder Decoder In Priority Encoders, The higher value is encoded on the ______. input output data control In Priority Encoders, Output is invalid when ____ inputs are active. one two three none In Priority Encoders, Output is valid when at least ______ input is active. one two three none Use a ___ input multiplexer to realize a logic circuit for a function with ___ minterms. 2^n 2^1 2^2 2^0 In using a 2^n Multiplexer, n is what? No. No. No. No. of of of of data inputs control inputs data outputs control outputs

Each minterm of the function can be mapped to a _____ input of the multiplexer. input

b) c) d) 16.

output data control For each row in the truth table, for the function, where the value of output is 1, sets the corresponding data input of the multiplexer to what value? 1 2 3 0

a) b) c) d)

17. a) b) c) d) 18.

A _______ is a combinational circuit that converts coded inputs to another coded outputs. MUX DeMUX Encoder Decoder The commercially available decoders are normally built using _____ gates instead of using AND gates because they are easy and less expensive to build. OR NAND NOR XOR Another common type of _________ is the seven-segment________. MUX DeMUX Encoder Decoder Example of the commercial 7-segment decoder is the ______ chip. 7447 7400 7402 7408 How many inputs are required for a 1-of-10 BCD decoder? 4 10 8 1

## a) b) c) d) 19. a) b) c) d) 20. a) b) c) d) 21. a) b) c) d)

22. a) b) c) d) 23. a) b) c) d)

Most demultiplexers facilitate which of the following? Decimal to hexa Single input, multiple output Ac to dc Odd parity to even parity One application of a digital multiplexer is to facilitate: Code conversion Parity checking Parallel to serial data conversion Data generation

a)

2 bit

## a) b) c) d) 38. a) b) c) d) 39. a) b) c) d) 40.

a) b) c) d) 41. a) b) c) d) 42.

a) b)

c) d) 43. a) b) c) d) 44.

Multiplexer Half-Adder ________ is a combinational circuit that adds three bits and generates a sum and carry. Encoder Full-Adder Multiplexer Half-Adder The ___________ of two binary numbers can be done by taking the 2s complement of the subtrahend and adding it to the minuend. Addition Decoding Encoding Subtraction The ___ complement can be obtained by taking the 1s complement and adding 1 to the LSB. 1s 2s 3s 4s It is a type of digital logic which is implemented by boolean circuits, where the output is a pure function of the present input only.

a) b) c) d) 45. a) b) c) d) 46.

## a) b) c) d) 47. a) b) c) d) 48. a) b) c) d) 49. a) b) c) d) 50. a) b) c) d) 51. a) b) c) d)

Combination Logic Sequential Logic Both a and b None The output depends not only on the present input but also on the history of the input. Combination Logic Sequential Logic Both a and b None The ____________ is a combinational circuit which is used to perform subtraction of two bits. Full-adder Half-adder Full-subtractor Half-subtractor It has two inputs, X (minuend) and Y (subtrahend) and two outputs D (difference) and B (borrow). Full-adder Half-adder Full-subtractor Half-subtractor The____________ is a combinational circuit which is used to perform subtraction of three bits. Full-adder Half-adder Full-subtractor Half-subtractor It has three inputs, X (minuend) and Y (subtrahend) and Z (subtrahend) and two outputs D (difference) and B (borrow). Full-adder Half-adder Full-subtractor Half-subtractor

52. A.4 B.16 C.8 D.10 53. A.true B.False 54. A. B. C. D. 55.

## How many outputs are on a BCD decoder?

In a Gray code, each number is 3 greater than the binary representation of that number.

Use the weighting factors to convert the following BCD numbers to binary. 01010011 11010100 110101 101011 001001101000 100001100000 100001100 001100001

From the following list of input conditions, determine the state of the five output leads on a 74148 octal-to-binary encoder. H represents for High, L for Low I0 = 1 I1 = 1 I2 = 1 I3 = 1 I4 = 0 I5 = 1 I6 = 1 I7 = 1 EI = 0

## A. B. C. D. 56. A. B. C. D. 57. A. B. C. D. 58. A. B. C. D. 59. A. B. C. D. 60. A. B. C. D.

GS = L, A0 = L, A1 = L, A2 = H, EO = H GS = L, A0 = H, A1 = L, A2 = L, EO = H GS = L, A0 = L, A1 = H, A2 = L, EO = H GS = L, A0 = H, A1 = H, A2 = L, EO = H What is the function of an enable input on a multiplexer chip? apply Vcc connect ground activate the entire chip active one half of the chip

to to to to

What do the mathematical symbols A < b and A > B mean A < B means A is greater than B. A > B means A is less than B. A > B means A is less than B. A < B means A is greater than B. A < B means A is less than B. A > B means A is greater than B. None of the above. A basic multiplexer principle can be demonstrated through the use of a: DPDT switch rotary switch linear stepper None of the above. How many inputs will a decimal-to-BCD encoder have? 4 .8 10 16 A principle regarding most IC decoders is that when the correct input is present, the related output will switch: active-HIGH a high impedance an open active-LOWs

to to to to

61. What control signals may be necessary to operate a 1-line-to-16 line decoder? A. flasher circuit control signal B. a LOW on all gate enable inputs C. input from a hexadecimal counter

D. 62. A. B. C. D. 63. A. B. C. D. 64. A. B. C. D. 65. A. B. C. D. 66. A. B. C. D. 67. A. B. C. D. 68. A. B. C. D. 69. A. B. C. D. 70. A. B. C. D. 71. A. B. C. D.

a HIGH on all gate enable circuits One multiplexer can take the place of: several SSI logic gates combinational logic circuits several Ex-NOR gates several SSI logic gates or combinational logic circuits How many exclusive-NOR gates would be required for an 8-bit comparator circuit? 4 6 8 10 How many inputs are required for a 1-of-10 BCD decoder? 4 8 10 5 A 4-input BCD decoder will have how many rows in its truth table? 10 9 8 3 A 6-bit binary input would have how many possible inputs? 16 32 64 128 Most demultiplexers facilitate which type of conversion? decimal-to-hexadecimal single input, multiple outputs ac to dc odd parity to even parity One application of a digital multiplexer is to facilitate data generation serial-to-parallel conversion parity checking data selector The primary use for Gray code is: coded representation of a shaft's mechanical position turning on/off software switches to represent the correct ASCII code to indicate the angular position of a shaft on rotating machinery to convert the angular position of a shaft on rotating machinery into hexadecimal code Why is a demultiplexer called a data distributor? The input will be distributed to one of the outputs One of the inputs will be selected for the output. The output will be distributed to one of the inputs None of the above. What is the status of the inputs S0, S1, and S2 of the 74151 eight-line multiplexer in order for the output Y to display output I5? S0 = 0, S1 = 1, S2 = 0 S0 = 0, S1 = 0, S2 = 1 S0 = 1, S1 = 1, S2 = 0 S0 = 1, S1 = 0, S2 = 1

72. One way to convert BCD to binary using the hardware approach 73. is: A. with MSI IC circuits B. with a keyboard encoder C. with an ALU

D. 74.

UART A microcontroller differs from a microprocessor in that it has several ________ ports and ________ built into its architecture, making it better suited for ________ applications. communication, PROMs, control parallel, logic gates, processing input/output, memory, control data, memory, decoding How is an encoder different from a decoder? The output of an encoder is a binary code for 1-of-N input. The output of a decoder is a binary code for 1-of-N input. Both a & b None of the above. Why is the Gray code more practical to use when coding the position of a rotating shaft? All digits change between counts. Two digits change between counts. Only one digit changes between counts A binary code that progresses such that only one bit changes between two successive codes is: nine's-complement code 8421 code excess-3 code Gray code Which of the following is not a common numbering system? Hexadecimal binary-coded decimal binary octal

## 79. A. B. C. D. 80. A. B. C. D. 81. A. B. C. D. 82. A. B. C. D. 83. A. B. C. D.

How many inputs are required for a 1-of-16 decoder? 2 4 8 16 A truth table with output columns numbered 015 may be for which type of decoder IC? hexadecimal 1-of-16 dual octal outputs binary-to-hexadecimal hexadecimal-to-binary In a BCD-to-seven-segment converter, why must a code converter be utilized? to convert the 4-bit BCD into 7-bit code to convert the 4-bit BCD into 10-bit code to convert the 4-bit BCD into Gray code No conversion is necessary. How can the active condition (HIGH or LOW) or the decoder output be determined from the logic symbol? indicates active-HIGH. indicates active-LOW. indicates active-HIGH. indicates active-LOW.

A A A A

## bubble bubble square square

If two inputs are active on a priority encoder, which will be coded on the output? the higher value the lower value neither of the inputs both of the inputs

## 84. A. B. C. D. 85. A. B. C. D. 86. A. B. C. D. 87. A. B. C. D. 88. A. B. C. D. 89. A. B. C. D. 90. A. B. C. D.

How many 74184 BCD-to-binary converters would be required to convert two complete BCD digits to a binary number? 8 4 2 1 How many select lines would be required for an 8-line-to-1-line multiplexer? 2 4 3 8 Which of the following statements accurately represents the two BEST methods of logic circuit simplification? Boolean algebra and Karnaugh mapping Karnaugh mapping and circuit waveform analysis Actual circuit trial and error evaluation and waveform analysis Boolean algebra and actual circuit trial and error evaluation How many 3-line-to-8-line decoders are required for a 1-of-32 decoder? 1 2 4 8 A circuit that consists of input variables, logic gates, and output variables. Encoder Decoder Combinational Circuits Circuits What is the indication of a short on the input of a load gate? Only the output of the defective gate is affected. There is a signal loss to all gates on the node. The affected node will be stuck in the LOW state. There is a signal loss to all gates on the node, and the affected node will be stuck in the LOW state. In HDL, LITERALS is/are: digital systems. scalars. binary coded decimals. numbering system.

91. A. B. C. D.

Which of the following expressions is in the sum-of-products form? (A + B)(C + D) (AB)(CD) AB(CD) AB + CD

## 92. The carry propagation can be expressed as ________. A. Cp = AB B. Cp = A + B

C.

D. 93. How many 4-bit parallel adders would be required to add two binary numbers

94.

## A. B. C. D. 95. A. B. C. D. 96. A. B. C. D. 97. A. B. C. D. 98. A. B. C. D.

1 3 2 4 How many 3-line-to-8-line decoders are required for a 1-of-32 decoder? 1 2 4 8 Is a combinational circuit that selects binary information from one of many input lines and directs it to a single output line? Multiplexer Decoder binary adder Full adder How many outputs would two 8-line-to-3-line encoders, expanded to a 16-line-to-4-line encoder, have? 3 5 6 4 Which of the following combinations of logic gates can decode binary 1101? 4-input AND gate 4-input AND gate, one OR gate 4-input NAND gate, one inverter 4-input AND gate, one inverter When adding an even parity bit to the code 110010, the result is ________. 1110010 1111001 110010 001101

100.

## The device shown here is most likely a ________.

A. B. C. D. 101.

Comparator Multiplexer Demultiplexer parity generator What type of logic circuit is represented by the figure shown below?

A. B. C. D.

XOR XNOR XAND XNAND 102. A full-adder has a Cin = 0. What are the sum ( ) and the carry (Cout) when A = 1 and B = 1?

A. B. C. D.

## 103.Solve the network in the figure given below for X.

A. B. C. D. 104.

A + BC + D ((A + B)C) + D D(A + B + C) (AC + BC)D A certain BCD-to-decimal decoder has active-HIGH inputs and active-LOW outputs. Which output goes LOW when the inputs are 1001? 0 3 9 None. All outputs are HIGH.

A. B. C. D.

105.

For the device shown here, let all D inputs be LOW, both S inputs be HIGH, and the the Y output?

A. B. C. D.

106.

## Convert BCD 0001 0010 0110 to binary

A 1111110 . C 1111000 .

B 1111101 . D 1111111 .

107.

A 74HC147 priority encoder has ten active-LOW inputs and four active-LOW outputs. What would be the state of the four outputs if inputs 4 and 5 are LOW and all other inputs are HIGH?

A. B. C. D. 108. A. B. C. D. 10101 10010 11000 10001 How many data select lines are required for selecting eight inputs? Convert BCD 0001 0111 to binary.

## 109. A. 1 B. 2 C. 3 D. 4 110. A. B. C. D. 111. A. 5 B. 7 C. 6 D. 8 112.

The simplest equation which implements the K-map shown below is:

How many 1-of-16 decoders are required for decoding a 7-bit binary number?

Which of the following logic expressions represents the logic diagram shown?

A. B. C.

D. 113. The implementation of simplified sum-of-products expressions may be easily implemented into actual logic circuits using all universal ________ gates with little or no increase in circuit complexity. (Select the response for the blank space that will BEST make the statement true.) AND/OR NAND

A. B.

C. D.

NOR OR/AND

114. Which of the following statements accurately represents the two BEST methods of logic circuit simplification? A. Boolean algebra and Karnaugh mapping B. Karnaugh mapping and circuit waveform analysis C. Actual circuit trial and error evaluation and waveform analysis D. Boolean algebra and actual circuit trial and error evaluation

115.

For the device shown here, assume the D input is LOW, both S inputs are HIGH, and the status of the outputs?

## input is HIGH. What is the

A. B. C. D.

All are HIGH. All are LOW. All but All but are LOW. are HIGH.

116. Which of the following combinations cannot be combined into K-map groups? A. Corners in the same row B. Corners in the same column C. Diagonal corners D. Overlapping combinations 117. Which gate is best used as a basic comparator? A. NOR B. OR C. Exclusive-OR D. AND 118. The device shown here is most likely a ________.

A. B. C. D.

## comparator multiplexer demultiplexer parity generator

119. Which of the following expressions is in the product-of-sums form? A. (A + B)(C + D)] B. (AB)(CD) C. AB(CD) D. AB + CD

120. Which of the following is an important feature of the sum-of-products form of expressions? A. All logic circuits are reduced to nothing more than simple AND and OR operations. B. The delay times are greatly reduced over other forms. C. No signal must pass through more than two gates, not including inverters. D. The maximum number of gates that any signal must pass through is reduced by a factor of two

121. of the

For the device shown here, assume the D input is LOW, both S inputs are LOW, and the outputs?

## input is LOW. What is the status

A. B. C.

All are HIGH. All are LOW. All but are LOW. are HIGH.\ The binary numbers A = 1100 and B = 1001 are applied to the inputs of a comparator. What are the output levels? 1, 0, 1, 0, A A A A < < < < B B B B = = = = 0, 1, 0, 1, A A A A < = = = B B B B = = = = 1 0 0 1

## D. All but 122. A. B. C. D. 123. A. B. C. D. A A A A > > > > B B B B = = = =

A logic probe is placed on the output of a gate and the display indicator is dim. A pulser is used on each of the input terminals, but the output indication does not change. What is wrong? The output of the gate appears to be open. The dim indication on the logic probe indicates that the supply voltage is probably low The dim indication is a result of a bad ground connection on the logic probe. The gate may be a tristate device. Each "1" entry in a K-map square represents: HIGH for each input truth table condition that produces a HIGH output. HIGH output on the truth table for all LOW input combinations LOW output for all possible HIGH input conditions DON'T CARE condition for all possible input truth table combinations. The binary numbers A = 1100 and B = 1001 are applied to the inputs of a comparator. What are the output levels? 1, A < B = 0, A < B = 1 0, A < B = 1, A = B = 0 1, A < B = 0, A = B = 0 0, A < B = 1, A = B = 1

124. A. a B. a C. a D. a 125. A. A B. A C. A D. A

## > > > >

B B B B

= = = =

126. Looping on a K-map always results in the elimination of: A. variables within the loop that appear only in their complemented form. B. variables that remain unchanged within the loop. C. variables within the loop that appear in both complemented and uncomplemented form D. variables within the loop that appear only in their uncomplemented form 127. What is the indication of a short on the input of a load gate? A. Only the output of the defective gate is affected. B. There is a signal loss to all gates on the node. C. The affected node will be stuck in the LOW state. D. There is a signal loss to all gates on the node, and the affected node will be stuck in the LOW state. 128. In HDL, LITERALS is/are: A. digital systems.

B. C. D.

## scalars. binary coded decimals. a numbering system.

129. Which of the following expressions is in the sum-of-products form? A. (A + B)(C + D) B. (AB)(CD) C. AB(CD) D. AB + CD

130. The carry propagation can be expressed as ________. A. Cp = AB B. Cp = A + B C. D. 131. Which statement below best describes a Karnaugh map? A. A Karnaugh map can be used to replace Boolean rules B. The Karnaugh map eliminates the need for using NAND and NOR gates. C. Variable complements can be eliminated by using Karnaugh maps. D. Karnaugh maps provide a visual approach to simplifying Boolean expressions 132. Which of the K-maps given below represents the expression X = AC + BC + B?

A. B. C. D. 133.

a b c d A decoder can be used as a demultiplexer by ________. A. tying all enable pins LOW B. tying all data-select lines LOW C. tying all data-select lines HIGH D. using the input lines for data selection and an enable line for data input

134.

What is the indication of a short to ground in the output of a driving gate? A. Only the output of the defective gate is affected. B. There is a signal loss to all load gates. C. The node may be stuck in either the HIGH or the LOW state. D. The affected node will be stuck in the HIGH state.

135. A True .

An encoder in which the highest and lowest value input digits are encoded simultaneously is known as a priority encoder. B False .

136.

## The device shown here is most likely a ________.

A. comparator B. multiplexer C. demultiplexer D. parity generator 137.Which of the following combinations cannot be combined into K-map groups? A. Corners in the same row B. Corners in the same column C. Diagonal corners D. Overlapping combinations

138.

For the device shown here, let all D inputs be LOW, both S inputs be HIGH, and the the Y output?

139.

## How many 3-line-to-8-line decoders are required for a 1-of-32 decoder? A. 1 C. 4 B. 2 D. 8

140.

Consists of input variables, logic gates, and output variables.48. A. encoder C. Combinational Circuits B. decoder D. circuits

139. A combinational circuit that performs the addition of two bits is called A B half adder adder . . C D Combinational Circuits Full adder . .

140. One that performs the addition of three bits (two significant bits and a previous carry) is called A.Full adder C.Combinational Circuits B.adder D Half adder .

141. is a combinational circuit that performs the arithmetic operations of addition and subtraction with binary numbers. A B binary adder-subtractor Full adder . . C D Combinational Circuits Half adder . . 142. is a digital circuit that produces the arithmetic sum of two binary numbers A B encoder decoder . . C D binary adder Full adder . . 143. is a combinational circuit that converts binary information from n input lines to a maximum of 2^n unique output lines. A B encoder decoder . . C D binary adder Full adder . . 144. An encoder is a digital circuit that performs the inverse operation of a decoder. A B encoder decoder . . C D binary adder Full adder . .

145. In VHDL, macrofunctions is/are: A. digital circuits. B. analog circuits. C. a set of bit vectors. D. preprogrammed TTL devices.

## results from this Karnaugh map.

A True .

B False .

147. The input at the 1, 2, 4, 8 inputs to a 4-line to 16-line decoder with active-low outputs is 1110. As a result, output line 7 is driven LOW. A True . B False .

148. To implement the full-adder sum functions, two exclusive-OR gates can be used. A B True False . . 149. Single looping in groups of three is a common K-map simplification technique. A B True False . . 150. In true sum-of-products expressions, the inversion signs cannot cover more than single variables in a term. A B True False . .

## A True . 152. A data selector is also called a demultiplexer. A True .

B False . B False .

153. An exclusive-OR gate will invert a signal on one input if the other is always HIGH. A B True False . .

A True .

B False .

## 155. The simplified form of A True .

. B False .

156. The K-map in the figure below shows the correct implementation of the expression X = ACD + AB(CD + BC).

A True .

B False .

## 159. The simplified form of A True .

. B False .

160. The carry output of each adder in a ripple adder provides an additional sum output bit. A True . B False .

Midterm

## 141. e) f) g) MUX DeMUX Encoder Decoder

A combinational circuit which gates one input of data line to one of 2^n output lines is defined as

h)

142. A combinational circuit which translates n input lines into an m-bit code word, where n <= 2^m is defined as a e) MUX f) DeMUX g) Encoder

h)
143. e) f) g) h) 144. e) f) g) h) 145. e)

Decoder A ________ has 2^n data inputs, n control inputs and 1 output. MUX DeMUX Encoder Decoder In Multiplexer, The value of the ______ _____ determines the data input that is selected. Control output Control Input Data input Data output A ______ has n inputs and 2^n outputs. MUX

## f) g) h) 146. e) f) g) h) 147. e) f) g) h) 148. e) f) g) h) 149. e) f) g) h) 150. e) f) g) h) 151. e) f) g) h) 152. e) f) g) h) 153. e) f) g) h) 154. e) f) g) h)

DeMUX Encoder Decoder It selects one of 2^n outputs by decoding the binary value on the n inputs. MUX DeMUX Encoder Decoder Exactly ____ output will be active for each combination of the inputs in multiplexer circuit. one two three four An ________ has 2^n inputs and n outputs. MUX DeMUX Encoder Decoder Encoder performs the inverse operation of a _________. MUX DeMUX Encoder Decoder In Priority Encoders, The higher value is encoded on the ______. input output data control In Priority Encoders, Output is invalid when ____ inputs are active. one two three none In Priority Encoders, Output is valid when at least ______ input is active. one two three none Use a ___ input multiplexer to realize a logic circuit for a function with ___ minterms. 2^n 2^1 2^2 2^0 In using a 2^n Multiplexer, n is what? No. No. No. No. of of of of data inputs control inputs data outputs control outputs

155. e) f) g) h) 156.

Each minterm of the function can be mapped to a _____ input of the multiplexer. input output data control For each row in the truth table, for the function, where the value of output is 1, sets the corresponding data input of the multiplexer to what value? 1 2 3 0

e) f) g) h)

157. e) f) g) h) 158.

A _______ is a combinational circuit that converts coded inputs to another coded outputs. MUX DeMUX Encoder Decoder The commercially available decoders are normally built using _____ gates instead of using AND gates because they are easy and less expensive to build. OR NAND NOR XOR Another common type of _________ is the seven-segment________. MUX DeMUX Encoder Decoder Example of the commercial 7-segment decoder is the ______ chip. 7447 7400 7402 7408 How many inputs are required for a 1-of-10 BCD decoder? 4 10 8 1

## e) f) g) h) 159. e) f) g) h) 160. e) f) g) h) 161. e) f) g) h)

162. a) b) c) d) 163. a) b)

Most demultiplexers facilitate which of the following? Decimal to hexa Single input, multiple output Ac to dc Odd parity to even parity One application of a digital multiplexer is to facilitate: Code conversion Parity checking

## 167. a) b) c) d) 168. a) b) c) d) 169. a) b) c) d) 170. a) b) c) d) 171. a) b) c) d) 172. a) b) c) d)

173. string. a) b) c) d) 174. a) b) c) d) 175. a) b) c) d) 176. a) b) c) d) 177. Carry Carry Carry Carry 2 3 1 n bit bit bit bit

When an _____ adder includes a carry-in (cin) and a carry-out (sn), they can be cascaded to generate an adder with n-bit

## a) b) c) d) 178. a) b) c) d) 179. a) b) c) d) 180.

a) b) c) d) 181. a) b) c) d)

182.

To add numbers with more than one bit, we must provide a way for carries between bit positions. This basic circuit for this operation is called a ___________ Encoder Full-Adder Multiplexer Half-Adder ________ is a combinational circuit that adds three bits and generates a sum and carry. Encoder Full-Adder Multiplexer Half-Adder The ___________ of two binary numbers can be done by taking the 2s complement of the subtrahend and adding it to the minuend. Addition Decoding Encoding Subtraction The ___ complement can be obtained by taking the 1s complement and adding 1 to the LSB. 1s 2s 3s 4s It is a type of digital logic which is implemented by boolean circuits, where the output is a pure function of the present input only.

a) b) c) d) 183. a) b) c) d) 184.

a) b) c) d) 185. a) b) c) d) 186.

## a) b) c) d) 187. a) b) c) d) 188. a) b) c) d) 189. a) b) c) d) 190. a) b) c) d) 191.

Combination Logic Sequential Logic Both a and b None The output depends not only on the present input but also on the history of the input. Combination Logic Sequential Logic Both a and b None The ____________ is a combinational circuit which is used to perform subtraction of two bits. Full-adder Half-adder Full-subtractor Half-subtractor It has two inputs, X (minuend) and Y (subtrahend) and two outputs D (difference) and B (borrow). Full-adder Half-adder Full-subtractor Half-subtractor The____________ is a combinational circuit which is used to perform subtraction of three bits. Full-adder Half-adder Full-subtractor Half-subtractor It has three inputs, X (minuend) and Y (subtrahend) and Z (subtrahend) and two outputs D (difference) and B (borrow).

I0 = 1 I1 = 1 I2 = 1 a) b) c) d) 192. A.4 B.16 C.8 D.10 193. A.true B.False 194. A. B. C. D. 195. Full-adder Half-adder Full-subtractor Half-subtractor

I3 = 1 I4 = 0 I5 = 1

I6 = 1 I7 = 1 EI = 0

## How many outputs are on a BCD decoder?

In a Gray code, each number is 3 greater than the binary representation of that number.

Use the weighting factors to convert the following BCD numbers to binary. 01010011 11010100 110101 101011 001001101000 100001100000 100001100 001100001

From the following list of input conditions, determine the state of the five output leads on a 74148 octal-to-binary encoder. H represents for High, L for Low

A. B. C. D.

GS = L, A0 = L, A1 = L, A2 = H, EO = H GS = L, A0 = H, A1 = L, A2 = L, EO = H GS = L, A0 = L, A1 = H, A2 = L, EO = H GS = L, A0 = H, A1 = H, A2 = L, EO = H What is the function of an enable input on a multiplexer chip? apply Vcc connect ground activate the entire chip active one half of the chip

196. A. to B. to C. to D. to

197. What do the mathematical symbols A < b and A > B mean A. A < B means A is greater than B. A > B means A is less than B. B. A > B means A is less than B. A < B means A is greater than B. C. A < B means A is less than B. A > B means A is greater than B. D. None of the above. 198. A basic multiplexer principle can be demonstrated through the use of a: A. DPDT switch B. rotary switch C. linear stepper D. None of the above. 199. A. 4 B. .8 C. 10 D. 16 200. A. to B. to C. to D. to How many inputs will a decimal-to-BCD encoder have?

A principle regarding most IC decoders is that when the correct input is present, the related output will switch: active-HIGH a high impedance an open active-LOWs

201. What control signals may be necessary to operate a 1-line-to-16 line decoder? A. flasher circuit control signal B. a LOW on all gate enable inputs C. input from a hexadecimal counter D. a HIGH on all gate enable circuits 202. One multiplexer can take the place of: A. several SSI logic gates B. combinational logic circuits C. several Ex-NOR gates D. several SSI logic gates or combinational logic circuits 203. A. 4 B. 6 C. 8 D. 10 204. A. 4 B. 8 C. 10 D. 5 205. A. 10 B. 9 C. 8 D. 3 206. A. 16 B. 32 C. 64 D. 128 How many exclusive-NOR gates would be required for an 8-bit comparator circuit?

## How many inputs are required for a 1-of-10 BCD decoder?

A 4-input BCD decoder will have how many rows in its truth table?

## A 6-bit binary input would have how many possible inputs?

207. Most demultiplexers facilitate which type of conversion? A. decimal-to-hexadecimal B. single input, multiple outputs C. ac to dc D. odd parity to even parity 208. One application of a digital multiplexer is to facilitate A. data generation B. serial-to-parallel conversion C. parity checking D. data selector 209. The primary use for Gray code is: A. coded representation of a shaft's mechanical position B. turning on/off software switches C. to represent the correct ASCII code to indicate the angular position of a shaft on rotating machinery D. to convert the angular position of a shaft on rotating machinery into hexadecimal code 210. Why is a demultiplexer called a data distributor? A. The input will be distributed to one of the outputs B. One of the inputs will be selected for the output. C. The output will be distributed to one of the inputs D. None of the above. 211. A. B. C. D. I5? S0 = S0 = S0 = S0 = 0, 0, 1, 1, What is the status of the inputs S0, S1, and S2 of the 74151 eight-line multiplexer in order for the output Y to display output S1 S1 S1 S1 = = = = 1, 0, 1, 0, S2 S2 S2 S2 = = = = 0 1 0 1

212. One way to convert BCD to binary using the hardware approach is: A. with MSI IC circuits B. with a keyboard encoder C. with an ALU D. UART 213. A microcontroller differs from a microprocessor in that it has several ________ ports and ________ built into its architecture, making it better suited for ________ applications. communication, PROMs, control parallel, logic gates, processing input/output, memory, control data, memory, decoding How is an encoder different from a decoder? The output of an encoder is a binary code for 1-of-N input. The output of a decoder is a binary code for 1-of-N input. Both a & b None of the above. Why is the Gray code more practical to use when coding the position of a rotating shaft? All digits change between counts. Two digits change between counts. Only one digit changes between counts

A. B. C. D. 214. A. B. C. D. 215. A. B. C.

216. A binary code that progresses such that only one bit changes between two successive codes is: A. nine's-complement code B. 8421 code C. excess-3 code D. Gray code 217. Which of the following is not a common numbering system? A. Hexadecimal B. binary-coded decimal C. binary D. octal 218. A. 2 B. 4 C. 8 D. 16 219. A. B. C. D. 220. A. B. C. D. How many inputs are required for a 1-of-16 decoder?

A truth table with output columns numbered 015 may be for which type of decoder IC? hexadecimal 1-of-16 dual octal outputs binary-to-hexadecimal hexadecimal-to-binary In a BCD-to-seven-segment converter, why must a code converter be utilized? to convert the 4-bit BCD into 7-bit code to convert the 4-bit BCD into 10-bit code to convert the 4-bit BCD into Gray code No conversion is necessary. How can the active condition (HIGH or LOW) or the decoder output be determined from the logic symbol? indicates active-HIGH. indicates active-LOW. indicates active-HIGH. indicates active-LOW.

221. A. A B. A C. A D. A

## bubble bubble square square

222. If two inputs are active on a priority encoder, which will be coded on the output? A. the higher value

B. C. D.

the lower value neither of the inputs both of the inputs How many 74184 BCD-to-binary converters would be required to convert two complete BCD digits to a binary number?

## How many select lines would be required for an 8-line-to-1-line multiplexer?

Which of the following statements accurately represents the two BEST methods of logic circuit simplification? Boolean algebra and Karnaugh mapping Karnaugh mapping and circuit waveform analysis Actual circuit trial and error evaluation and waveform analysis Boolean algebra and actual circuit trial and error evaluation How many 3-line-to-8-line decoders are required for a 1-of-32 decoder?

226. A. 1 B. 2 C. 4 D. 8

227. A circuit that consists of input variables, logic gates, and output variables. A. Encoder B. Decoder C. Combinational Circuits D. Circuits 228. What is the indication of a short on the input of a load gate? A. Only the output of the defective gate is affected. B. There is a signal loss to all gates on the node. C. The affected node will be stuck in the LOW state. D. There is a signal loss to all gates on the node, and the affected node will be stuck in the LOW state. 229. In HDL, LITERALS is/are: A. digital systems. B. scalars. C. binary coded decimals. D. numbering system.

230. Which of the following expressions is in the sum-of-products form? A. (A + B)(C + D) B. (AB)(CD) C. AB(CD) D. AB + CD

## 231. The carry propagation can be expressed as ________. A. Cp = AB B. Cp = A + B

C.

D. 232. How many 4-bit parallel adders would be required to add two binary numbers each representing decimal numbers up through 30010?

A. B. C. D. 233. A. B. C. D. 234.

1 3 2 4 How many 3-line-to-8-line decoders are required for a 1-of-32 decoder? 1 2 4 8 Is a combinational circuit that selects binary information from one of many input lines and directs it to a single output line?

A. Multiplexer B. Decoder C. binary adder D. Full adder 235. How many outputs would two 8-line-to-3-line encoders, expanded to a 16-line-to-4-line encoder, have? A. 3 B. 5 C. 6 D. 4 236. A. One B. One C. One D. One 237. 1110010 1111001 110010 001101 238. The device shown here is most likely a ________. Which of the following combinations of logic gates can decode binary 1101? 4-input AND gate 4-input AND gate, one OR gate 4-input NAND gate, one inverter 4-input AND gate, one inverter When adding an even parity bit to the code 110010, the result is ________.

A. B. C. D. 239.

Comparator Multiplexer Demultiplexer parity generator What type of logic circuit is represented by the figure shown below?

A. B. C. D.

XOR XNOR XAND XNAND 240. A full-adder has a Cin = 0. What are the sum ( ) and the carry (Cout) when A = 1 and B = 1?

A. B. C. D.

## 241.Solve the network in the figure given below for X.

A. B. C. D. 242.

A + BC + D ((A + B)C) + D D(A + B + C) (AC + BC)D A certain BCD-to-decimal decoder has active-HIGH inputs and active-LOW outputs. Which output goes LOW when the inputs are 1001? 0 3 9 None. All outputs are HIGH.

A. B. C. D.

243.

For the device shown here, let all D inputs be LOW, both S inputs be HIGH, and the the Y output?

A. B. C. D.

244.

## Convert BCD 0001 0010 0110 to binary

A 1111110 . C 1111000 .

B 1111101 . D 1111111 .

245.

A 74HC147 priority encoder has ten active-LOW inputs and four active-LOW outputs. What would be the state of the four outputs if inputs 4 and 5 are LOW and all other inputs are HIGH?

A. B. C. D. 246. A. B. C. D. 10101 10010 11000 10001 How many data select lines are required for selecting eight inputs? Convert BCD 0001 0111 to binary.

## 247. A. 1 B. 2 C. 3 D. 4 248. A. B. C. D. 249. A. 5 B. 7 C. 6 D. 8 250.

The simplest equation which implements the K-map shown below is:

How many 1-of-16 decoders are required for decoding a 7-bit binary number?

Which of the following logic expressions represents the logic diagram shown?

A. B. C. D.

251.

The implementation of simplified sum-of-products expressions may be easily implemented into actual logic circuits using all universal ________ gates with little or no increase in circuit complexity. (Select the response for the blank space that will BEST make the statement true.) AND/OR NAND NOR OR/AND

A. B. C. D.

252. Which of the following statements accurately represents the two BEST methods of logic circuit simplification? A. Boolean algebra and Karnaugh mapping B. Karnaugh mapping and circuit waveform analysis C. Actual circuit trial and error evaluation and waveform analysis D. Boolean algebra and actual circuit trial and error evaluation

253.

For the device shown here, assume the D input is LOW, both S inputs are HIGH, and the status of the outputs?

## input is HIGH. What is the

A. B. C. D.

All are HIGH. All are LOW. All but All but are LOW. are HIGH.

254. Which of the following combinations cannot be combined into K-map groups? A. Corners in the same row B. Corners in the same column C. Diagonal corners D. Overlapping combinations 255. Which gate is best used as a basic comparator? A. NOR B. OR C. Exclusive-OR D. AND 256. The device shown here is most likely a ________.

A. B. C. D.

## comparator multiplexer demultiplexer parity generator

257. Which of the following expressions is in the product-of-sums form? A. (A + B)(C + D)] B. (AB)(CD) C. AB(CD) D. AB + CD 258. Which of the following is an important feature of the sum-of-products form of expressions? A. All logic circuits are reduced to nothing more than simple AND and OR operations. B. The delay times are greatly reduced over other forms. C. No signal must pass through more than two gates, not including inverters. D. The maximum number of gates that any signal must pass through is reduced by a factor of two

259. of the

For the device shown here, assume the D input is LOW, both S inputs are LOW, and the outputs?

## input is LOW. What is the status

A. B. C.

All are HIGH. All are LOW. All but are LOW. are HIGH.\ The binary numbers A = 1100 and B = 1001 are applied to the inputs of a comparator. What are the output levels?

## D. All but 260.

A. B. C. D. 261. A. B. C. D.

A A A A

B B B B

= = = =

1, 0, 1, 0,

A A A A

## < < < <

B B B B

= = = =

0, 1, 0, 1,

A A A A

< = = =

B B B B

= = = =

1 0 0 1

A logic probe is placed on the output of a gate and the display indicator is dim. A pulser is used on each of the input terminals, but the output indication does not change. What is wrong? The output of the gate appears to be open. The dim indication on the logic probe indicates that the supply voltage is probably low The dim indication is a result of a bad ground connection on the logic probe. The gate may be a tristate device. Each "1" entry in a K-map square represents: HIGH for each input truth table condition that produces a HIGH output. HIGH output on the truth table for all LOW input combinations LOW output for all possible HIGH input conditions DON'T CARE condition for all possible input truth table combinations. The binary numbers A = 1100 and B = 1001 are applied to the inputs of a comparator. What are the output levels? 1, A < B = 0, A < B = 1 0, A < B = 1, A = B = 0 1, A < B = 0, A = B = 0 0, A < B = 1, A = B = 1

262. A. a B. a C. a D. a 263. A. A B. A C. A D. A

## > > > >

B B B B

= = = =

264. Looping on a K-map always results in the elimination of: A. variables within the loop that appear only in their complemented form. B. variables that remain unchanged within the loop. C. variables within the loop that appear in both complemented and uncomplemented form D. variables within the loop that appear only in their uncomplemented form 265. What is the indication of a short on the input of a load gate?

A. B. C. D.

Only the output of the defective gate is affected. There is a signal loss to all gates on the node. The affected node will be stuck in the LOW state. There is a signal loss to all gates on the node, and the affected node will be stuck in the LOW state.

266. In HDL, LITERALS is/are: A. digital systems. B. scalars. C. binary coded decimals. D. a numbering system. 267. Which of the following expressions is in the sum-of-products form? A. (A + B)(C + D) B. (AB)(CD) C. AB(CD) D. AB + CD 268. The carry propagation can be expressed as ________. A. Cp = AB B. Cp = A + B C. D. 269. Which statement below best describes a Karnaugh map? A. A Karnaugh map can be used to replace Boolean rules B. The Karnaugh map eliminates the need for using NAND and NOR gates. C. Variable complements can be eliminated by using Karnaugh maps. D. Karnaugh maps provide a visual approach to simplifying Boolean expressions 270. Which of the K-maps given below represents the expression X = AC + BC + B?

A. B. C. D. 271.

a b c d A decoder can be used as a demultiplexer by ________. A. tying all enable pins LOW B. tying all data-select lines LOW C. tying all data-select lines HIGH D. using the input lines for data selection and an enable line for data input

272.

What is the indication of a short to ground in the output of a driving gate? A. Only the output of the defective gate is affected. B. There is a signal loss to all load gates. C. The node may be stuck in either the HIGH or the LOW state. D. The affected node will be stuck in the HIGH state.

273.

An encoder in which the highest and lowest value input digits are encoded simultaneously is known as a priority encoder.

A True .

B False .

274.

## The device shown here is most likely a ________.

A. comparator B. multiplexer C. demultiplexer D. parity generator 275.Which of the following combinations cannot be combined into K-map groups? A. Corners in the same row B. Corners in the same column C. Diagonal corners D. Overlapping combinations

276.

For the device shown here, let all D inputs be LOW, both S inputs be HIGH, and the the Y output?

277.

A. C.

1 4

B. D.

2 8

278.

## A. encoder C. Combinational Circuits

B. decoder D. circuits

139. A combinational circuit that performs the addition of two bits is called A B half adder adder . . C D Combinational Circuits Full adder . . 140. One that performs the addition of three bits (two significant bits and a previous carry) is called A.Full adder C.Combinational Circuits B.adder D Half adder .

141. is a combinational circuit that performs the arithmetic operations of addition and subtraction with binary numbers. A B binary adder-subtractor Full adder . . C D Combinational Circuits Half adder . . 142. is a digital circuit that produces the arithmetic sum of two binary numbers A B encoder decoder . . C D binary adder Full adder . . 143. is a combinational circuit that converts binary information from n input lines to a maximum of 2^n unique output lines. A B encoder decoder . . C D binary adder Full adder . . 144. An encoder is a digital circuit that performs the inverse operation of a decoder. A B encoder decoder . . C D binary adder Full adder . .

145. In VHDL, macrofunctions is/are: A. digital circuits. B. analog circuits. C. a set of bit vectors. D. preprogrammed TTL devices.

## results from this Karnaugh map.

A True .

B False .

147. The input at the 1, 2, 4, 8 inputs to a 4-line to 16-line decoder with active-low outputs is 1110. As a result, output line 7 is driven LOW. A True . B False .

148. To implement the full-adder sum functions, two exclusive-OR gates can be used. A B True False . . 149. Single looping in groups of three is a common K-map simplification technique. A B True False . . 150. In true sum-of-products expressions, the inversion signs cannot cover more than single variables in a term. A B True False . . 151. A combinatorial logic circuit has memory characteristics that "remember" the inputs after they have been removed. A B True False . . 152. A data selector is also called a demultiplexer. A True . B False .

153. An exclusive-OR gate will invert a signal on one input if the other is always HIGH. A B True False . .

A True .

B False .

## 155. The simplified form of A True .

. B False .

156. The K-map in the figure below shows the correct implementation of the expression X = ACD + AB(CD + BC).

## A True . 159. The simplified form of A True . .

B False .

B False .

160. The carry output of each adder in a ripple adder provides an additional sum output bit. A True . B False .

FINALS 1. Determine the output frequency for a frequency division circuit that contains 12 flip-flops with an input clock frequency of 20.48 MHz. A. B. C. D. 10.24 kHz 5 kHz 30.24 kHz 15 kHz

2. Which statement BEST describes the operation of a negative-edge-triggered D flip-flop? A. The logic level at the D input is transferred to Q on NGT of CLK. B. The Q output is ALWAYS identical to the CLK input if the D input is HIGH. C. The Q output is ALWAYS identical to the D input when CLK = PGT. D. The Q output is ALWAYS identical to the D input. 3 3. Propagation delay time, t , is measured from the ________. PLH . A. triggering edge of the clock pulse to the LOW-to-HIGH transition of the output 3 B. triggering edge of the clock pulse to the HIGH-to-LOW transition of the output .C. preset input to the LOW-to-HIGH transition of the output D. clear input to the HIGH-to-LOW transition of the output 4. How is a J-K flip-flop made to toggle? A. J = 0, K = 0 B. J = 1, K = 0 C. J = 0, K = 1 D. J = 1, K = 1

## 5. How many flip-flops are in the 7475 IC? A. 1 C. 4

B. 2 D. 8

6. How many flip-flops are required to produce a divide-by-128 device? A. 1 B. 4 C. 6 D. 7 7. Which is not an Altera primitive port identifier? A. clk

B. ena

C. clr

D. prn

8. The timing network that sets the output frequency of a 555 astable circuit contains ________. A. three external resistors are used B. two external resistors and an external capacitor are used C. an external resistor and two external capacitors are used D. no external resistor or capacitor is required 9. What is the difference between the enable input of the 7475 and the clock input of the 7474? A. The 7475 is edge-triggered. B. The 7474 is edge-triggered. 10. The phenomenon of interpreting unwanted signals on J and K while C (clock pulse) is HIGH is called ________. p A. parity error checking B. ones catching C. digital discrimination D. digital filtering What is another name for a one-shot? A. Monostable C. Bistable On A. B. C. D. a master-slave flip-flop, when is the master enabled? when the gate is LOW when the gate is HIGH both of the above neither of the above

11.

B. Multivibrator D. Astable

12.

13.

One example of the use of an S-R flip-flop is as a(n): A. racer B. astable oscillator C. binary storage register D. transition pulse generator What is the difference between the 7476 and the 74LS76? A. the 7476 is master-slave, the 74LS76 is master-slave B. the 7476 is edge-triggered, the 74LS76 is edge-triggered C. the 7476 is edge-triggered, the 74LS76 is master-slave D. the 7476 is master-slave, the 74LS76 is edge-triggered Which of the following is correct for a gated D flip-flop? A. The output toggles if one of the inputs is held HIGH. B. Only one of the inputs can be HIGH at a time. C. The output complement follows the input when enabled. D. Q output follows the input D when the enable is HIGH. With regard to a D latch, ________. A. the Q output follows the D input when EN is LOW B. the Q output is opposite the D input when EN is LOW C. the Q output follows the D input when EN is HIGH D. the Q output is HIGH regardless of EN's input state How can the cross-coupled NAND flip-flop be made to have active-HIGH S-R inputs? A. It can't be done. B. Invert the Q outputs. C. Invert the S-R inputs. When is a flip-flop said to be transparent? A. when the Q output is opposite the input B. when the Q output follows the input C. when you can see through the IC packaging

14.

15.

16.

17.

18.

20.

## . Determine C for a pulse width of 2 s. 1

22.

Which of the following is correct for a D latch? A. The output toggles if one of the inputs is held HIGH. B. Q output follows the input D when the enable is HIGH. C. Only one of the inputs can be HIGH at a time. D. The output complement follows the input when enabled.

23.

A J-K flip-flop is in a "no change" condition when ________. A. J = 1, K = 1 B. J = 1, K = 0 C. J = 0, K = 1 D. J = 0, K = 0 A correct output is achieved from a master-slave J-K flip-flop only if its inputs are stable while the: A. clock is LOW B. slave is transferring C. flip-flop is reset D. clock is HIGH

24.

25.

Which of the following describes the operation of a positive edge-triggered D flip-flop? A. If both inputs are HIGH, the output will toggle. B. The output will follow the input on the leading edge of the clock. C. When both inputs are LOW, an invalid state exists. The input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of D. the clock. What does the triangle on the clock input of a J-K flip-flop mean? A. level enabled B. edge-triggered A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is ________. A. constantly LOW B. constantly HIGH C. a 20 kHz square wave D. a 10 kHz square wave

26.

27.

28.

The toggle conditions in a master-slave J-K flip-flop means that Q and A. opposite, active clock edge B. inverted, positive clock edge C. quiescent, negative clock edge D. reset, synchronous clock edge

29.

EXT

of 49 k

and a C

EXT

of 0.2

## F. The pulse width (t

) is W

B. 6.9 ms C. 69 ms D. 690 ms 30. On A. B. C. D. a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________. the clock pulse is LOW the clock pulse is HIGH the clock pulse transitions from LOW to HIGH the clock pulse transitions from HIGH to LOW

31.

What is the hold condition of a flip-flop? A. both S and R inputs activated B. no active S or R input C. only S is active D. only R is active If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the R input goes to 0, the latch will be ________. A. SET B. RESET C. clear D. invalid In VHDL, how many inputs will a primitive JK flip-flop have? A. 2 C. 4

32.

33.

B. 3 D. 5

34.

## F. Determine R for a pulse width of 2 ms. 1

35.

A D flip-flop utilizing a PGT clock is in the CLEAR state. Which of the following input actions will cause it to change states? A. CLK = NGT, D = 0 B. CLK = PGT, D = 0 C. CLOCK NGT, D = 1 D. CLOCK PGT, D = 1 E. CLK = NGT, D = 0, CLOCK NGT, D = 1

37.

In a 555 timer, three 5 k resistors provide a trigger level of ________. A. 1/4 VCC and a threshold level 1/2 VCC B. 1/3 VCC and a threshold level 3/4 VCC C. 1/3 VCC and a threshold level 2/3 VCC D. 1/4 VCC and a threshold level 2/3 VCC Does the cross-coupled NOR flip-flop have active-HIGH or active-LOW set and reset inputs? A. active-HIGH B. active-LOW The circuit that is primarily responsible for certain flip-flops to be designated as edge-triggered is the: A. edge-detection circuit. B. NOR latch. C. NAND latch. D. pulse-steering circuit.

38.

39.

40.

With four J-K flip-flops wired as an asynchronous counter, the first output change of divider #4 indicates a count of how many input clock pulses? A. 16 B. 8 C. 4 D. 2 What is the significance of the J and K terminals on the J-K flip-flop? A. There is no known significance in their designations. B. The J represents "jump," which is how the Q output reacts whenever the clock goes high and the J input is also HIGH. C. The letters were chosen in honor of Jack Kilby, the inventory of the integrated circuit. D. All of the other letters of the alphabet are already in use. Why are the S and R inputs of a gated flip-flop said to be synchronous? A. They must occur with the gate. B. They occur independent of the gate. Gated S-R flip-flops are called asynchronous because the output responds immediately to input changes. A. True B. False Which of the following is not generally associated with flip-flops? A. Hold time B. Propagation delay time C. Interval time D. Set up time

41.

42.

43.

44.

45.

EXT

of 100 k

and a C

EXT

of 0.005

## F. The pulse width is

s C. 160 s D. 32 s 46. Edge-triggered flip-flops must have: A. very fast response times B. at least two inputs to handle rising and falling edges C. positive edge-detection circuits D. negative edge-detection circuits

47.

## . Determine C for a pulse width of 4 ms. 1

48.

What is one disadvantage of an S-R flip-flop? A. It has no enable input. B. It has an invalid state. C. It has no clock input. D. It has only a single output. 49. To completely load and then unload an 8-bit register requires how many clock pulses? A. 2 B. 4 C. 8 D. 16

50.

What is one disadvantage of an S-R flip-flop? A. It has no enable input. B. It has an invalid state. C. It has no clock input. D. It has only a single output. 51. Which of the following best describes the action of pulse-triggered FF's? A. The clock and the S-R inputs must be pulse shaped. B. The data is entered on the leading edge of the clock, and transferred out on the trailing edge of the clock. C. A pulse on the clock transfers data from input to output .D. The synchronous inputs must be pulsed. 52. An invalid condition in the operation of an active-HIGH input S-R latch occurs when ________. A. HIGHs are applied simultaneously to both inputs S and R B. LOWs are applied simultaneously to both inputs S and R C. a LOW is applied to the S input while a HIGH is applied to the R input D. a HIGH is applied to the S input while a LOW is applied to the R input 53. On a J-K flip-flop, when is the flip-flop in a hold condition? A. J = 0, K = 0 B. J = 1, K = 0 C. J = 0, K = 1 D. J = 1, K = 1 54.

The output pulse width for a 555 monostable circuit with R = 3.3 k 1

and C = 0.02 1

F is ________.

A. 7.3

B. 73 C. 7.3 msD. 73 ms

55.

Edge-triggered flip-flops must have: A. very fast response times. B. at least two inputs to handle rising and falling edges. C. a pulse transition detector. D. active-LOW inputs and complemented outputs.

56.

As A. B. C. D.

a general rule for stable flip-flop triggering, the clock pulse rise and fall times must be: very long. very short. at a maximum value to enable the input control signals to stabilize. of no consequence as long as the levels are within the determinate range of value.

57.

A positive edge-triggered D flip-flop will store a 1 when ________. A .the D input is HIGH and the clock transitions from HIGH . to LOW B .the D input is HIGH and the clock transitions . from LOW to HIGH C the D input is HIGH and the clock is LOW . D the D input is HIGH and the clock is HIGH .

58.

If an input is activated by a signal transition, it is ________. A. edge-triggered B. toggle triggered C. clock triggered D. noise triggered

59.

A positive edge-triggered J-K flip-flop is used to produce a two-phase clock. However, when the circuit is operated it produces erratic results. Close examination with a scope reveals the presence of glitches. What causes the glitches, and how might the problem be corrected? A. The PRESET and CLEAR terminals may have been left floating; they should be properly terminated if not being used. The problem is caused by a race condition between the J and K inputs; an inverter should be inserted in one of the B. terminals to correct the problem. A race condition exists between the Q and Q outputs to the AND gate; the AND gate should be replaced with a NAND C. gate. A race condition exists between the clock and the outputs of the flip-flop feeding the AND gate; replace D. the flip-flop with a negative edge-triggered J-K Flip-Flop.

60.

## F. Determine R for a pulse width of 500 ms. 1

C. 4.5 k D. 455 k

61.

Asynchronous inputs will cause the flip-flop to respond immediately with regard to the clock input. A. True B. False Which is not a real advantage of HDL? A. Using higher levels of abstraction B. Tailoring components to exactly fit the needs of the project C. The use of graphical tools D. Using higher levels of abstraction and tailoring components to exactly fit the needs of the project

62.

63.

Two J-K flip-flops with their J-K inputs tied HIGH are cascaded to be used as counters. After four input clock pulses, the binary count is ________. A. 00 B. 11 C. 01 D. 10 Latches constructed with NOR and NAND gates tend to remain in the latched condition due to which configuration feature? A. cross coupling B. gate impedance C. low input voltages D. asynchronous operation In VHDL, how is each instance of a component addressed? A. A name followed by a colon and the name of the library primitive B. A name followed by a semicolon and the component type C. A name followed by the library being used D. A name followed by the component library number The output of a gated S-R flip-flop changes only if the: A. flip-flop is set B. control input data has changed C. flip-flop is reset

64.

65.

66.

D. input data has no change 67. In VHDL, in which declaration section is a COMPONENT declared? A. Architecture B. Library C. Entity D. Port map View Answer Workspace Report Discuss in Forum 68. A gated S-R latch and its associated waveforms are shown below. What, if anything, is wrong and what could be causing the problem?

A. The

output is always low; the circuit is defective. output; the S and Rterminals are reversed.

## B. The Q output should be the complement of the

C. The Q should be following the R input; the R input is defective. D. There is nothing wrong with the circuit. 69.

The output pulse width of a 555 monostable circuit with R 1 = 4.7 k A. 24 s B. 24 ms C. 243 ms D. 243 s

and C1 = 47

F is ________.

View Answer Workspace Report Discuss in Forum 70. If both inputs of an S-R flip-flop are low, what will happen when the clock goes HIGH? A. An invalid state will exist. B. No change will occur in the output. C. The output will toggle. D. The output will reset. View Answer Workspace Report Discuss in Forum 71. The circuit given below fails to function; the inputs are checked with a logic probe and the following indications are obtained: CLK, J1, J2, J3, K1, K2, and K3 are pulsing. Qand are HIGH. and PRE are LOW. What could be causing the problem?

A. There is no problem. B. The clock should be held HIGH. C. The PRE is stuck LOW. D. The CLR is stuck HIGH. 72. A push-button switch is used to input data to a register. The output of the register is erratic. What could be causing the problem? A. The power supply is probably noisy. B. The switch contacts are bouncing. C. The socket contacts on the register IC are corroded. D. The register IC is intermittent and failure is imminent. 73. A 555 timer is connected for astable operation as shown below along with the output waveform. It is determined that the duty cycle should be 0.5. What steps need to be taken to correct the duty cycle, while maintaining the same output frequency? A. Increase the value of C. B. Increase Vcc and decrease RL. C. Decrease R1 and R2. D. Decrease R1 and increase R2. 74. The pulse width of a one-shot circuit is determined by ________. A. a resistor and capacitor B. two resistors C. two capacitors D. none of the above 75. For an S-R flip-flop to be set or reset, the respective input must be: A. installed with steering diodes B. in parallel with a limiting resistor C. LOW D. HIGH

78. Four J-K flip-flops are cascaded with their J-K inputs tied HIGH. If the input frequency (f in) to the first flip-flop is 32 kHz, the output frequency (fout) is ________. A. 1 kHz B. 2 kHz C. 4 kHz D. 16 kHz

79. A gated S-R flip-flop goes into the SET condition when S is HIGH, R is LOW, and EN is HIGH. A. True B. False

80. VHDL does require a special designation for an output with a feedback. A. True 81 B. False

A negative edge-triggered flip-flop will accept inputs only when the clock is LOW. A. True B. False

82. The term CLEAR always means that A. True 83 PRESET and CLEAR inputs are normally synchronous. A. True B. False 84 VHDL was created as a very flexible language and it allows us to define the operation of clocked devices in the code . without relying on logic primitives. A. True 85 B. False . B. False

The Q output of a flip-flop is normally HIGH when the device is in the "CLEAR" or "RESET" state. A. True B. False

86. An astable multivibrator is sometimes referred to as a clock. A. True 87 The 7476 and 74LS76 are both dual flip-flops. A. True B. False B. False

88. The 7475 is an example of an IC D latch (also called a bistable latch) that contains four transparent D latches. A. True B. False